irq/dcn201/irq_service_dcn201.c

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027
0028 #include "include/logger_interface.h"
0029
0030 #include "../dce110/irq_service_dce110.h"
0031
0032 #include "dcn/dcn_2_0_3_offset.h"
0033 #include "dcn/dcn_2_0_3_sh_mask.h"
0034
0035 #include "cyan_skillfish_ip_offset.h"
0036 #include "soc15_hw_ip.h"
0037
0038 #include "irq_service_dcn201.h"
0039
0040 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
0041
0042 static enum dc_irq_source to_dal_irq_source_dcn201(struct irq_service *irq_service,
0043                            uint32_t src_id,
0044                            uint32_t ext_id)
0045 {
0046     switch (src_id) {
0047     case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
0048         return DC_IRQ_SOURCE_VBLANK1;
0049     case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
0050         return DC_IRQ_SOURCE_VBLANK2;
0051     case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
0052         return DC_IRQ_SOURCE_DC1_VLINE0;
0053     case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
0054         return DC_IRQ_SOURCE_DC2_VLINE0;
0055     case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
0056         return DC_IRQ_SOURCE_PFLIP1;
0057     case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
0058         return DC_IRQ_SOURCE_PFLIP2;
0059     case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0060         return DC_IRQ_SOURCE_VUPDATE1;
0061     case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0062         return DC_IRQ_SOURCE_VUPDATE2;
0063     case DCN_1_0__SRCID__DC_HPD1_INT:
0064         /* generic src_id for all HPD and HPDRX interrupts */
0065         switch (ext_id) {
0066         case DCN_1_0__CTXID__DC_HPD1_INT:
0067             return DC_IRQ_SOURCE_HPD1;
0068         case DCN_1_0__CTXID__DC_HPD2_INT:
0069             return DC_IRQ_SOURCE_HPD2;
0070         case DCN_1_0__CTXID__DC_HPD1_RX_INT:
0071             return DC_IRQ_SOURCE_HPD1RX;
0072         case DCN_1_0__CTXID__DC_HPD2_RX_INT:
0073             return DC_IRQ_SOURCE_HPD2RX;
0074         default:
0075             return DC_IRQ_SOURCE_INVALID;
0076         }
0077         break;
0078
0079     default:
0080         return DC_IRQ_SOURCE_INVALID;
0081     }
0082     return DC_IRQ_SOURCE_INVALID;
0083 }
0084
0085 static bool hpd_ack(
0086     struct irq_service *irq_service,
0087     const struct irq_source_info *info)
0088 {
0089     uint32_t addr = info->status_reg;
0090     uint32_t value = dm_read_reg(irq_service->ctx, addr);
0091     uint32_t current_status =
0092         get_reg_field_value(
0093             value,
0094             HPD0_DC_HPD_INT_STATUS,
0095             DC_HPD_SENSE_DELAYED);
0096
0097     dal_irq_service_ack_generic(irq_service, info);
0098
0099     value = dm_read_reg(irq_service->ctx, info->enable_reg);
0100
0101     set_reg_field_value(
0102         value,
0103         current_status ? 0 : 1,
0104         HPD0_DC_HPD_INT_CONTROL,
0105         DC_HPD_INT_POLARITY);
0106
0107     dm_write_reg(irq_service->ctx, info->enable_reg, value);
0108
0109     return true;
0110 }
0111
0112 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
0113     .set = NULL,
0114     .ack = hpd_ack
0115 };
0116
0117 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
0118     .set = NULL,
0119     .ack = NULL
0120 };
0121
0122 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
0123     .set = NULL,
0124     .ack = NULL
0125 };
0126
0127 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
0128     .set = NULL,
0129     .ack = NULL
0130 };
0131
0132 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
0133     .set = NULL,
0134     .ack = NULL
0135 };
0136 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
0137     .set = NULL,
0138     .ack = NULL
0139 };
0140
0141 #undef BASE_INNER
0142 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
0143
0144 #define BASE(seg) BASE_INNER(seg)
0145
0146 /* compile time expand base address. */
0147 #define BASE(seg) \
0148     BASE_INNER(seg)
0149
0150 #define SRI(reg_name, block, id)\
0151     BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0152                     mm ## block ## id ## _ ## reg_name
0153
0154 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
0155     .enable_reg = SRI(reg1, block, reg_num),\
0156     .enable_mask = \
0157         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0158     .enable_value = {\
0159         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0160         ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
0161     },\
0162     .ack_reg = SRI(reg2, block, reg_num),\
0163     .ack_mask = \
0164         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
0165     .ack_value = \
0166         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
0167
0168 #define hpd_int_entry(reg_num)\
0169     [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
0170         IRQ_REG_ENTRY(HPD, reg_num,\
0171             DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
0172             DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
0173         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0174         .funcs = &hpd_irq_info_funcs\
0175     }
0176
0177 #define hpd_rx_int_entry(reg_num)\
0178     [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
0179         IRQ_REG_ENTRY(HPD, reg_num,\
0180             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
0181             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
0182         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0183         .funcs = &hpd_rx_irq_info_funcs\
0184     }
0185 #define pflip_int_entry(reg_num)\
0186     [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
0187         IRQ_REG_ENTRY(HUBPREQ, reg_num,\
0188             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
0189             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
0190         .funcs = &pflip_irq_info_funcs\
0191     }
0192
0193 #define vupdate_int_entry(reg_num)\
0194     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0195         IRQ_REG_ENTRY(OTG, reg_num,\
0196             OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
0197             OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
0198         .funcs = &vblank_irq_info_funcs\
0199     }
0200
0201 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
0202  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
0203  */
0204 #define vupdate_no_lock_int_entry(reg_num)\
0205     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0206         IRQ_REG_ENTRY(OTG, reg_num,\
0207             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
0208             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
0209         .funcs = &vupdate_no_lock_irq_info_funcs\
0210     }
0211 #define vblank_int_entry(reg_num)\
0212     [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
0213         IRQ_REG_ENTRY(OTG, reg_num,\
0214             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
0215             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
0216         .funcs = &vblank_irq_info_funcs\
0217     }
0218
0219 #define vline0_int_entry(reg_num)\
0220     [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
0221         IRQ_REG_ENTRY(OTG, reg_num,\
0222             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
0223             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
0224         .funcs = &vline0_irq_info_funcs\
0225     }
0226
0227 #define dummy_irq_entry() \
0228     {\
0229         .funcs = &dummy_irq_info_funcs\
0230     }
0231
0232 #define i2c_int_entry(reg_num) \
0233     [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
0234
0235 #define dp_sink_int_entry(reg_num) \
0236     [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
0237
0238 #define gpio_pad_int_entry(reg_num) \
0239     [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
0240
0241 #define dc_underflow_int_entry(reg_num) \
0242     [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
0243
0244 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
0245     .set = dal_irq_service_dummy_set,
0246     .ack = dal_irq_service_dummy_ack
0247 };
0248
0249 static const struct irq_source_info
0250 irq_source_info_dcn201[DAL_IRQ_SOURCES_NUMBER] = {
0251     [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
0252     hpd_int_entry(0),
0253     hpd_int_entry(1),
0254     dummy_irq_entry(),
0255     dummy_irq_entry(),
0256     dummy_irq_entry(),
0257     dummy_irq_entry(),
0258     hpd_rx_int_entry(0),
0259     hpd_rx_int_entry(1),
0260     dummy_irq_entry(),
0261     dummy_irq_entry(),
0262     dummy_irq_entry(),
0263     dummy_irq_entry(),
0264     i2c_int_entry(1),
0265     i2c_int_entry(2),
0266     dummy_irq_entry(),
0267     dummy_irq_entry(),
0268     dummy_irq_entry(),
0269     dummy_irq_entry(),
0270     dp_sink_int_entry(1),
0271     dp_sink_int_entry(2),
0272     dummy_irq_entry(),
0273     dummy_irq_entry(),
0274     dummy_irq_entry(),
0275     dummy_irq_entry(),
0276     [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
0277     pflip_int_entry(0),
0278     pflip_int_entry(1),
0279     pflip_int_entry(2),
0280     pflip_int_entry(3),
0281     [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
0282     [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
0283     [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
0284     gpio_pad_int_entry(0),
0285     gpio_pad_int_entry(1),
0286     gpio_pad_int_entry(2),
0287     gpio_pad_int_entry(3),
0288     gpio_pad_int_entry(4),
0289     gpio_pad_int_entry(5),
0290     gpio_pad_int_entry(6),
0291     gpio_pad_int_entry(7),
0292     gpio_pad_int_entry(8),
0293     gpio_pad_int_entry(9),
0294     gpio_pad_int_entry(10),
0295     gpio_pad_int_entry(11),
0296     gpio_pad_int_entry(12),
0297     gpio_pad_int_entry(13),
0298     gpio_pad_int_entry(14),
0299     gpio_pad_int_entry(15),
0300     gpio_pad_int_entry(16),
0301     gpio_pad_int_entry(17),
0302     gpio_pad_int_entry(18),
0303     gpio_pad_int_entry(19),
0304     gpio_pad_int_entry(20),
0305     gpio_pad_int_entry(21),
0306     gpio_pad_int_entry(22),
0307     gpio_pad_int_entry(23),
0308     gpio_pad_int_entry(24),
0309     gpio_pad_int_entry(25),
0310     gpio_pad_int_entry(26),
0311     gpio_pad_int_entry(27),
0312     gpio_pad_int_entry(28),
0313     gpio_pad_int_entry(29),
0314     gpio_pad_int_entry(30),
0315     dc_underflow_int_entry(1),
0316     dc_underflow_int_entry(2),
0317     dummy_irq_entry(),
0318     dummy_irq_entry(),
0319     dummy_irq_entry(),
0320     dummy_irq_entry(),
0321     [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
0322     [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
0323     vupdate_no_lock_int_entry(0),
0324     vupdate_no_lock_int_entry(1),
0325     dummy_irq_entry(),
0326     dummy_irq_entry(),
0327     dummy_irq_entry(),
0328     dummy_irq_entry(),
0329     vblank_int_entry(0),
0330     vblank_int_entry(1),
0331     dummy_irq_entry(),
0332     dummy_irq_entry(),
0333     dummy_irq_entry(),
0334     dummy_irq_entry(),
0335     vline0_int_entry(0),
0336     vline0_int_entry(1),
0337     dummy_irq_entry(),
0338     dummy_irq_entry(),
0339     dummy_irq_entry(),
0340     dummy_irq_entry(),
0341 };
0342
0343 static const struct irq_service_funcs irq_service_funcs_dcn201 = {
0344         .to_dal_irq_source = to_dal_irq_source_dcn201
0345 };
0346
0347 static void dcn201_irq_construct(
0348     struct irq_service *irq_service,
0349     struct irq_service_init_data *init_data)
0350 {
0351     dal_irq_service_construct(irq_service, init_data);
0352
0353     irq_service->info = irq_source_info_dcn201;
0354     irq_service->funcs = &irq_service_funcs_dcn201;
0355 }
0356
0357 struct irq_service *dal_irq_service_dcn201_create(
0358     struct irq_service_init_data *init_data)
0359 {
0360     struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
0361                           GFP_KERNEL);
0362
0363     if (!irq_service)
0364         return NULL;
0365
0366     dcn201_irq_construct(irq_service, init_data);
0367     return irq_service;
0368 }