irq/dcn20/irq_service_dcn20.c

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include <linux/slab.h>
0027
0028 #include "dm_services.h"
0029
0030 #include "include/logger_interface.h"
0031
0032 #include "../dce110/irq_service_dce110.h"
0033
0034 #include "dcn/dcn_2_0_0_offset.h"
0035 #include "dcn/dcn_2_0_0_sh_mask.h"
0036 #include "navi10_ip_offset.h"
0037
0038
0039 #include "irq_service_dcn20.h"
0040
0041 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
0042
0043 static enum dc_irq_source to_dal_irq_source_dcn20(
0044         struct irq_service *irq_service,
0045         uint32_t src_id,
0046         uint32_t ext_id)
0047 {
0048     switch (src_id) {
0049     case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
0050         return DC_IRQ_SOURCE_VBLANK1;
0051     case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
0052         return DC_IRQ_SOURCE_VBLANK2;
0053     case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
0054         return DC_IRQ_SOURCE_VBLANK3;
0055     case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
0056         return DC_IRQ_SOURCE_VBLANK4;
0057     case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
0058         return DC_IRQ_SOURCE_VBLANK5;
0059     case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
0060         return DC_IRQ_SOURCE_VBLANK6;
0061     case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
0062         return DC_IRQ_SOURCE_DC1_VLINE0;
0063     case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
0064         return DC_IRQ_SOURCE_DC2_VLINE0;
0065     case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
0066         return DC_IRQ_SOURCE_DC3_VLINE0;
0067     case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
0068         return DC_IRQ_SOURCE_DC4_VLINE0;
0069     case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
0070         return DC_IRQ_SOURCE_DC5_VLINE0;
0071     case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
0072         return DC_IRQ_SOURCE_DC6_VLINE0;
0073     case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
0074         return DC_IRQ_SOURCE_PFLIP1;
0075     case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
0076         return DC_IRQ_SOURCE_PFLIP2;
0077     case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
0078         return DC_IRQ_SOURCE_PFLIP3;
0079     case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
0080         return DC_IRQ_SOURCE_PFLIP4;
0081     case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
0082         return DC_IRQ_SOURCE_PFLIP5;
0083     case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
0084         return DC_IRQ_SOURCE_PFLIP6;
0085     case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0086         return DC_IRQ_SOURCE_VUPDATE1;
0087     case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0088         return DC_IRQ_SOURCE_VUPDATE2;
0089     case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0090         return DC_IRQ_SOURCE_VUPDATE3;
0091     case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0092         return DC_IRQ_SOURCE_VUPDATE4;
0093     case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0094         return DC_IRQ_SOURCE_VUPDATE5;
0095     case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0096         return DC_IRQ_SOURCE_VUPDATE6;
0097
0098     case DCN_1_0__SRCID__DC_HPD1_INT:
0099         /* generic src_id for all HPD and HPDRX interrupts */
0100         switch (ext_id) {
0101         case DCN_1_0__CTXID__DC_HPD1_INT:
0102             return DC_IRQ_SOURCE_HPD1;
0103         case DCN_1_0__CTXID__DC_HPD2_INT:
0104             return DC_IRQ_SOURCE_HPD2;
0105         case DCN_1_0__CTXID__DC_HPD3_INT:
0106             return DC_IRQ_SOURCE_HPD3;
0107         case DCN_1_0__CTXID__DC_HPD4_INT:
0108             return DC_IRQ_SOURCE_HPD4;
0109         case DCN_1_0__CTXID__DC_HPD5_INT:
0110             return DC_IRQ_SOURCE_HPD5;
0111         case DCN_1_0__CTXID__DC_HPD6_INT:
0112             return DC_IRQ_SOURCE_HPD6;
0113         case DCN_1_0__CTXID__DC_HPD1_RX_INT:
0114             return DC_IRQ_SOURCE_HPD1RX;
0115         case DCN_1_0__CTXID__DC_HPD2_RX_INT:
0116             return DC_IRQ_SOURCE_HPD2RX;
0117         case DCN_1_0__CTXID__DC_HPD3_RX_INT:
0118             return DC_IRQ_SOURCE_HPD3RX;
0119         case DCN_1_0__CTXID__DC_HPD4_RX_INT:
0120             return DC_IRQ_SOURCE_HPD4RX;
0121         case DCN_1_0__CTXID__DC_HPD5_RX_INT:
0122             return DC_IRQ_SOURCE_HPD5RX;
0123         case DCN_1_0__CTXID__DC_HPD6_RX_INT:
0124             return DC_IRQ_SOURCE_HPD6RX;
0125         default:
0126             return DC_IRQ_SOURCE_INVALID;
0127         }
0128         break;
0129
0130     default:
0131         return DC_IRQ_SOURCE_INVALID;
0132     }
0133 }
0134
0135 static bool hpd_ack(
0136     struct irq_service *irq_service,
0137     const struct irq_source_info *info)
0138 {
0139     uint32_t addr = info->status_reg;
0140     uint32_t value = dm_read_reg(irq_service->ctx, addr);
0141     uint32_t current_status =
0142         get_reg_field_value(
0143             value,
0144             HPD0_DC_HPD_INT_STATUS,
0145             DC_HPD_SENSE_DELAYED);
0146
0147     dal_irq_service_ack_generic(irq_service, info);
0148
0149     value = dm_read_reg(irq_service->ctx, info->enable_reg);
0150
0151     set_reg_field_value(
0152         value,
0153         current_status ? 0 : 1,
0154         HPD0_DC_HPD_INT_CONTROL,
0155         DC_HPD_INT_POLARITY);
0156
0157     dm_write_reg(irq_service->ctx, info->enable_reg, value);
0158
0159     return true;
0160 }
0161
0162 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
0163     .set = NULL,
0164     .ack = hpd_ack
0165 };
0166
0167 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
0168     .set = NULL,
0169     .ack = NULL
0170 };
0171
0172 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
0173     .set = NULL,
0174     .ack = NULL
0175 };
0176
0177 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
0178     .set = NULL,
0179     .ack = NULL
0180 };
0181
0182 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
0183     .set = NULL,
0184     .ack = NULL
0185 };
0186
0187 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
0188     .set = NULL,
0189     .ack = NULL
0190 };
0191
0192 #undef BASE_INNER
0193 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0194
0195 /* compile time expand base address. */
0196 #define BASE(seg) \
0197     BASE_INNER(seg)
0198
0199
0200 #define SRI(reg_name, block, id)\
0201     BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0202             mm ## block ## id ## _ ## reg_name
0203
0204
0205 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
0206     .enable_reg = SRI(reg1, block, reg_num),\
0207     .enable_mask = \
0208         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0209     .enable_value = {\
0210         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0211         ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
0212     },\
0213     .ack_reg = SRI(reg2, block, reg_num),\
0214     .ack_mask = \
0215         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
0216     .ack_value = \
0217         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
0218
0219
0220
0221 #define hpd_int_entry(reg_num)\
0222     [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
0223         IRQ_REG_ENTRY(HPD, reg_num,\
0224             DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
0225             DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
0226         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0227         .funcs = &hpd_irq_info_funcs\
0228     }
0229
0230 #define hpd_rx_int_entry(reg_num)\
0231     [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
0232         IRQ_REG_ENTRY(HPD, reg_num,\
0233             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
0234             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
0235         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0236         .funcs = &hpd_rx_irq_info_funcs\
0237     }
0238 #define pflip_int_entry(reg_num)\
0239     [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
0240         IRQ_REG_ENTRY(HUBPREQ, reg_num,\
0241             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
0242             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
0243         .funcs = &pflip_irq_info_funcs\
0244     }
0245
0246 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
0247  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
0248  */
0249 #define vupdate_no_lock_int_entry(reg_num)\
0250     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0251         IRQ_REG_ENTRY(OTG, reg_num,\
0252             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
0253             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
0254         .funcs = &vupdate_no_lock_irq_info_funcs\
0255     }
0256
0257 #define vblank_int_entry(reg_num)\
0258     [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
0259         IRQ_REG_ENTRY(OTG, reg_num,\
0260             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
0261             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
0262         .funcs = &vblank_irq_info_funcs\
0263     }
0264
0265 #define vline0_int_entry(reg_num)\
0266     [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
0267         IRQ_REG_ENTRY(OTG, reg_num,\
0268             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
0269             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
0270         .funcs = &vline0_irq_info_funcs\
0271     }
0272
0273 #define dummy_irq_entry() \
0274     {\
0275         .funcs = &dummy_irq_info_funcs\
0276     }
0277
0278 #define i2c_int_entry(reg_num) \
0279     [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
0280
0281 #define dp_sink_int_entry(reg_num) \
0282     [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
0283
0284 #define gpio_pad_int_entry(reg_num) \
0285     [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
0286
0287 #define dc_underflow_int_entry(reg_num) \
0288     [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
0289
0290 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
0291     .set = dal_irq_service_dummy_set,
0292     .ack = dal_irq_service_dummy_ack
0293 };
0294
0295 static const struct irq_source_info
0296 irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
0297     [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
0298     hpd_int_entry(0),
0299     hpd_int_entry(1),
0300     hpd_int_entry(2),
0301     hpd_int_entry(3),
0302     hpd_int_entry(4),
0303     hpd_int_entry(5),
0304     hpd_rx_int_entry(0),
0305     hpd_rx_int_entry(1),
0306     hpd_rx_int_entry(2),
0307     hpd_rx_int_entry(3),
0308     hpd_rx_int_entry(4),
0309     hpd_rx_int_entry(5),
0310     i2c_int_entry(1),
0311     i2c_int_entry(2),
0312     i2c_int_entry(3),
0313     i2c_int_entry(4),
0314     i2c_int_entry(5),
0315     i2c_int_entry(6),
0316     dp_sink_int_entry(1),
0317     dp_sink_int_entry(2),
0318     dp_sink_int_entry(3),
0319     dp_sink_int_entry(4),
0320     dp_sink_int_entry(5),
0321     dp_sink_int_entry(6),
0322     [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
0323     pflip_int_entry(0),
0324     pflip_int_entry(1),
0325     pflip_int_entry(2),
0326     pflip_int_entry(3),
0327     pflip_int_entry(4),
0328     pflip_int_entry(5),
0329     [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
0330     gpio_pad_int_entry(0),
0331     gpio_pad_int_entry(1),
0332     gpio_pad_int_entry(2),
0333     gpio_pad_int_entry(3),
0334     gpio_pad_int_entry(4),
0335     gpio_pad_int_entry(5),
0336     gpio_pad_int_entry(6),
0337     gpio_pad_int_entry(7),
0338     gpio_pad_int_entry(8),
0339     gpio_pad_int_entry(9),
0340     gpio_pad_int_entry(10),
0341     gpio_pad_int_entry(11),
0342     gpio_pad_int_entry(12),
0343     gpio_pad_int_entry(13),
0344     gpio_pad_int_entry(14),
0345     gpio_pad_int_entry(15),
0346     gpio_pad_int_entry(16),
0347     gpio_pad_int_entry(17),
0348     gpio_pad_int_entry(18),
0349     gpio_pad_int_entry(19),
0350     gpio_pad_int_entry(20),
0351     gpio_pad_int_entry(21),
0352     gpio_pad_int_entry(22),
0353     gpio_pad_int_entry(23),
0354     gpio_pad_int_entry(24),
0355     gpio_pad_int_entry(25),
0356     gpio_pad_int_entry(26),
0357     gpio_pad_int_entry(27),
0358     gpio_pad_int_entry(28),
0359     gpio_pad_int_entry(29),
0360     gpio_pad_int_entry(30),
0361     dc_underflow_int_entry(1),
0362     dc_underflow_int_entry(2),
0363     dc_underflow_int_entry(3),
0364     dc_underflow_int_entry(4),
0365     dc_underflow_int_entry(5),
0366     dc_underflow_int_entry(6),
0367     [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
0368     [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
0369     vupdate_no_lock_int_entry(0),
0370     vupdate_no_lock_int_entry(1),
0371     vupdate_no_lock_int_entry(2),
0372     vupdate_no_lock_int_entry(3),
0373     vupdate_no_lock_int_entry(4),
0374     vupdate_no_lock_int_entry(5),
0375     vblank_int_entry(0),
0376     vblank_int_entry(1),
0377     vblank_int_entry(2),
0378     vblank_int_entry(3),
0379     vblank_int_entry(4),
0380     vblank_int_entry(5),
0381     vline0_int_entry(0),
0382     vline0_int_entry(1),
0383     vline0_int_entry(2),
0384     vline0_int_entry(3),
0385     vline0_int_entry(4),
0386     vline0_int_entry(5),
0387 };
0388
0389 static const struct irq_service_funcs irq_service_funcs_dcn20 = {
0390         .to_dal_irq_source = to_dal_irq_source_dcn20
0391 };
0392
0393 static void dcn20_irq_construct(
0394     struct irq_service *irq_service,
0395     struct irq_service_init_data *init_data)
0396 {
0397     dal_irq_service_construct(irq_service, init_data);
0398
0399     irq_service->info = irq_source_info_dcn20;
0400     irq_service->funcs = &irq_service_funcs_dcn20;
0401 }
0402
0403 struct irq_service *dal_irq_service_dcn20_create(
0404     struct irq_service_init_data *init_data)
0405 {
0406     struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
0407                           GFP_KERNEL);
0408
0409     if (!irq_service)
0410         return NULL;
0411
0412     dcn20_irq_construct(irq_service, init_data);
0413     return irq_service;
0414 }