irq/dcn10/irq_service_dcn10.c

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027
0028 #include "include/logger_interface.h"
0029
0030 #include "../dce110/irq_service_dce110.h"
0031
0032 #include "dcn/dcn_1_0_offset.h"
0033 #include "dcn/dcn_1_0_sh_mask.h"
0034 #include "soc15_hw_ip.h"
0035 #include "vega10_ip_offset.h"
0036
0037 #include "irq_service_dcn10.h"
0038
0039 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
0040
0041 static enum dc_irq_source to_dal_irq_source_dcn10(struct irq_service *irq_service,
0042                           uint32_t src_id,
0043                           uint32_t ext_id)
0044 {
0045     switch (src_id) {
0046     case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
0047         return DC_IRQ_SOURCE_VBLANK1;
0048     case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
0049         return DC_IRQ_SOURCE_VBLANK2;
0050     case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
0051         return DC_IRQ_SOURCE_VBLANK3;
0052     case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
0053         return DC_IRQ_SOURCE_VBLANK4;
0054     case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
0055         return DC_IRQ_SOURCE_VBLANK5;
0056     case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
0057         return DC_IRQ_SOURCE_VBLANK6;
0058     case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
0059         return DC_IRQ_SOURCE_DC1_VLINE0;
0060     case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
0061         return DC_IRQ_SOURCE_DC2_VLINE0;
0062     case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
0063         return DC_IRQ_SOURCE_DC3_VLINE0;
0064     case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
0065         return DC_IRQ_SOURCE_DC4_VLINE0;
0066     case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
0067         return DC_IRQ_SOURCE_DC5_VLINE0;
0068     case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
0069         return DC_IRQ_SOURCE_DC6_VLINE0;
0070     case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0071         return DC_IRQ_SOURCE_VUPDATE1;
0072     case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0073         return DC_IRQ_SOURCE_VUPDATE2;
0074     case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0075         return DC_IRQ_SOURCE_VUPDATE3;
0076     case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0077         return DC_IRQ_SOURCE_VUPDATE4;
0078     case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0079         return DC_IRQ_SOURCE_VUPDATE5;
0080     case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0081         return DC_IRQ_SOURCE_VUPDATE6;
0082     case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
0083         return DC_IRQ_SOURCE_PFLIP1;
0084     case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
0085         return DC_IRQ_SOURCE_PFLIP2;
0086     case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
0087         return DC_IRQ_SOURCE_PFLIP3;
0088     case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
0089         return DC_IRQ_SOURCE_PFLIP4;
0090     case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
0091         return DC_IRQ_SOURCE_PFLIP5;
0092     case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
0093         return DC_IRQ_SOURCE_PFLIP6;
0094
0095     case DCN_1_0__SRCID__DC_HPD1_INT:
0096         /* generic src_id for all HPD and HPDRX interrupts */
0097         switch (ext_id) {
0098         case DCN_1_0__CTXID__DC_HPD1_INT:
0099             return DC_IRQ_SOURCE_HPD1;
0100         case DCN_1_0__CTXID__DC_HPD2_INT:
0101             return DC_IRQ_SOURCE_HPD2;
0102         case DCN_1_0__CTXID__DC_HPD3_INT:
0103             return DC_IRQ_SOURCE_HPD3;
0104         case DCN_1_0__CTXID__DC_HPD4_INT:
0105             return DC_IRQ_SOURCE_HPD4;
0106         case DCN_1_0__CTXID__DC_HPD5_INT:
0107             return DC_IRQ_SOURCE_HPD5;
0108         case DCN_1_0__CTXID__DC_HPD6_INT:
0109             return DC_IRQ_SOURCE_HPD6;
0110         case DCN_1_0__CTXID__DC_HPD1_RX_INT:
0111             return DC_IRQ_SOURCE_HPD1RX;
0112         case DCN_1_0__CTXID__DC_HPD2_RX_INT:
0113             return DC_IRQ_SOURCE_HPD2RX;
0114         case DCN_1_0__CTXID__DC_HPD3_RX_INT:
0115             return DC_IRQ_SOURCE_HPD3RX;
0116         case DCN_1_0__CTXID__DC_HPD4_RX_INT:
0117             return DC_IRQ_SOURCE_HPD4RX;
0118         case DCN_1_0__CTXID__DC_HPD5_RX_INT:
0119             return DC_IRQ_SOURCE_HPD5RX;
0120         case DCN_1_0__CTXID__DC_HPD6_RX_INT:
0121             return DC_IRQ_SOURCE_HPD6RX;
0122         default:
0123             return DC_IRQ_SOURCE_INVALID;
0124         }
0125         break;
0126
0127     default:
0128         return DC_IRQ_SOURCE_INVALID;
0129     }
0130 }
0131
0132 static bool hpd_ack(
0133     struct irq_service *irq_service,
0134     const struct irq_source_info *info)
0135 {
0136     uint32_t addr = info->status_reg;
0137     uint32_t value = dm_read_reg(irq_service->ctx, addr);
0138     uint32_t current_status =
0139         get_reg_field_value(
0140             value,
0141             HPD0_DC_HPD_INT_STATUS,
0142             DC_HPD_SENSE_DELAYED);
0143
0144     dal_irq_service_ack_generic(irq_service, info);
0145
0146     value = dm_read_reg(irq_service->ctx, info->enable_reg);
0147
0148     set_reg_field_value(
0149         value,
0150         current_status ? 0 : 1,
0151         HPD0_DC_HPD_INT_CONTROL,
0152         DC_HPD_INT_POLARITY);
0153
0154     dm_write_reg(irq_service->ctx, info->enable_reg, value);
0155
0156     return true;
0157 }
0158
0159 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
0160     .set = NULL,
0161     .ack = hpd_ack
0162 };
0163
0164 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
0165     .set = NULL,
0166     .ack = NULL
0167 };
0168
0169 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
0170     .set = NULL,
0171     .ack = NULL
0172 };
0173
0174 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
0175     .set = NULL,
0176     .ack = NULL
0177 };
0178
0179 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
0180     .set = NULL,
0181     .ack = NULL
0182 };
0183
0184 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
0185     .set = NULL,
0186     .ack = NULL
0187 };
0188
0189 #define BASE_INNER(seg) \
0190     DCE_BASE__INST0_SEG ## seg
0191
0192 #define BASE(seg) \
0193     BASE_INNER(seg)
0194
0195 #define SRI(reg_name, block, id)\
0196     BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0197             mm ## block ## id ## _ ## reg_name
0198
0199
0200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
0201     .enable_reg = SRI(reg1, block, reg_num),\
0202     .enable_mask = \
0203         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0204     .enable_value = {\
0205         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0206         ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
0207     },\
0208     .ack_reg = SRI(reg2, block, reg_num),\
0209     .ack_mask = \
0210         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
0211     .ack_value = \
0212         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
0213
0214 #define hpd_int_entry(reg_num)\
0215     [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
0216         IRQ_REG_ENTRY(HPD, reg_num,\
0217             DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
0218             DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
0219         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0220         .funcs = &hpd_irq_info_funcs\
0221     }
0222
0223 #define hpd_rx_int_entry(reg_num)\
0224     [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
0225         IRQ_REG_ENTRY(HPD, reg_num,\
0226             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
0227             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
0228         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0229         .funcs = &hpd_rx_irq_info_funcs\
0230     }
0231 #define pflip_int_entry(reg_num)\
0232     [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
0233         IRQ_REG_ENTRY(HUBPREQ, reg_num,\
0234             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
0235             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
0236         .funcs = &pflip_irq_info_funcs\
0237     }
0238
0239 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
0240  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
0241  */
0242 #define vupdate_no_lock_int_entry(reg_num)\
0243     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0244         IRQ_REG_ENTRY(OTG, reg_num,\
0245             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
0246             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
0247         .funcs = &vupdate_no_lock_irq_info_funcs\
0248     }
0249
0250 #define vblank_int_entry(reg_num)\
0251     [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
0252         IRQ_REG_ENTRY(OTG, reg_num,\
0253             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
0254             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
0255         .funcs = &vblank_irq_info_funcs\
0256     }
0257
0258 #define vline0_int_entry(reg_num)\
0259     [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
0260         IRQ_REG_ENTRY(OTG, reg_num,\
0261             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
0262             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
0263         .funcs = &vline0_irq_info_funcs\
0264     }
0265
0266 #define dummy_irq_entry() \
0267     {\
0268         .funcs = &dummy_irq_info_funcs\
0269     }
0270
0271 #define i2c_int_entry(reg_num) \
0272     [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
0273
0274 #define dp_sink_int_entry(reg_num) \
0275     [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
0276
0277 #define gpio_pad_int_entry(reg_num) \
0278     [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
0279
0280 #define dc_underflow_int_entry(reg_num) \
0281     [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
0282
0283 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
0284     .set = dal_irq_service_dummy_set,
0285     .ack = dal_irq_service_dummy_ack
0286 };
0287
0288 static const struct irq_source_info
0289 irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = {
0290     [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
0291     hpd_int_entry(0),
0292     hpd_int_entry(1),
0293     hpd_int_entry(2),
0294     hpd_int_entry(3),
0295     hpd_int_entry(4),
0296     hpd_int_entry(5),
0297     hpd_rx_int_entry(0),
0298     hpd_rx_int_entry(1),
0299     hpd_rx_int_entry(2),
0300     hpd_rx_int_entry(3),
0301     hpd_rx_int_entry(4),
0302     hpd_rx_int_entry(5),
0303     i2c_int_entry(1),
0304     i2c_int_entry(2),
0305     i2c_int_entry(3),
0306     i2c_int_entry(4),
0307     i2c_int_entry(5),
0308     i2c_int_entry(6),
0309     dp_sink_int_entry(1),
0310     dp_sink_int_entry(2),
0311     dp_sink_int_entry(3),
0312     dp_sink_int_entry(4),
0313     dp_sink_int_entry(5),
0314     dp_sink_int_entry(6),
0315     [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
0316     pflip_int_entry(0),
0317     pflip_int_entry(1),
0318     pflip_int_entry(2),
0319     pflip_int_entry(3),
0320     [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
0321     [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
0322     [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
0323     gpio_pad_int_entry(0),
0324     gpio_pad_int_entry(1),
0325     gpio_pad_int_entry(2),
0326     gpio_pad_int_entry(3),
0327     gpio_pad_int_entry(4),
0328     gpio_pad_int_entry(5),
0329     gpio_pad_int_entry(6),
0330     gpio_pad_int_entry(7),
0331     gpio_pad_int_entry(8),
0332     gpio_pad_int_entry(9),
0333     gpio_pad_int_entry(10),
0334     gpio_pad_int_entry(11),
0335     gpio_pad_int_entry(12),
0336     gpio_pad_int_entry(13),
0337     gpio_pad_int_entry(14),
0338     gpio_pad_int_entry(15),
0339     gpio_pad_int_entry(16),
0340     gpio_pad_int_entry(17),
0341     gpio_pad_int_entry(18),
0342     gpio_pad_int_entry(19),
0343     gpio_pad_int_entry(20),
0344     gpio_pad_int_entry(21),
0345     gpio_pad_int_entry(22),
0346     gpio_pad_int_entry(23),
0347     gpio_pad_int_entry(24),
0348     gpio_pad_int_entry(25),
0349     gpio_pad_int_entry(26),
0350     gpio_pad_int_entry(27),
0351     gpio_pad_int_entry(28),
0352     gpio_pad_int_entry(29),
0353     gpio_pad_int_entry(30),
0354     dc_underflow_int_entry(1),
0355     dc_underflow_int_entry(2),
0356     dc_underflow_int_entry(3),
0357     dc_underflow_int_entry(4),
0358     dc_underflow_int_entry(5),
0359     dc_underflow_int_entry(6),
0360     [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
0361     [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
0362     vupdate_no_lock_int_entry(0),
0363     vupdate_no_lock_int_entry(1),
0364     vupdate_no_lock_int_entry(2),
0365     vupdate_no_lock_int_entry(3),
0366     vupdate_no_lock_int_entry(4),
0367     vupdate_no_lock_int_entry(5),
0368     vblank_int_entry(0),
0369     vblank_int_entry(1),
0370     vblank_int_entry(2),
0371     vblank_int_entry(3),
0372     vblank_int_entry(4),
0373     vblank_int_entry(5),
0374     vline0_int_entry(0),
0375     vline0_int_entry(1),
0376     vline0_int_entry(2),
0377     vline0_int_entry(3),
0378     vline0_int_entry(4),
0379     vline0_int_entry(5),
0380 };
0381
0382 static const struct irq_service_funcs irq_service_funcs_dcn10 = {
0383         .to_dal_irq_source = to_dal_irq_source_dcn10
0384 };
0385
0386 static void dcn10_irq_construct(
0387     struct irq_service *irq_service,
0388     struct irq_service_init_data *init_data)
0389 {
0390     dal_irq_service_construct(irq_service, init_data);
0391
0392     irq_service->info = irq_source_info_dcn10;
0393     irq_service->funcs = &irq_service_funcs_dcn10;
0394 }
0395
0396 struct irq_service *dal_irq_service_dcn10_create(
0397     struct irq_service_init_data *init_data)
0398 {
0399     struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
0400                           GFP_KERNEL);
0401
0402     if (!irq_service)
0403         return NULL;
0404
0405     dcn10_irq_construct(irq_service, init_data);
0406     return irq_service;
0407 }