irq/dce80/irq_service_dce80.c

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027
0028 #include "include/logger_interface.h"
0029
0030 #include "irq_service_dce80.h"
0031 #include "../dce110/irq_service_dce110.h"
0032
0033 #include "dce/dce_8_0_d.h"
0034 #include "dce/dce_8_0_sh_mask.h"
0035
0036 #include "ivsrcid/ivsrcid_vislands30.h"
0037
0038 #include "dc_types.h"
0039
0040 static bool hpd_ack(
0041     struct irq_service *irq_service,
0042     const struct irq_source_info *info)
0043 {
0044     uint32_t addr = info->status_reg;
0045     uint32_t value = dm_read_reg(irq_service->ctx, addr);
0046     uint32_t current_status =
0047         get_reg_field_value(
0048             value,
0049             DC_HPD1_INT_STATUS,
0050             DC_HPD1_SENSE_DELAYED);
0051
0052     dal_irq_service_ack_generic(irq_service, info);
0053
0054     value = dm_read_reg(irq_service->ctx, info->enable_reg);
0055
0056     set_reg_field_value(
0057         value,
0058         current_status ? 0 : 1,
0059         DC_HPD1_INT_CONTROL,
0060         DC_HPD1_INT_POLARITY);
0061
0062     dm_write_reg(irq_service->ctx, info->enable_reg, value);
0063
0064     return true;
0065 }
0066
0067 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
0068     .set = NULL,
0069     .ack = hpd_ack
0070 };
0071
0072 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
0073     .set = NULL,
0074     .ack = NULL
0075 };
0076
0077 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
0078     .set = NULL,
0079     .ack = NULL
0080 };
0081
0082 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
0083     .set = dce110_vblank_set,
0084     .ack = NULL
0085 };
0086
0087 static const struct irq_source_info_funcs vupdate_irq_info_funcs = {
0088     .set = NULL,
0089     .ack = NULL
0090 };
0091
0092 #define hpd_int_entry(reg_num)\
0093     [DC_IRQ_SOURCE_INVALID + reg_num] = {\
0094         .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
0095         .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
0096         .enable_value = {\
0097             DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
0098             ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
0099         },\
0100         .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
0101         .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
0102         .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
0103         .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
0104         .funcs = &hpd_irq_info_funcs\
0105     }
0106
0107 #define hpd_rx_int_entry(reg_num)\
0108     [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
0109         .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
0110         .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
0111         .enable_value = {\
0112                 DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
0113             ~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
0114         .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
0115         .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
0116         .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
0117         .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
0118         .funcs = &hpd_rx_irq_info_funcs\
0119     }
0120
0121 #define pflip_int_entry(reg_num)\
0122     [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
0123         .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
0124         .enable_mask =\
0125         GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
0126         .enable_value = {\
0127             GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
0128             ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
0129         .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
0130         .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
0131         .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
0132         .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
0133         .funcs = &pflip_irq_info_funcs\
0134     }
0135
0136 #define vupdate_int_entry(reg_num)\
0137     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0138         .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
0139         .enable_mask =\
0140         CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
0141         .enable_value = {\
0142             CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
0143             ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
0144         .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
0145         .ack_mask =\
0146         CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
0147         .ack_value =\
0148         CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
0149         .funcs = &vupdate_irq_info_funcs\
0150     }
0151
0152 #define vblank_int_entry(reg_num)\
0153     [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
0154         .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
0155         .enable_mask =\
0156         CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
0157         .enable_value = {\
0158             CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
0159             ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
0160         .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
0161         .ack_mask =\
0162         CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
0163         .ack_value =\
0164         CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
0165         .funcs = &vblank_irq_info_funcs,\
0166         .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
0167     }
0168
0169 #define dummy_irq_entry() \
0170     {\
0171         .funcs = &dummy_irq_info_funcs\
0172     }
0173
0174 #define i2c_int_entry(reg_num) \
0175     [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
0176
0177 #define dp_sink_int_entry(reg_num) \
0178     [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
0179
0180 #define gpio_pad_int_entry(reg_num) \
0181     [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
0182
0183 #define dc_underflow_int_entry(reg_num) \
0184     [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
0185
0186
0187 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
0188     .set = dal_irq_service_dummy_set,
0189     .ack = dal_irq_service_dummy_ack
0190 };
0191
0192 static const struct irq_source_info
0193 irq_source_info_dce80[DAL_IRQ_SOURCES_NUMBER] = {
0194     [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
0195     hpd_int_entry(1),
0196     hpd_int_entry(2),
0197     hpd_int_entry(3),
0198     hpd_int_entry(4),
0199     hpd_int_entry(5),
0200     hpd_int_entry(6),
0201     hpd_rx_int_entry(1),
0202     hpd_rx_int_entry(2),
0203     hpd_rx_int_entry(3),
0204     hpd_rx_int_entry(4),
0205     hpd_rx_int_entry(5),
0206     hpd_rx_int_entry(6),
0207     i2c_int_entry(1),
0208     i2c_int_entry(2),
0209     i2c_int_entry(3),
0210     i2c_int_entry(4),
0211     i2c_int_entry(5),
0212     i2c_int_entry(6),
0213     dp_sink_int_entry(1),
0214     dp_sink_int_entry(2),
0215     dp_sink_int_entry(3),
0216     dp_sink_int_entry(4),
0217     dp_sink_int_entry(5),
0218     dp_sink_int_entry(6),
0219     [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
0220     pflip_int_entry(0),
0221     pflip_int_entry(1),
0222     pflip_int_entry(2),
0223     pflip_int_entry(3),
0224     pflip_int_entry(4),
0225     pflip_int_entry(5),
0226     [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
0227     gpio_pad_int_entry(0),
0228     gpio_pad_int_entry(1),
0229     gpio_pad_int_entry(2),
0230     gpio_pad_int_entry(3),
0231     gpio_pad_int_entry(4),
0232     gpio_pad_int_entry(5),
0233     gpio_pad_int_entry(6),
0234     gpio_pad_int_entry(7),
0235     gpio_pad_int_entry(8),
0236     gpio_pad_int_entry(9),
0237     gpio_pad_int_entry(10),
0238     gpio_pad_int_entry(11),
0239     gpio_pad_int_entry(12),
0240     gpio_pad_int_entry(13),
0241     gpio_pad_int_entry(14),
0242     gpio_pad_int_entry(15),
0243     gpio_pad_int_entry(16),
0244     gpio_pad_int_entry(17),
0245     gpio_pad_int_entry(18),
0246     gpio_pad_int_entry(19),
0247     gpio_pad_int_entry(20),
0248     gpio_pad_int_entry(21),
0249     gpio_pad_int_entry(22),
0250     gpio_pad_int_entry(23),
0251     gpio_pad_int_entry(24),
0252     gpio_pad_int_entry(25),
0253     gpio_pad_int_entry(26),
0254     gpio_pad_int_entry(27),
0255     gpio_pad_int_entry(28),
0256     gpio_pad_int_entry(29),
0257     gpio_pad_int_entry(30),
0258     dc_underflow_int_entry(1),
0259     dc_underflow_int_entry(2),
0260     dc_underflow_int_entry(3),
0261     dc_underflow_int_entry(4),
0262     dc_underflow_int_entry(5),
0263     dc_underflow_int_entry(6),
0264     [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
0265     [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
0266     vupdate_int_entry(0),
0267     vupdate_int_entry(1),
0268     vupdate_int_entry(2),
0269     vupdate_int_entry(3),
0270     vupdate_int_entry(4),
0271     vupdate_int_entry(5),
0272     vblank_int_entry(0),
0273     vblank_int_entry(1),
0274     vblank_int_entry(2),
0275     vblank_int_entry(3),
0276     vblank_int_entry(4),
0277     vblank_int_entry(5),
0278 };
0279
0280 static const struct irq_service_funcs irq_service_funcs_dce80 = {
0281         .to_dal_irq_source = to_dal_irq_source_dce110
0282 };
0283
0284 static void dce80_irq_construct(
0285     struct irq_service *irq_service,
0286     struct irq_service_init_data *init_data)
0287 {
0288     dal_irq_service_construct(irq_service, init_data);
0289
0290     irq_service->info = irq_source_info_dce80;
0291     irq_service->funcs = &irq_service_funcs_dce80;
0292 }
0293
0294 struct irq_service *dal_irq_service_dce80_create(
0295     struct irq_service_init_data *init_data)
0296 {
0297     struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
0298                           GFP_KERNEL);
0299
0300     if (!irq_service)
0301         return NULL;
0302
0303     dce80_irq_construct(irq_service, init_data);
0304     return irq_service;
0305 }
0306
0307