irq/dce120/irq_service_dce120.c

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027
0028 #include "include/logger_interface.h"
0029
0030 #include "irq_service_dce120.h"
0031 #include "../dce110/irq_service_dce110.h"
0032
0033 #include "dce/dce_12_0_offset.h"
0034 #include "dce/dce_12_0_sh_mask.h"
0035 #include "soc15_hw_ip.h"
0036 #include "vega10_ip_offset.h"
0037
0038 #include "ivsrcid/ivsrcid_vislands30.h"
0039
0040 static bool hpd_ack(
0041     struct irq_service *irq_service,
0042     const struct irq_source_info *info)
0043 {
0044     uint32_t addr = info->status_reg;
0045     uint32_t value = dm_read_reg(irq_service->ctx, addr);
0046     uint32_t current_status =
0047         get_reg_field_value(
0048             value,
0049             HPD0_DC_HPD_INT_STATUS,
0050             DC_HPD_SENSE_DELAYED);
0051
0052     dal_irq_service_ack_generic(irq_service, info);
0053
0054     value = dm_read_reg(irq_service->ctx, info->enable_reg);
0055
0056     set_reg_field_value(
0057         value,
0058         current_status ? 0 : 1,
0059         HPD0_DC_HPD_INT_CONTROL,
0060         DC_HPD_INT_POLARITY);
0061
0062     dm_write_reg(irq_service->ctx, info->enable_reg, value);
0063
0064     return true;
0065 }
0066
0067 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
0068     .set = NULL,
0069     .ack = hpd_ack
0070 };
0071
0072 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
0073     .set = NULL,
0074     .ack = NULL
0075 };
0076
0077 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
0078     .set = NULL,
0079     .ack = NULL
0080 };
0081
0082 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
0083     .set = dce110_vblank_set,
0084     .ack = NULL
0085 };
0086
0087 static const struct irq_source_info_funcs vupdate_irq_info_funcs = {
0088     .set = NULL,
0089     .ack = NULL
0090 };
0091
0092 #define BASE_INNER(seg) \
0093     DCE_BASE__INST0_SEG ## seg
0094
0095 #define BASE(seg) \
0096     BASE_INNER(seg)
0097
0098 #define SRI(reg_name, block, id)\
0099     BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0100             mm ## block ## id ## _ ## reg_name
0101
0102
0103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
0104     .enable_reg = SRI(reg1, block, reg_num),\
0105     .enable_mask = \
0106         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0107     .enable_value = {\
0108         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0109         ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
0110     },\
0111     .ack_reg = SRI(reg2, block, reg_num),\
0112     .ack_mask = \
0113         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
0114     .ack_value = \
0115         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
0116
0117 #define hpd_int_entry(reg_num)\
0118     [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
0119         IRQ_REG_ENTRY(HPD, reg_num,\
0120             DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
0121             DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
0122         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0123         .funcs = &hpd_irq_info_funcs\
0124     }
0125
0126 #define hpd_rx_int_entry(reg_num)\
0127     [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
0128         IRQ_REG_ENTRY(HPD, reg_num,\
0129             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
0130             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
0131         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0132         .funcs = &hpd_rx_irq_info_funcs\
0133     }
0134 #define pflip_int_entry(reg_num)\
0135     [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
0136         IRQ_REG_ENTRY(DCP, reg_num, \
0137             GRPH_INTERRUPT_CONTROL, GRPH_PFLIP_INT_MASK, \
0138             GRPH_INTERRUPT_STATUS, GRPH_PFLIP_INT_CLEAR),\
0139         .status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
0140         .funcs = &pflip_irq_info_funcs\
0141     }
0142
0143 #define vupdate_int_entry(reg_num)\
0144     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0145         IRQ_REG_ENTRY(CRTC, reg_num,\
0146             CRTC_INTERRUPT_CONTROL, CRTC_V_UPDATE_INT_MSK,\
0147             CRTC_V_UPDATE_INT_STATUS, CRTC_V_UPDATE_INT_CLEAR),\
0148         .funcs = &vupdate_irq_info_funcs\
0149     }
0150
0151 #define vblank_int_entry(reg_num)\
0152     [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
0153         IRQ_REG_ENTRY(CRTC, reg_num,\
0154                 CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_INT_ENABLE,\
0155                 CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_CLEAR),\
0156         .funcs = &vblank_irq_info_funcs,\
0157         .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
0158     }
0159
0160 #define dummy_irq_entry() \
0161     {\
0162         .funcs = &dummy_irq_info_funcs\
0163     }
0164
0165 #define i2c_int_entry(reg_num) \
0166     [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
0167
0168 #define dp_sink_int_entry(reg_num) \
0169     [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
0170
0171 #define gpio_pad_int_entry(reg_num) \
0172     [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
0173
0174 #define dc_underflow_int_entry(reg_num) \
0175     [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
0176
0177 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
0178     .set = dal_irq_service_dummy_set,
0179     .ack = dal_irq_service_dummy_ack
0180 };
0181
0182 static const struct irq_source_info
0183 irq_source_info_dce120[DAL_IRQ_SOURCES_NUMBER] = {
0184     [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
0185     hpd_int_entry(0),
0186     hpd_int_entry(1),
0187     hpd_int_entry(2),
0188     hpd_int_entry(3),
0189     hpd_int_entry(4),
0190     hpd_int_entry(5),
0191     hpd_rx_int_entry(0),
0192     hpd_rx_int_entry(1),
0193     hpd_rx_int_entry(2),
0194     hpd_rx_int_entry(3),
0195     hpd_rx_int_entry(4),
0196     hpd_rx_int_entry(5),
0197     i2c_int_entry(1),
0198     i2c_int_entry(2),
0199     i2c_int_entry(3),
0200     i2c_int_entry(4),
0201     i2c_int_entry(5),
0202     i2c_int_entry(6),
0203     dp_sink_int_entry(1),
0204     dp_sink_int_entry(2),
0205     dp_sink_int_entry(3),
0206     dp_sink_int_entry(4),
0207     dp_sink_int_entry(5),
0208     dp_sink_int_entry(6),
0209     [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
0210     pflip_int_entry(0),
0211     pflip_int_entry(1),
0212     pflip_int_entry(2),
0213     pflip_int_entry(3),
0214     pflip_int_entry(4),
0215     pflip_int_entry(5),
0216     [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
0217     gpio_pad_int_entry(0),
0218     gpio_pad_int_entry(1),
0219     gpio_pad_int_entry(2),
0220     gpio_pad_int_entry(3),
0221     gpio_pad_int_entry(4),
0222     gpio_pad_int_entry(5),
0223     gpio_pad_int_entry(6),
0224     gpio_pad_int_entry(7),
0225     gpio_pad_int_entry(8),
0226     gpio_pad_int_entry(9),
0227     gpio_pad_int_entry(10),
0228     gpio_pad_int_entry(11),
0229     gpio_pad_int_entry(12),
0230     gpio_pad_int_entry(13),
0231     gpio_pad_int_entry(14),
0232     gpio_pad_int_entry(15),
0233     gpio_pad_int_entry(16),
0234     gpio_pad_int_entry(17),
0235     gpio_pad_int_entry(18),
0236     gpio_pad_int_entry(19),
0237     gpio_pad_int_entry(20),
0238     gpio_pad_int_entry(21),
0239     gpio_pad_int_entry(22),
0240     gpio_pad_int_entry(23),
0241     gpio_pad_int_entry(24),
0242     gpio_pad_int_entry(25),
0243     gpio_pad_int_entry(26),
0244     gpio_pad_int_entry(27),
0245     gpio_pad_int_entry(28),
0246     gpio_pad_int_entry(29),
0247     gpio_pad_int_entry(30),
0248     dc_underflow_int_entry(1),
0249     dc_underflow_int_entry(2),
0250     dc_underflow_int_entry(3),
0251     dc_underflow_int_entry(4),
0252     dc_underflow_int_entry(5),
0253     dc_underflow_int_entry(6),
0254     [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
0255     [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
0256     vupdate_int_entry(0),
0257     vupdate_int_entry(1),
0258     vupdate_int_entry(2),
0259     vupdate_int_entry(3),
0260     vupdate_int_entry(4),
0261     vupdate_int_entry(5),
0262     vblank_int_entry(0),
0263     vblank_int_entry(1),
0264     vblank_int_entry(2),
0265     vblank_int_entry(3),
0266     vblank_int_entry(4),
0267     vblank_int_entry(5),
0268 };
0269
0270 static const struct irq_service_funcs irq_service_funcs_dce120 = {
0271         .to_dal_irq_source = to_dal_irq_source_dce110
0272 };
0273
0274 static void dce120_irq_construct(
0275     struct irq_service *irq_service,
0276     struct irq_service_init_data *init_data)
0277 {
0278     dal_irq_service_construct(irq_service, init_data);
0279
0280     irq_service->info = irq_source_info_dce120;
0281     irq_service->funcs = &irq_service_funcs_dce120;
0282 }
0283
0284 struct irq_service *dal_irq_service_dce120_create(
0285     struct irq_service_init_data *init_data)
0286 {
0287     struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
0288                           GFP_KERNEL);
0289
0290     if (!irq_service)
0291         return NULL;
0292
0293     dce120_irq_construct(irq_service, init_data);
0294     return irq_service;
0295 }