dc/inc/resource.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  */
0024
0025 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_
0026 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_
0027
0028 #include "core_types.h"
0029 #include "core_status.h"
0030 #include "dal_asic_id.h"
0031 #include "dm_pp_smu.h"
0032
0033 #define MEMORY_TYPE_MULTIPLIER_CZ 4
0034 #define MEMORY_TYPE_HBM 2
0035
0036
0037 #define IS_PIPE_SYNCD_VALID(pipe) ((((pipe)->pipe_idx_syncd) & 0x80)?1:0)
0038 #define GET_PIPE_SYNCD_FROM_PIPE(pipe) ((pipe)->pipe_idx_syncd & 0x7F)
0039 #define SET_PIPE_SYNCD_TO_PIPE(pipe, pipe_syncd) ((pipe)->pipe_idx_syncd = (0x80 | pipe_syncd))
0040
0041 enum dce_version resource_parse_asic_id(
0042         struct hw_asic_id asic_id);
0043
0044 struct resource_caps {
0045     int num_timing_generator;
0046     int num_opp;
0047     int num_video_plane;
0048     int num_audio;
0049     int num_stream_encoder;
0050     int num_pll;
0051     int num_dwb;
0052     int num_ddc;
0053     int num_vmid;
0054     int num_dsc;
0055     unsigned int num_dig_link_enc; // Total number of DIGs (digital encoders) in DIO (Display Input/Output).
0056     unsigned int num_usb4_dpia; // Total number of USB4 DPIA (DisplayPort Input Adapters).
0057     int num_hpo_dp_stream_encoder;
0058     int num_hpo_dp_link_encoder;
0059     int num_mpc_3dlut;
0060 };
0061
0062 struct resource_straps {
0063     uint32_t hdmi_disable;
0064     uint32_t dc_pinstraps_audio;
0065     uint32_t audio_stream_number;
0066 };
0067
0068 struct resource_create_funcs {
0069     void (*read_dce_straps)(
0070             struct dc_context *ctx, struct resource_straps *straps);
0071
0072     struct audio *(*create_audio)(
0073             struct dc_context *ctx, unsigned int inst);
0074
0075     struct stream_encoder *(*create_stream_encoder)(
0076             enum engine_id eng_id, struct dc_context *ctx);
0077
0078     struct hpo_dp_stream_encoder *(*create_hpo_dp_stream_encoder)(
0079             enum engine_id eng_id, struct dc_context *ctx);
0080
0081     struct hpo_dp_link_encoder *(*create_hpo_dp_link_encoder)(
0082             uint8_t inst,
0083             struct dc_context *ctx);
0084
0085     struct dce_hwseq *(*create_hwseq)(
0086             struct dc_context *ctx);
0087 };
0088
0089 bool resource_construct(
0090     unsigned int num_virtual_links,
0091     struct dc *dc,
0092     struct resource_pool *pool,
0093     const struct resource_create_funcs *create_funcs);
0094
0095 struct resource_pool *dc_create_resource_pool(struct dc  *dc,
0096                           const struct dc_init_data *init_data,
0097                           enum dce_version dc_version);
0098
0099 void dc_destroy_resource_pool(struct dc *dc);
0100
0101 enum dc_status resource_map_pool_resources(
0102         const struct dc *dc,
0103         struct dc_state *context,
0104         struct dc_stream_state *stream);
0105
0106 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
0107
0108 enum dc_status resource_build_scaling_params_for_context(
0109         const struct dc *dc,
0110         struct dc_state *context);
0111
0112 void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
0113
0114 void resource_unreference_clock_source(
0115         struct resource_context *res_ctx,
0116         const struct resource_pool *pool,
0117         struct clock_source *clock_source);
0118
0119 void resource_reference_clock_source(
0120         struct resource_context *res_ctx,
0121         const struct resource_pool *pool,
0122         struct clock_source *clock_source);
0123
0124 int resource_get_clock_source_reference(
0125         struct resource_context *res_ctx,
0126         const struct resource_pool *pool,
0127         struct clock_source *clock_source);
0128
0129 bool resource_are_streams_timing_synchronizable(
0130         struct dc_stream_state *stream1,
0131         struct dc_stream_state *stream2);
0132
0133 bool resource_are_vblanks_synchronizable(
0134         struct dc_stream_state *stream1,
0135         struct dc_stream_state *stream2);
0136
0137 struct clock_source *resource_find_used_clk_src_for_sharing(
0138         struct resource_context *res_ctx,
0139         struct pipe_ctx *pipe_ctx);
0140
0141 struct clock_source *dc_resource_find_first_free_pll(
0142         struct resource_context *res_ctx,
0143         const struct resource_pool *pool);
0144
0145 struct pipe_ctx *resource_get_head_pipe_for_stream(
0146         struct resource_context *res_ctx,
0147         struct dc_stream_state *stream);
0148
0149 bool resource_attach_surfaces_to_context(
0150         struct dc_plane_state *const *plane_state,
0151         int surface_count,
0152         struct dc_stream_state *dc_stream,
0153         struct dc_state *context,
0154         const struct resource_pool *pool);
0155
0156 struct pipe_ctx *find_idle_secondary_pipe(
0157         struct resource_context *res_ctx,
0158         const struct resource_pool *pool,
0159         const struct pipe_ctx *primary_pipe);
0160
0161 bool resource_validate_attach_surfaces(
0162         const struct dc_validation_set set[],
0163         int set_count,
0164         const struct dc_state *old_context,
0165         struct dc_state *context,
0166         const struct resource_pool *pool);
0167
0168 void resource_validate_ctx_update_pointer_after_copy(
0169         const struct dc_state *src_ctx,
0170         struct dc_state *dst_ctx);
0171
0172 enum dc_status resource_map_clock_resources(
0173         const struct dc *dc,
0174         struct dc_state *context,
0175         struct dc_stream_state *stream);
0176
0177 enum dc_status resource_map_phy_clock_resources(
0178         const struct dc *dc,
0179         struct dc_state *context,
0180         struct dc_stream_state *stream);
0181
0182 bool pipe_need_reprogram(
0183         struct pipe_ctx *pipe_ctx_old,
0184         struct pipe_ctx *pipe_ctx);
0185
0186 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
0187         struct bit_depth_reduction_params *fmt_bit_depth);
0188
0189 void update_audio_usage(
0190         struct resource_context *res_ctx,
0191         const struct resource_pool *pool,
0192         struct audio *audio,
0193         bool acquired);
0194
0195 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format);
0196
0197 void get_audio_check(struct audio_info *aud_modes,
0198     struct audio_check *aud_chk);
0199
0200 int get_num_mpc_splits(struct pipe_ctx *pipe);
0201
0202 int get_num_odm_splits(struct pipe_ctx *pipe);
0203
0204 bool get_temp_dp_link_res(struct dc_link *link,
0205         struct link_resource *link_res,
0206         struct dc_link_settings *link_settings);
0207
0208 #if defined(CONFIG_DRM_AMD_DC_DCN)
0209 struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
0210         const struct resource_context *res_ctx,
0211         const struct resource_pool *pool,
0212         const struct dc_link *link);
0213 #endif
0214
0215 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
0216     struct dc_state *context);
0217
0218 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
0219     struct dc_state *context,
0220     uint8_t disabled_master_pipe_idx);
0221
0222 void reset_sync_context_for_pipe(const struct dc *dc,
0223     struct dc_state *context,
0224     uint8_t pipe_idx);
0225
0226 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter);
0227
0228 const struct link_hwss *get_link_hwss(const struct dc_link *link,
0229         const struct link_resource *link_res);
0230
0231 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */