dc/inc/hw_sequencer_private.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_HW_SEQUENCER_PRIVATE_H__
0027 #define __DC_HW_SEQUENCER_PRIVATE_H__
0028
0029 #include "dc_types.h"
0030
0031 enum pipe_gating_control {
0032     PIPE_GATING_CONTROL_DISABLE = 0,
0033     PIPE_GATING_CONTROL_ENABLE,
0034     PIPE_GATING_CONTROL_INIT
0035 };
0036
0037 struct dce_hwseq_wa {
0038     bool blnd_crtc_trigger;
0039     bool DEGVIDCN10_253;
0040     bool false_optc_underflow;
0041     bool DEGVIDCN10_254;
0042     bool DEGVIDCN21;
0043     bool disallow_self_refresh_during_multi_plane_transition;
0044     bool dp_hpo_and_otg_sequence;
0045     bool wait_hubpret_read_start_during_mpo_transition;
0046 };
0047
0048 struct hwseq_wa_state {
0049     bool DEGVIDCN10_253_applied;
0050     bool disallow_self_refresh_during_multi_plane_transition_applied;
0051     unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame;
0052 };
0053
0054 struct pipe_ctx;
0055 struct dc_state;
0056 struct dc_stream_status;
0057 struct dc_writeback_info;
0058 struct dchub_init_data;
0059 struct dc_static_screen_params;
0060 struct resource_pool;
0061 struct resource_context;
0062 struct stream_resource;
0063 struct dc_phy_addr_space_config;
0064 struct dc_virtual_addr_space_config;
0065 struct hubp;
0066 struct dpp;
0067 struct dce_hwseq;
0068 struct timing_generator;
0069 struct tg_color;
0070 struct output_pixel_processor;
0071 struct mpcc_blnd_cfg;
0072
0073 struct hwseq_private_funcs {
0074
0075     void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
0076     void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
0077     void (*init_pipes)(struct dc *dc, struct dc_state *context);
0078     void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
0079     void (*update_plane_addr)(const struct dc *dc,
0080             struct pipe_ctx *pipe_ctx);
0081     void (*plane_atomic_disconnect)(struct dc *dc,
0082             struct pipe_ctx *pipe_ctx);
0083     void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
0084     bool (*set_input_transfer_func)(struct dc *dc,
0085                 struct pipe_ctx *pipe_ctx,
0086                 const struct dc_plane_state *plane_state);
0087     bool (*set_output_transfer_func)(struct dc *dc,
0088                 struct pipe_ctx *pipe_ctx,
0089                 const struct dc_stream_state *stream);
0090     void (*power_down)(struct dc *dc);
0091     void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,
0092                     bool clock_gating);
0093     bool (*enable_display_power_gating)(struct dc *dc,
0094                     uint8_t controller_id,
0095                     struct dc_bios *dcb,
0096                     enum pipe_gating_control power_gating);
0097     void (*blank_pixel_data)(struct dc *dc,
0098             struct pipe_ctx *pipe_ctx,
0099             bool blank);
0100     enum dc_status (*enable_stream_timing)(
0101             struct pipe_ctx *pipe_ctx,
0102             struct dc_state *context,
0103             struct dc *dc);
0104     void (*edp_backlight_control)(struct dc_link *link,
0105             bool enable);
0106     void (*setup_vupdate_interrupt)(struct dc *dc,
0107             struct pipe_ctx *pipe_ctx);
0108     bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
0109     void (*init_blank)(struct dc *dc, struct timing_generator *tg);
0110     void (*disable_vga)(struct dce_hwseq *hws);
0111     void (*bios_golden_init)(struct dc *dc);
0112     void (*plane_atomic_power_down)(struct dc *dc,
0113             struct dpp *dpp,
0114             struct hubp *hubp);
0115     void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);
0116     void (*enable_power_gating_plane)(struct dce_hwseq *hws,
0117         bool enable);
0118     void (*dpp_pg_control)(struct dce_hwseq *hws,
0119             unsigned int dpp_inst,
0120             bool power_on);
0121     void (*hubp_pg_control)(struct dce_hwseq *hws,
0122             unsigned int hubp_inst,
0123             bool power_on);
0124     void (*dsc_pg_control)(struct dce_hwseq *hws,
0125             unsigned int dsc_inst,
0126             bool power_on);
0127     void (*update_odm)(struct dc *dc, struct dc_state *context,
0128             struct pipe_ctx *pipe_ctx);
0129     void (*program_all_writeback_pipes_in_tree)(struct dc *dc,
0130             const struct dc_stream_state *stream,
0131             struct dc_state *context);
0132     bool (*s0i3_golden_init_wa)(struct dc *dc);
0133     void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
0134     void (*verify_allow_pstate_change_high)(struct dc *dc);
0135     void (*program_pipe)(struct dc *dc,
0136             struct pipe_ctx *pipe_ctx,
0137             struct dc_state *context);
0138     bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);
0139     void (*dccg_init)(struct dce_hwseq *hws);
0140     bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,
0141             const struct dc_plane_state *plane_state);
0142     bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
0143             const struct dc_plane_state *plane_state);
0144     bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,
0145             const struct dc_plane_state *plane_state);
0146     void (*PLAT_58856_wa)(struct dc_state *context,
0147             struct pipe_ctx *pipe_ctx);
0148     void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
0149 #ifdef CONFIG_DRM_AMD_DC_DCN
0150     void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);
0151     void (*subvp_update_force_pstate)(struct dc *dc, struct dc_state *context);
0152     void (*update_mall_sel)(struct dc *dc, struct dc_state *context);
0153     unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,
0154             unsigned int *k1_div,
0155             unsigned int *k2_div);
0156     void (*set_pixels_per_cycle)(struct pipe_ctx *pipe_ctx);
0157     bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx);
0158 #endif
0159 };
0160
0161 struct dce_hwseq {
0162     struct dc_context *ctx;
0163     const struct dce_hwseq_registers *regs;
0164     const struct dce_hwseq_shift *shifts;
0165     const struct dce_hwseq_mask *masks;
0166     struct dce_hwseq_wa wa;
0167     struct hwseq_wa_state wa_state;
0168     struct hwseq_private_funcs funcs;
0169
0170     PHYSICAL_ADDRESS_LOC fb_base;
0171     PHYSICAL_ADDRESS_LOC fb_top;
0172     PHYSICAL_ADDRESS_LOC fb_offset;
0173     PHYSICAL_ADDRESS_LOC uma_top;
0174 };
0175
0176 #endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */