inc/hw/timing_generator.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DAL_TIMING_GENERATOR_TYPES_H__
0027 #define __DAL_TIMING_GENERATOR_TYPES_H__
0028
0029 #include "hw_shared.h"
0030
0031 struct dc_bios;
0032
0033 /* Contains CRTC vertical/horizontal pixel counters */
0034 struct crtc_position {
0035     int32_t vertical_count;
0036     int32_t horizontal_count;
0037     int32_t nominal_vcount;
0038 };
0039
0040 struct dcp_gsl_params {
0041     int gsl_group;
0042     int gsl_master;
0043 };
0044
0045 struct gsl_params {
0046     int gsl0_en;
0047     int gsl1_en;
0048     int gsl2_en;
0049     int gsl_master_en;
0050     int gsl_master_mode;
0051     int master_update_lock_gsl_en;
0052     int gsl_window_start_x;
0053     int gsl_window_end_x;
0054     int gsl_window_start_y;
0055     int gsl_window_end_y;
0056 };
0057
0058 /* define the structure of Dynamic Refresh Mode */
0059 struct drr_params {
0060     uint32_t vertical_total_min;
0061     uint32_t vertical_total_max;
0062     uint32_t vertical_total_mid;
0063     uint32_t vertical_total_mid_frame_num;
0064     bool immediate_flip;
0065 };
0066
0067 #define LEFT_EYE_3D_PRIMARY_SURFACE 1
0068 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0
0069
0070 enum crtc_state {
0071     CRTC_STATE_VBLANK = 0,
0072     CRTC_STATE_VACTIVE
0073 };
0074
0075 struct vupdate_keepout_params {
0076     int start_offset;
0077     int end_offset;
0078     int enable;
0079 };
0080
0081 struct crtc_stereo_flags {
0082     uint8_t PROGRAM_STEREO         : 1;
0083     uint8_t PROGRAM_POLARITY       : 1;
0084     uint8_t RIGHT_EYE_POLARITY     : 1;
0085     uint8_t FRAME_PACKED           : 1;
0086     uint8_t DISABLE_STEREO_DP_SYNC : 1;
0087 };
0088
0089 enum crc_selection {
0090     /* Order must match values expected by hardware */
0091     UNION_WINDOW_A_B = 0,
0092     UNION_WINDOW_A_NOT_B,
0093     UNION_WINDOW_NOT_A_B,
0094     UNION_WINDOW_NOT_A_NOT_B,
0095     INTERSECT_WINDOW_A_B,
0096     INTERSECT_WINDOW_A_NOT_B,
0097     INTERSECT_WINDOW_NOT_A_B,
0098     INTERSECT_WINDOW_NOT_A_NOT_B,
0099 };
0100
0101 enum otg_out_mux_dest {
0102     OUT_MUX_DIO = 0,
0103     OUT_MUX_HPO_DP = 2,
0104 };
0105
0106 enum h_timing_div_mode {
0107     H_TIMING_NO_DIV,
0108     H_TIMING_DIV_BY2,
0109     H_TIMING_RESERVED,
0110     H_TIMING_DIV_BY4,
0111 };
0112
0113 enum timing_synchronization_type {
0114     NOT_SYNCHRONIZABLE,
0115     TIMING_SYNCHRONIZABLE,
0116     VBLANK_SYNCHRONIZABLE
0117 };
0118
0119 struct crc_params {
0120     /* Regions used to calculate CRC*/
0121     uint16_t windowa_x_start;
0122     uint16_t windowa_x_end;
0123     uint16_t windowa_y_start;
0124     uint16_t windowa_y_end;
0125
0126     uint16_t windowb_x_start;
0127     uint16_t windowb_x_end;
0128     uint16_t windowb_y_start;
0129     uint16_t windowb_y_end;
0130
0131     enum crc_selection selection;
0132
0133     uint8_t dsc_mode;
0134     uint8_t odm_mode;
0135
0136     bool continuous_mode;
0137     bool enable;
0138 };
0139
0140 struct timing_generator {
0141     const struct timing_generator_funcs *funcs;
0142     struct dc_bios *bp;
0143     struct dc_context *ctx;
0144     int inst;
0145 };
0146
0147 struct dc_crtc_timing;
0148
0149 struct drr_params;
0150
0151
0152 struct timing_generator_funcs {
0153     bool (*validate_timing)(struct timing_generator *tg,
0154                             const struct dc_crtc_timing *timing);
0155     void (*program_timing)(struct timing_generator *tg,
0156                             const struct dc_crtc_timing *timing,
0157                             int vready_offset,
0158                             int vstartup_start,
0159                             int vupdate_offset,
0160                             int vupdate_width,
0161                             const enum signal_type signal,
0162                             bool use_vbios
0163     );
0164     void (*setup_vertical_interrupt0)(
0165             struct timing_generator *optc,
0166             uint32_t start_line,
0167             uint32_t end_line);
0168     void (*setup_vertical_interrupt1)(
0169             struct timing_generator *optc,
0170             uint32_t start_line);
0171     void (*setup_vertical_interrupt2)(
0172             struct timing_generator *optc,
0173             uint32_t start_line);
0174
0175     bool (*enable_crtc)(struct timing_generator *tg);
0176     bool (*disable_crtc)(struct timing_generator *tg);
0177 #ifdef CONFIG_DRM_AMD_DC_DCN
0178     void (*phantom_crtc_post_enable)(struct timing_generator *tg);
0179 #endif
0180     bool (*immediate_disable_crtc)(struct timing_generator *tg);
0181     bool (*is_counter_moving)(struct timing_generator *tg);
0182     void (*get_position)(struct timing_generator *tg,
0183                 struct crtc_position *position);
0184
0185     uint32_t (*get_frame_count)(struct timing_generator *tg);
0186     void (*get_scanoutpos)(
0187         struct timing_generator *tg,
0188         uint32_t *v_blank_start,
0189         uint32_t *v_blank_end,
0190         uint32_t *h_position,
0191         uint32_t *v_position);
0192     bool (*get_otg_active_size)(struct timing_generator *optc,
0193             uint32_t *otg_active_width,
0194             uint32_t *otg_active_height);
0195     bool (*is_matching_timing)(struct timing_generator *tg,
0196             const struct dc_crtc_timing *otg_timing);
0197     void (*set_early_control)(struct timing_generator *tg,
0198                                uint32_t early_cntl);
0199     void (*wait_for_state)(struct timing_generator *tg,
0200                             enum crtc_state state);
0201     void (*set_blank)(struct timing_generator *tg,
0202                     bool enable_blanking);
0203     bool (*is_blanked)(struct timing_generator *tg);
0204     bool (*is_locked)(struct timing_generator *tg);
0205     void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
0206     void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
0207     void (*set_colors)(struct timing_generator *tg,
0208                         const struct tg_color *blank_color,
0209                         const struct tg_color *overscan_color);
0210
0211     void (*disable_vga)(struct timing_generator *tg);
0212     bool (*did_triggered_reset_occur)(struct timing_generator *tg);
0213     void (*setup_global_swap_lock)(struct timing_generator *tg,
0214                             const struct dcp_gsl_params *gsl_params);
0215     void (*unlock)(struct timing_generator *tg);
0216     void (*lock)(struct timing_generator *tg);
0217     void (*lock_doublebuffer_disable)(struct timing_generator *tg);
0218     void (*lock_doublebuffer_enable)(struct timing_generator *tg);
0219     void(*triplebuffer_unlock)(struct timing_generator *tg);
0220     void(*triplebuffer_lock)(struct timing_generator *tg);
0221     void (*enable_reset_trigger)(struct timing_generator *tg,
0222                      int source_tg_inst);
0223     void (*enable_crtc_reset)(struct timing_generator *tg,
0224                   int source_tg_inst,
0225                   struct crtc_trigger_info *crtc_tp);
0226     void (*disable_reset_trigger)(struct timing_generator *tg);
0227     void (*tear_down_global_swap_lock)(struct timing_generator *tg);
0228     void (*enable_advanced_request)(struct timing_generator *tg,
0229                     bool enable, const struct dc_crtc_timing *timing);
0230     void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
0231     void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max);
0232     void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate);
0233     void (*set_static_screen_control)(struct timing_generator *tg,
0234                         uint32_t event_triggers,
0235                         uint32_t num_frames);
0236     void (*set_test_pattern)(
0237         struct timing_generator *tg,
0238         enum controller_dp_test_pattern test_pattern,
0239         enum dc_color_depth color_depth);
0240
0241     bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
0242
0243     void (*program_global_sync)(struct timing_generator *tg,
0244             int vready_offset,
0245             int vstartup_start,
0246             int vupdate_offset,
0247             int vupdate_width);
0248     void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
0249     void (*program_stereo)(struct timing_generator *tg,
0250         const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
0251     bool (*is_stereo_left_eye)(struct timing_generator *tg);
0252
0253     void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
0254
0255     void (*tg_init)(struct timing_generator *tg);
0256     bool (*is_tg_enabled)(struct timing_generator *tg);
0257     bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
0258     void (*clear_optc_underflow)(struct timing_generator *tg);
0259
0260     void (*set_dwb_source)(struct timing_generator *optc,
0261         uint32_t dwb_pipe_inst);
0262
0263     void (*get_optc_source)(struct timing_generator *optc,
0264             uint32_t *num_of_input_segments,
0265             uint32_t *seg0_src_sel,
0266             uint32_t *seg1_src_sel);
0267
0268     /**
0269      * Configure CRCs for the given timing generator. Return false if TG is
0270      * not on.
0271      */
0272     bool (*configure_crc)(struct timing_generator *tg,
0273                    const struct crc_params *params);
0274
0275     /**
0276      * Get CRCs for the given timing generator. Return false if CRCs are
0277      * not enabled (via configure_crc).
0278      */
0279     bool (*get_crc)(struct timing_generator *tg,
0280             uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
0281
0282     void (*program_manual_trigger)(struct timing_generator *optc);
0283     void (*setup_manual_trigger)(struct timing_generator *optc);
0284     bool (*get_hw_timing)(struct timing_generator *optc,
0285             struct dc_crtc_timing *hw_crtc_timing);
0286
0287     void (*set_vtg_params)(struct timing_generator *optc,
0288             const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);
0289
0290     void (*set_dsc_config)(struct timing_generator *optc,
0291                    enum optc_dsc_mode dsc_mode,
0292                    uint32_t dsc_bytes_per_pixel,
0293                    uint32_t dsc_slice_width);
0294     void (*get_dsc_status)(struct timing_generator *optc,
0295                     uint32_t *dsc_mode);
0296     void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
0297     void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
0298             struct dc_crtc_timing *timing);
0299     void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode);
0300     void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
0301     void (*set_gsl_source_select)(struct timing_generator *optc,
0302             int group_idx,
0303             uint32_t gsl_ready_signal);
0304     void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
0305     void (*set_drr_trigger_window)(struct timing_generator *optc,
0306             uint32_t window_start, uint32_t window_end);
0307     void (*set_vtotal_change_limit)(struct timing_generator *optc,
0308             uint32_t limit);
0309     void (*align_vblanks)(struct timing_generator *master_optc,
0310             struct timing_generator *slave_optc,
0311             uint32_t master_pixel_clock_100Hz,
0312             uint32_t slave_pixel_clock_100Hz,
0313             uint8_t master_clock_divider,
0314             uint8_t slave_clock_divider);
0315     bool (*validate_vmin_vmax)(struct timing_generator *optc,
0316             int vmin, int vmax);
0317     bool (*validate_vtotal_change_limit)(struct timing_generator *optc,
0318             uint32_t vtotal_change_limit);
0319
0320     void (*init_odm)(struct timing_generator *tg);
0321 };
0322
0323 #endif