inc/hw/link_encoder.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 /*
0024  * link_encoder.h
0025  *
0026  *  Created on: Oct 6, 2015
0027  *      Author: yonsun
0028  */
0029
0030 #ifndef LINK_ENCODER_H_
0031 #define LINK_ENCODER_H_
0032
0033 #include "grph_object_defs.h"
0034 #include "signal_types.h"
0035 #include "dc_types.h"
0036
0037 struct dc_context;
0038 struct encoder_set_dp_phy_pattern_param;
0039 struct link_mst_stream_allocation_table;
0040 struct dc_link_settings;
0041 struct link_training_settings;
0042 struct pipe_ctx;
0043
0044 struct encoder_init_data {
0045     enum channel_id channel;
0046     struct graphics_object_id connector;
0047     enum hpd_source_id hpd_source;
0048     /* TODO: in DAL2, here was pointer to EventManagerInterface */
0049     struct graphics_object_id encoder;
0050     struct dc_context *ctx;
0051     enum transmitter transmitter;
0052 };
0053
0054 struct encoder_feature_support {
0055     union {
0056         struct {
0057             uint32_t IS_HBR2_CAPABLE:1;
0058             uint32_t IS_HBR3_CAPABLE:1;
0059             uint32_t IS_TPS3_CAPABLE:1;
0060             uint32_t IS_TPS4_CAPABLE:1;
0061             uint32_t HDMI_6GB_EN:1;
0062             uint32_t IS_DP2_CAPABLE:1;
0063             uint32_t IS_UHBR10_CAPABLE:1;
0064             uint32_t IS_UHBR13_5_CAPABLE:1;
0065             uint32_t IS_UHBR20_CAPABLE:1;
0066             uint32_t DP_IS_USB_C:1;
0067         } bits;
0068         uint32_t raw;
0069     } flags;
0070
0071     enum dc_color_depth max_hdmi_deep_color;
0072     unsigned int max_hdmi_pixel_clock;
0073     bool hdmi_ycbcr420_supported;
0074     bool dp_ycbcr420_supported;
0075     bool fec_supported;
0076 };
0077
0078 union dpcd_psr_configuration {
0079     struct {
0080         unsigned char ENABLE                    : 1;
0081         unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1;
0082         unsigned char CRC_VERIFICATION          : 1;
0083         unsigned char FRAME_CAPTURE_INDICATION  : 1;
0084         /* For eDP 1.4, PSR v2*/
0085         unsigned char LINE_CAPTURE_INDICATION   : 1;
0086         /* For eDP 1.4, PSR v2*/
0087         unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
0088         unsigned char ENABLE_PSR2               : 1;
0089         /* For eDP 1.5, PSR v2 w/ early transport */
0090         unsigned char EARLY_TRANSPORT_ENABLE    : 1;
0091     } bits;
0092     unsigned char raw;
0093 };
0094
0095 union dpcd_alpm_configuration {
0096     struct {
0097         unsigned char ENABLE                    : 1;
0098         unsigned char IRQ_HPD_ENABLE            : 1;
0099         unsigned char RESERVED                  : 6;
0100     } bits;
0101     unsigned char raw;
0102 };
0103
0104 union dpcd_sink_active_vtotal_control_mode {
0105     struct {
0106         unsigned char ENABLE                    : 1;
0107         unsigned char RESERVED                  : 7;
0108     } bits;
0109     unsigned char raw;
0110 };
0111
0112 union psr_error_status {
0113     struct {
0114         unsigned char LINK_CRC_ERROR        :1;
0115         unsigned char RFB_STORAGE_ERROR     :1;
0116         unsigned char VSC_SDP_ERROR         :1;
0117         unsigned char RESERVED              :5;
0118     } bits;
0119     unsigned char raw;
0120 };
0121
0122 union psr_sink_psr_status {
0123     struct {
0124     unsigned char SINK_SELF_REFRESH_STATUS  :3;
0125     unsigned char RESERVED                  :5;
0126     } bits;
0127     unsigned char raw;
0128 };
0129
0130 struct link_encoder {
0131     const struct link_encoder_funcs *funcs;
0132     int32_t aux_channel_offset;
0133     struct dc_context *ctx;
0134     struct graphics_object_id id;
0135     struct graphics_object_id connector;
0136     uint32_t output_signals;
0137     enum engine_id preferred_engine;
0138     struct encoder_feature_support features;
0139     enum transmitter transmitter;
0140     enum hpd_source_id hpd_source;
0141     bool usbc_combo_phy;
0142 };
0143
0144 struct link_enc_state {
0145
0146         uint32_t dphy_fec_en;
0147         uint32_t dphy_fec_ready_shadow;
0148         uint32_t dphy_fec_active_status;
0149         uint32_t dp_link_training_complete;
0150
0151 };
0152
0153 enum encoder_type_select {
0154     ENCODER_TYPE_DIG = 0,
0155     ENCODER_TYPE_HDMI_FRL = 1,
0156     ENCODER_TYPE_DP_128B132B = 2
0157 };
0158
0159 struct link_encoder_funcs {
0160     void (*read_state)(
0161             struct link_encoder *enc, struct link_enc_state *s);
0162     bool (*validate_output_with_stream)(
0163         struct link_encoder *enc, const struct dc_stream_state *stream);
0164     void (*hw_init)(struct link_encoder *enc);
0165     void (*setup)(struct link_encoder *enc,
0166         enum signal_type signal);
0167     void (*enable_tmds_output)(struct link_encoder *enc,
0168         enum clock_source_id clock_source,
0169         enum dc_color_depth color_depth,
0170         enum signal_type signal,
0171         uint32_t pixel_clock);
0172     void (*enable_dp_output)(struct link_encoder *enc,
0173         const struct dc_link_settings *link_settings,
0174         enum clock_source_id clock_source);
0175     void (*enable_dp_mst_output)(struct link_encoder *enc,
0176         const struct dc_link_settings *link_settings,
0177         enum clock_source_id clock_source);
0178     void (*enable_lvds_output)(struct link_encoder *enc,
0179         enum clock_source_id clock_source,
0180         uint32_t pixel_clock);
0181     void (*disable_output)(struct link_encoder *link_enc,
0182         enum signal_type signal);
0183     void (*dp_set_lane_settings)(struct link_encoder *enc,
0184         const struct dc_link_settings *link_settings,
0185         const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
0186     void (*dp_set_phy_pattern)(struct link_encoder *enc,
0187         const struct encoder_set_dp_phy_pattern_param *para);
0188     void (*update_mst_stream_allocation_table)(
0189         struct link_encoder *enc,
0190         const struct link_mst_stream_allocation_table *table);
0191     void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc,
0192             bool exit_link_training_required);
0193     void (*psr_program_secondary_packet)(struct link_encoder *enc,
0194                 unsigned int sdp_transmit_line_num_deadline);
0195     void (*connect_dig_be_to_fe)(struct link_encoder *enc,
0196         enum engine_id engine,
0197         bool connect);
0198     void (*enable_hpd)(struct link_encoder *enc);
0199     void (*disable_hpd)(struct link_encoder *enc);
0200     bool (*is_dig_enabled)(struct link_encoder *enc);
0201     unsigned int (*get_dig_frontend)(struct link_encoder *enc);
0202     void (*destroy)(struct link_encoder **enc);
0203
0204     void (*fec_set_enable)(struct link_encoder *enc,
0205         bool enable);
0206
0207     void (*fec_set_ready)(struct link_encoder *enc,
0208         bool ready);
0209
0210     bool (*fec_is_active)(struct link_encoder *enc);
0211     bool (*is_in_alt_mode) (struct link_encoder *enc);
0212
0213     void (*get_max_link_cap)(struct link_encoder *enc,
0214         struct dc_link_settings *link_settings);
0215
0216     enum signal_type (*get_dig_mode)(
0217         struct link_encoder *enc);
0218     void (*set_dio_phy_mux)(
0219         struct link_encoder *enc,
0220         enum encoder_type_select sel,
0221         uint32_t hpo_inst);
0222     void (*set_dig_output_mode)(
0223             struct link_encoder *enc, uint8_t pix_per_container);
0224 };
0225
0226 /*
0227  * Used to track assignments of links (display endpoints) to link encoders.
0228  *
0229  * Entry in link_enc_assignments table in struct resource_context.
0230  * Entries only marked valid once encoder assigned to a link and invalidated once unassigned.
0231  * Uses engine ID as identifier since PHY ID not relevant for USB4 DPIA endpoint.
0232  */
0233 struct link_enc_assignment {
0234     bool valid;
0235     struct display_endpoint_id ep_id;
0236     enum engine_id eng_id;
0237     struct dc_stream_state *stream;
0238 };
0239
0240 enum link_enc_cfg_mode {
0241     LINK_ENC_CFG_STEADY, /* Normal operation - use current_state. */
0242     LINK_ENC_CFG_TRANSIENT /* During commit state - use state to be committed. */
0243 };
0244
0245 enum dp2_link_mode {
0246     DP2_LINK_TRAINING_TPS1,
0247     DP2_LINK_TRAINING_TPS2,
0248     DP2_LINK_ACTIVE,
0249     DP2_TEST_PATTERN
0250 };
0251
0252 enum dp2_phy_tp_select {
0253     DP_DPHY_TP_SELECT_TPS1,
0254     DP_DPHY_TP_SELECT_TPS2,
0255     DP_DPHY_TP_SELECT_PRBS,
0256     DP_DPHY_TP_SELECT_CUSTOM,
0257     DP_DPHY_TP_SELECT_SQUARE
0258 };
0259
0260 enum dp2_phy_tp_prbs {
0261     DP_DPHY_TP_PRBS7,
0262     DP_DPHY_TP_PRBS9,
0263     DP_DPHY_TP_PRBS11,
0264     DP_DPHY_TP_PRBS15,
0265     DP_DPHY_TP_PRBS23,
0266     DP_DPHY_TP_PRBS31
0267 };
0268
0269 struct hpo_dp_link_enc_state {
0270     uint32_t   link_enc_enabled;
0271     uint32_t   link_mode;
0272     uint32_t   lane_count;
0273     uint32_t   slot_count[4];
0274     uint32_t   stream_src[4];
0275     uint32_t   vc_rate_x[4];
0276     uint32_t   vc_rate_y[4];
0277 };
0278
0279 struct hpo_dp_link_encoder {
0280     const struct hpo_dp_link_encoder_funcs *funcs;
0281     struct dc_context *ctx;
0282     int inst;
0283     enum engine_id preferred_engine;
0284     enum transmitter transmitter;
0285     enum hpd_source_id hpd_source;
0286 };
0287
0288 struct hpo_dp_link_encoder_funcs {
0289
0290     void (*enable_link_phy)(struct hpo_dp_link_encoder *enc,
0291         const struct dc_link_settings *link_settings,
0292         enum transmitter transmitter,
0293         enum hpd_source_id hpd_source);
0294
0295     void (*disable_link_phy)(struct hpo_dp_link_encoder *link_enc,
0296         enum signal_type signal);
0297
0298     void (*link_enable)(
0299             struct hpo_dp_link_encoder *enc,
0300             enum dc_lane_count num_lanes);
0301
0302     void (*link_disable)(
0303             struct hpo_dp_link_encoder *enc);
0304
0305     void (*set_link_test_pattern)(
0306             struct hpo_dp_link_encoder *enc,
0307             struct encoder_set_dp_phy_pattern_param *tp_params);
0308
0309     void (*update_stream_allocation_table)(
0310             struct hpo_dp_link_encoder *enc,
0311             const struct link_mst_stream_allocation_table *table);
0312
0313     void (*set_throttled_vcp_size)(
0314             struct hpo_dp_link_encoder *enc,
0315             uint32_t stream_encoder_inst,
0316             struct fixed31_32 avg_time_slots_per_mtp);
0317
0318     bool (*is_in_alt_mode) (
0319             struct hpo_dp_link_encoder *enc);
0320
0321     void (*read_state)(
0322             struct hpo_dp_link_encoder *enc,
0323             struct hpo_dp_link_enc_state *state);
0324
0325     void (*set_ffe)(
0326         struct hpo_dp_link_encoder *enc,
0327         const struct dc_link_settings *link_settings,
0328         uint8_t ffe_preset);
0329 };
0330
0331 #endif /* LINK_ENCODER_H_ */