inc/hw/hw_shared.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DAL_HW_SHARED_H__
0027 #define __DAL_HW_SHARED_H__
0028
0029 #include "os_types.h"
0030 #include "fixed31_32.h"
0031 #include "dc_hw_types.h"
0032
0033 /******************************************************************************
0034  * Data types shared between different Virtual HW blocks
0035  ******************************************************************************/
0036
0037 #define MAX_AUDIOS 7
0038 #define MAX_PIPES 6
0039 #define MAX_DIG_LINK_ENCODERS 7
0040 #define MAX_DWB_PIPES   1
0041 #define MAX_HPO_DP2_ENCODERS    4
0042 #define MAX_HPO_DP2_LINK_ENCODERS   2
0043
0044 struct gamma_curve {
0045     uint32_t offset;
0046     uint32_t segments_num;
0047 };
0048
0049 struct curve_points {
0050     struct fixed31_32 x;
0051     struct fixed31_32 y;
0052     struct fixed31_32 offset;
0053     struct fixed31_32 slope;
0054
0055     uint32_t custom_float_x;
0056     uint32_t custom_float_y;
0057     uint32_t custom_float_offset;
0058     uint32_t custom_float_slope;
0059 };
0060
0061 struct curve_points3 {
0062     struct curve_points red;
0063     struct curve_points green;
0064     struct curve_points blue;
0065 };
0066
0067 struct pwl_result_data {
0068     struct fixed31_32 red;
0069     struct fixed31_32 green;
0070     struct fixed31_32 blue;
0071
0072     struct fixed31_32 delta_red;
0073     struct fixed31_32 delta_green;
0074     struct fixed31_32 delta_blue;
0075
0076     uint32_t red_reg;
0077     uint32_t green_reg;
0078     uint32_t blue_reg;
0079
0080     uint32_t delta_red_reg;
0081     uint32_t delta_green_reg;
0082     uint32_t delta_blue_reg;
0083 };
0084
0085 struct dc_rgb {
0086     uint32_t red;
0087     uint32_t green;
0088     uint32_t blue;
0089 };
0090
0091 struct tetrahedral_17x17x17 {
0092     struct dc_rgb lut0[1229];
0093     struct dc_rgb lut1[1228];
0094     struct dc_rgb lut2[1228];
0095     struct dc_rgb lut3[1228];
0096 };
0097 struct tetrahedral_9x9x9 {
0098     struct dc_rgb lut0[183];
0099     struct dc_rgb lut1[182];
0100     struct dc_rgb lut2[182];
0101     struct dc_rgb lut3[182];
0102 };
0103
0104 struct tetrahedral_params {
0105     union {
0106         struct tetrahedral_17x17x17 tetrahedral_17;
0107         struct tetrahedral_9x9x9 tetrahedral_9;
0108     };
0109     bool use_tetrahedral_9;
0110     bool use_12bits;
0111
0112 };
0113
0114 /* arr_curve_points - regamma regions/segments specification
0115  * arr_points - beginning and end point specified separately (only one on DCE)
0116  * corner_points - beginning and end point for all 3 colors (DCN)
0117  * rgb_resulted - final curve
0118  */
0119 struct pwl_params {
0120     struct gamma_curve arr_curve_points[34];
0121     union {
0122         struct curve_points arr_points[2];
0123         struct curve_points3 corner_points[2];
0124     };
0125     struct pwl_result_data rgb_resulted[256 + 3];
0126     uint32_t hw_points_num;
0127 };
0128
0129 /* move to dpp
0130  * while we are moving functionality out of opp to dpp to align
0131  * HW programming to HW IP, we define these struct in hw_shared
0132  * so we can still compile while refactoring
0133  */
0134
0135 enum lb_pixel_depth {
0136     /* do not change the values because it is used as bit vector */
0137     LB_PIXEL_DEPTH_18BPP = 1,
0138     LB_PIXEL_DEPTH_24BPP = 2,
0139     LB_PIXEL_DEPTH_30BPP = 4,
0140     LB_PIXEL_DEPTH_36BPP = 8
0141 };
0142
0143 enum graphics_csc_adjust_type {
0144     GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
0145     GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
0146     GRAPHICS_CSC_ADJUST_TYPE_SW  /*use adjustments */
0147 };
0148
0149 enum ipp_degamma_mode {
0150     IPP_DEGAMMA_MODE_BYPASS,
0151     IPP_DEGAMMA_MODE_HW_sRGB,
0152     IPP_DEGAMMA_MODE_HW_xvYCC,
0153     IPP_DEGAMMA_MODE_USER_PWL
0154 };
0155
0156 enum gamcor_mode {
0157     GAMCOR_MODE_BYPASS,
0158     GAMCOR_MODE_RESERVED_1,
0159     GAMCOR_MODE_USER_PWL,
0160     GAMCOR_MODE_RESERVED_3
0161 };
0162
0163 enum ipp_output_format {
0164     IPP_OUTPUT_FORMAT_12_BIT_FIX,
0165     IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
0166     IPP_OUTPUT_FORMAT_FLOAT
0167 };
0168
0169 enum expansion_mode {
0170     EXPANSION_MODE_DYNAMIC,
0171     EXPANSION_MODE_ZERO
0172 };
0173
0174 struct default_adjustment {
0175     enum lb_pixel_depth lb_color_depth;
0176     enum dc_color_space out_color_space;
0177     enum dc_color_space in_color_space;
0178     enum dc_color_depth color_depth;
0179     enum pixel_format surface_pixel_format;
0180     enum graphics_csc_adjust_type csc_adjust_type;
0181     bool force_hw_default;
0182 };
0183
0184
0185 struct out_csc_color_matrix {
0186     enum dc_color_space color_space;
0187     uint16_t regval[12];
0188 };
0189
0190 enum gamut_remap_select {
0191     GAMUT_REMAP_BYPASS = 0,
0192     GAMUT_REMAP_COEFF,
0193     GAMUT_REMAP_COMA_COEFF,
0194     GAMUT_REMAP_COMB_COEFF
0195 };
0196
0197 enum opp_regamma {
0198     OPP_REGAMMA_BYPASS = 0,
0199     OPP_REGAMMA_SRGB,
0200     OPP_REGAMMA_XVYCC,
0201     OPP_REGAMMA_USER
0202 };
0203
0204 enum optc_dsc_mode {
0205     OPTC_DSC_DISABLED = 0,
0206     OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
0207     OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
0208 };
0209
0210 struct dc_bias_and_scale {
0211     uint16_t scale_red;
0212     uint16_t bias_red;
0213     uint16_t scale_green;
0214     uint16_t bias_green;
0215     uint16_t scale_blue;
0216     uint16_t bias_blue;
0217 };
0218
0219 enum test_pattern_dyn_range {
0220     TEST_PATTERN_DYN_RANGE_VESA = 0,
0221     TEST_PATTERN_DYN_RANGE_CEA
0222 };
0223
0224 enum test_pattern_mode {
0225     TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
0226     TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
0227     TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
0228     TEST_PATTERN_MODE_VERTICALBARS,
0229     TEST_PATTERN_MODE_HORIZONTALBARS,
0230     TEST_PATTERN_MODE_SINGLERAMP_RGB,
0231     TEST_PATTERN_MODE_DUALRAMP_RGB,
0232     TEST_PATTERN_MODE_XR_BIAS_RGB
0233 };
0234
0235 enum test_pattern_color_format {
0236     TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
0237     TEST_PATTERN_COLOR_FORMAT_BPC_8,
0238     TEST_PATTERN_COLOR_FORMAT_BPC_10,
0239     TEST_PATTERN_COLOR_FORMAT_BPC_12
0240 };
0241
0242 enum controller_dp_test_pattern {
0243     CONTROLLER_DP_TEST_PATTERN_D102 = 0,
0244     CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
0245     CONTROLLER_DP_TEST_PATTERN_PRBS7,
0246     CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
0247     CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
0248     CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
0249     CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
0250     CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
0251     CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
0252     CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
0253     CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
0254     CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA,
0255     CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
0256 };
0257
0258 enum controller_dp_color_space {
0259     CONTROLLER_DP_COLOR_SPACE_RGB,
0260     CONTROLLER_DP_COLOR_SPACE_YCBCR601,
0261     CONTROLLER_DP_COLOR_SPACE_YCBCR709,
0262     CONTROLLER_DP_COLOR_SPACE_UDEFINED
0263 };
0264
0265 enum dc_lut_mode {
0266     LUT_BYPASS,
0267     LUT_RAM_A,
0268     LUT_RAM_B
0269 };
0270
0271 /**
0272  * speakersToChannels
0273  *
0274  * @brief
0275  *  translate speakers to channels
0276  *
0277  *  FL  - Front Left
0278  *  FR  - Front Right
0279  *  RL  - Rear Left
0280  *  RR  - Rear Right
0281  *  RC  - Rear Center
0282  *  FC  - Front Center
0283  *  FLC - Front Left Center
0284  *  FRC - Front Right Center
0285  *  RLC - Rear Left Center
0286  *  RRC - Rear Right Center
0287  *  LFE - Low Freq Effect
0288  *
0289  *               FC
0290  *          FLC      FRC
0291  *    FL                    FR
0292  *
0293  *                    LFE
0294  *              ()
0295  *
0296  *
0297  *    RL                    RR
0298  *          RLC      RRC
0299  *               RC
0300  *
0301  *             ch  8   7   6   5   4   3   2   1
0302  * 0b00000011      -   -   -   -   -   -   FR  FL
0303  * 0b00000111      -   -   -   -   -   LFE FR  FL
0304  * 0b00001011      -   -   -   -   FC  -   FR  FL
0305  * 0b00001111      -   -   -   -   FC  LFE FR  FL
0306  * 0b00010011      -   -   -   RC  -   -   FR  FL
0307  * 0b00010111      -   -   -   RC  -   LFE FR  FL
0308  * 0b00011011      -   -   -   RC  FC  -   FR  FL
0309  * 0b00011111      -   -   -   RC  FC  LFE FR  FL
0310  * 0b00110011      -   -   RR  RL  -   -   FR  FL
0311  * 0b00110111      -   -   RR  RL  -   LFE FR  FL
0312  * 0b00111011      -   -   RR  RL  FC  -   FR  FL
0313  * 0b00111111      -   -   RR  RL  FC  LFE FR  FL
0314  * 0b01110011      -   RC  RR  RL  -   -   FR  FL
0315  * 0b01110111      -   RC  RR  RL  -   LFE FR  FL
0316  * 0b01111011      -   RC  RR  RL  FC  -   FR  FL
0317  * 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
0318  * 0b11110011      RRC RLC RR  RL  -   -   FR  FL
0319  * 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
0320  * 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
0321  * 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
0322  * 0b11000011      FRC FLC -   -   -   -   FR  FL
0323  * 0b11000111      FRC FLC -   -   -   LFE FR  FL
0324  * 0b11001011      FRC FLC -   -   FC  -   FR  FL
0325  * 0b11001111      FRC FLC -   -   FC  LFE FR  FL
0326  * 0b11010011      FRC FLC -   RC  -   -   FR  FL
0327  * 0b11010111      FRC FLC -   RC  -   LFE FR  FL
0328  * 0b11011011      FRC FLC -   RC  FC  -   FR  FL
0329  * 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
0330  * 0b11110011      FRC FLC RR  RL  -   -   FR  FL
0331  * 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
0332  * 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
0333  * 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
0334  *
0335  * @param
0336  *  speakers - speaker information as it comes from CEA audio block
0337  */
0338 /* translate speakers to channels */
0339
0340 union audio_cea_channels {
0341     uint8_t all;
0342     struct audio_cea_channels_bits {
0343         uint32_t FL:1;
0344         uint32_t FR:1;
0345         uint32_t LFE:1;
0346         uint32_t FC:1;
0347         uint32_t RL_RC:1;
0348         uint32_t RR:1;
0349         uint32_t RC_RLC_FLC:1;
0350         uint32_t RRC_FRC:1;
0351     } channels;
0352 };
0353
0354 #endif /* __DAL_HW_SHARED_H__ */