inc/hw/dwb.h

0001 /* Copyright 2012-17 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024
0025 #ifndef __DC_DWBC_H__
0026 #define __DC_DWBC_H__
0027
0028 #include "dal_types.h"
0029 #include "dc_hw_types.h"
0030
0031 #define DWB_SW_V2   1
0032 #define DWB_MCIF_BUF_COUNT 4
0033
0034 /* forward declaration of mcif_wb struct */
0035 struct mcif_wb;
0036
0037
0038 enum dwb_sw_version {
0039     dwb_ver_1_0 = 1,
0040     dwb_ver_2_0 = 2,
0041 };
0042
0043 enum dwb_source {
0044     dwb_src_scl = 0,    /* for DCE7x/9x, DCN won't support. */
0045     dwb_src_blnd,       /* for DCE7x/9x */
0046     dwb_src_fmt,        /* for DCE7x/9x */
0047     dwb_src_otg0 = 0x100,   /* for DCN1.x/DCN2.x, register: mmDWB_SOURCE_SELECT */
0048     dwb_src_otg1,       /* for DCN1.x/DCN2.x */
0049     dwb_src_otg2,       /* for DCN1.x/DCN2.x */
0050     dwb_src_otg3,       /* for DCN1.x/DCN2.x */
0051 };
0052
0053 /* DCN1.x, DCN2.x support 2 pipes */
0054 enum dwb_pipe {
0055     dwb_pipe0 = 0,
0056 #if defined(CONFIG_DRM_AMD_DC_DCN)
0057     dwb_pipe1,
0058 #endif
0059     dwb_pipe_max_num,
0060 };
0061
0062 enum dwb_frame_capture_enable {
0063     DWB_FRAME_CAPTURE_DISABLE = 0,
0064     DWB_FRAME_CAPTURE_ENABLE = 1,
0065 };
0066
0067 enum wbscl_coef_filter_type_sel {
0068     WBSCL_COEF_LUMA_VERT_FILTER = 0,
0069     WBSCL_COEF_CHROMA_VERT_FILTER = 1,
0070     WBSCL_COEF_LUMA_HORZ_FILTER = 2,
0071     WBSCL_COEF_CHROMA_HORZ_FILTER = 3
0072 };
0073
0074
0075 #if defined(CONFIG_DRM_AMD_DC_DCN)
0076 enum dwb_boundary_mode {
0077     DWBSCL_BOUNDARY_MODE_EDGE  = 0,
0078     DWBSCL_BOUNDARY_MODE_BLACK = 1
0079 };
0080 #endif
0081
0082 #if defined(CONFIG_DRM_AMD_DC_DCN)
0083 enum dwb_output_csc_mode {
0084     DWB_OUTPUT_CSC_DISABLE = 0,
0085     DWB_OUTPUT_CSC_COEF_A = 1,
0086     DWB_OUTPUT_CSC_COEF_B = 2
0087 };
0088
0089 enum dwb_ogam_lut_mode {
0090     DWB_OGAM_MODE_BYPASS,
0091     DWB_OGAM_RAMA_LUT,
0092     DWB_OGAM_RAMB_LUT
0093 };
0094
0095 enum dwb_color_volume {
0096     DWB_SRGB_BT709 = 0, //SDR
0097     DWB_PQ = 1, //HDR
0098     DWB_HLG = 2,    //HDR
0099 };
0100
0101 enum dwb_color_space {
0102     DWB_SRGB = 0,   //SDR
0103     DWB_BT709 = 1,  //SDR
0104     DWB_BT2020 = 2, //HDR
0105 };
0106
0107 struct dwb_efc_hdr_metadata {
0108     /*display chromaticities and white point in units of 0.00001 */
0109     unsigned int    chromaticity_green_x;
0110     unsigned int    chromaticity_green_y;
0111     unsigned int    chromaticity_blue_x;
0112     unsigned int    chromaticity_blue_y;
0113     unsigned int    chromaticity_red_x;
0114     unsigned int    chromaticity_red_y;
0115     unsigned int    chromaticity_white_point_x;
0116     unsigned int    chromaticity_white_point_y;
0117
0118     /*in units of candelas per square meter */
0119     unsigned int    min_luminance;
0120     unsigned int    max_luminance;
0121
0122     /*in units of nits */
0123     unsigned int    maximum_content_light_level;
0124     unsigned int    maximum_frame_average_light_level;
0125 };
0126
0127 struct dwb_efc_display_settings {
0128     unsigned int    inputColorVolume;
0129     unsigned int    inputColorSpace;
0130     unsigned int    inputBitDepthMinus8;
0131     struct dwb_efc_hdr_metadata hdr_metadata;
0132     unsigned int    dwbOutputBlack; // 0 - Normal, 1 - Output Black
0133 };
0134
0135 #endif
0136 struct dwb_warmup_params {
0137     bool    warmup_en;  /* false: normal mode, true: enable pattern generator */
0138     bool    warmup_mode;    /* false: 420, true: 444 */
0139     bool    warmup_depth;   /* false: 8bit, true: 10bit */
0140     int warmup_data;    /* Data to be sent by pattern generator (same for each pixel component) */
0141     int warmup_width;   /* Pattern width (pixels) */
0142     int warmup_height;  /* Pattern height (lines) */
0143 };
0144
0145 struct dwb_caps {
0146     enum dce_version hw_version;    /* DCN engine version. */
0147     enum dwb_sw_version sw_version; /* DWB sw implementation version. */
0148     unsigned int    reserved[6];    /* Reserved for future use, MUST BE 0. */
0149     unsigned int    adapter_id;
0150     unsigned int    num_pipes;  /* number of DWB pipes */
0151     struct {
0152         unsigned int support_dwb    :1;
0153         unsigned int support_ogam   :1;
0154         unsigned int support_wbscl  :1;
0155         unsigned int support_ocsc   :1;
0156         unsigned int support_stereo :1;
0157     } caps;
0158     unsigned int     reserved2[9];  /* Reserved for future use, MUST BE 0. */
0159 };
0160
0161 struct dwbc {
0162     const struct dwbc_funcs *funcs;
0163     struct dc_context *ctx;
0164     int inst;
0165     struct mcif_wb *mcif;
0166     bool status;
0167     int inputSrcSelect;
0168     bool dwb_output_black;
0169     enum dc_transfer_func_predefined tf;
0170     enum dc_color_space output_color_space;
0171     bool dwb_is_efc_transition;
0172     bool dwb_is_drc;
0173     int wb_src_plane_inst;/*hubp, mpcc, inst*/
0174     uint32_t mask_id;
0175     int otg_inst;
0176     bool mvc_cfg;
0177 };
0178
0179 struct dwbc_funcs {
0180     bool (*get_caps)(
0181         struct dwbc *dwbc,
0182         struct dwb_caps *caps);
0183
0184     bool (*enable)(
0185         struct dwbc *dwbc,
0186         struct dc_dwb_params *params);
0187
0188     bool (*disable)(struct dwbc *dwbc);
0189
0190     bool (*update)(
0191         struct dwbc *dwbc,
0192         struct dc_dwb_params *params);
0193
0194     bool (*is_enabled)(
0195         struct dwbc *dwbc);
0196
0197     void (*set_stereo)(
0198         struct dwbc *dwbc,
0199         struct dwb_stereo_params *stereo_params);
0200
0201     void (*set_new_content)(
0202         struct dwbc *dwbc,
0203         bool is_new_content);
0204
0205
0206     void (*set_warmup)(
0207         struct dwbc *dwbc,
0208         struct dwb_warmup_params *warmup_params);
0209
0210
0211 #if defined(CONFIG_DRM_AMD_DC_DCN)
0212
0213     void (*dwb_program_output_csc)(
0214         struct dwbc *dwbc,
0215         enum dc_color_space color_space,
0216         enum dwb_output_csc_mode mode);
0217
0218     bool (*dwb_ogam_set_output_transfer_func)(
0219         struct dwbc *dwbc,
0220         const struct dc_transfer_func *in_transfer_func_dwb_ogam);
0221
0222     //TODO: merge with output_transfer_func?
0223     bool (*dwb_ogam_set_input_transfer_func)(
0224         struct dwbc *dwbc,
0225         const struct dc_transfer_func *in_transfer_func_dwb_ogam);
0226 #endif
0227     bool (*get_dwb_status)(
0228         struct dwbc *dwbc);
0229     void (*dwb_set_scaler)(
0230         struct dwbc *dwbc,
0231         struct dc_dwb_params *params);
0232 };
0233
0234 #endif