inc/hw/dsc.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 #ifndef __DAL_DSC_H__
0026 #define __DAL_DSC_H__
0027
0028 #include "dc_dsc.h"
0029 #include "dc_hw_types.h"
0030 #include "dc_types.h"
0031 /* do not include any other headers
0032  * or else it might break Edid Utility functionality.
0033  */
0034
0035
0036 /* Input parameters for configuring DSC from the outside of DSC */
0037 struct dsc_config {
0038     uint32_t pic_width;
0039     uint32_t pic_height;
0040     enum dc_pixel_encoding pixel_encoding;
0041     enum dc_color_depth color_depth;  /* Bits per component */
0042     bool is_odm;
0043     struct dc_dsc_config dc_dsc_cfg;
0044 };
0045
0046
0047 /* Output parameters for configuring DSC-related part of OPTC */
0048 struct dsc_optc_config {
0049     uint32_t slice_width; /* Slice width in pixels */
0050     uint32_t bytes_per_pixel; /* Bytes per pixel in u3.28 format */
0051     bool is_pixel_format_444; /* 'true' if pixel format is 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4)' */
0052 };
0053
0054
0055 struct dcn_dsc_state {
0056     uint32_t dsc_clock_en;
0057     uint32_t dsc_slice_width;
0058     uint32_t dsc_bits_per_pixel;
0059     uint32_t dsc_slice_height;
0060     uint32_t dsc_pic_width;
0061     uint32_t dsc_pic_height;
0062     uint32_t dsc_slice_bpg_offset;
0063     uint32_t dsc_chunk_size;
0064     uint32_t dsc_fw_en;
0065     uint32_t dsc_opp_source;
0066 };
0067
0068
0069 /* DSC encoder capabilities
0070  * They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps.
0071  */
0072 union dsc_enc_slice_caps {
0073     struct {
0074         uint8_t NUM_SLICES_1 : 1;
0075         uint8_t NUM_SLICES_2 : 1;
0076         uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */
0077         uint8_t NUM_SLICES_4 : 1;
0078         uint8_t NUM_SLICES_8 : 1;
0079     } bits;
0080     uint8_t raw;
0081 };
0082
0083 struct dsc_enc_caps {
0084     uint8_t dsc_version;
0085     union dsc_enc_slice_caps slice_caps;
0086     int32_t lb_bit_depth;
0087     bool is_block_pred_supported;
0088     union dsc_color_formats color_formats;
0089     union dsc_color_depth color_depth;
0090     int32_t max_total_throughput_mps; /* Maximum total throughput with all the slices combined */
0091     int32_t max_slice_width;
0092     uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
0093     uint32_t edp_sink_max_bits_per_pixel;
0094     bool is_dp;
0095 };
0096
0097 struct dsc_funcs {
0098     void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
0099     void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
0100     bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
0101     void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
0102             struct dsc_optc_config *dsc_optc_cfg);
0103     bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
0104             uint8_t *dsc_packed_pps);
0105     void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
0106     void (*dsc_disable)(struct display_stream_compressor *dsc);
0107     void (*dsc_disconnect)(struct display_stream_compressor *dsc);
0108 };
0109
0110 #endif