inc/hw/dccg.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DAL_DCCG_H__
0027 #define __DAL_DCCG_H__
0028
0029 #include "dc_types.h"
0030 #include "hw_shared.h"
0031
0032 enum phyd32clk_clock_source {
0033     PHYD32CLKA,
0034     PHYD32CLKB,
0035     PHYD32CLKC,
0036     PHYD32CLKD,
0037     PHYD32CLKE,
0038     PHYD32CLKF,
0039     PHYD32CLKG,
0040 };
0041
0042 enum physymclk_clock_source {
0043     PHYSYMCLK_FORCE_SRC_SYMCLK,    // Select symclk as source of clock which is output to PHY through DCIO.
0044     PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO.
0045     PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
0046 };
0047
0048 enum streamclk_source {
0049     REFCLK,                   // Selects REFCLK as source for hdmistreamclk.
0050     DTBCLK0,                  // Selects DTBCLK0 as source for hdmistreamclk.
0051     DPREFCLK,                 // Selects DPREFCLK as source for hdmistreamclk
0052 };
0053
0054 enum dentist_dispclk_change_mode {
0055     DISPCLK_CHANGE_MODE_IMMEDIATE,
0056     DISPCLK_CHANGE_MODE_RAMPING,
0057 };
0058
0059 enum pixel_rate_div {
0060    PIXEL_RATE_DIV_BY_1 = 0,
0061    PIXEL_RATE_DIV_BY_2 = 1,
0062    PIXEL_RATE_DIV_BY_4 = 3,
0063    PIXEL_RATE_DIV_NA = 0xF
0064 };
0065
0066 struct dccg {
0067     struct dc_context *ctx;
0068     const struct dccg_funcs *funcs;
0069     int pipe_dppclk_khz[MAX_PIPES];
0070     int ref_dppclk;
0071     //int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
0072     //int audio_dtbclk_khz;/* TODO needs to be removed */
0073     //int ref_dtbclk_khz;/* TODO needs to be removed */
0074 };
0075
0076 struct dtbclk_dto_params {
0077     const struct dc_crtc_timing *timing;
0078     int otg_inst;
0079     int pixclk_khz;
0080     int req_audio_dtbclk_khz;
0081     int num_odm_segments;
0082     int ref_dtbclk_khz;
0083     bool is_hdmi;
0084 };
0085
0086 struct dccg_funcs {
0087     void (*update_dpp_dto)(struct dccg *dccg,
0088             int dpp_inst,
0089             int req_dppclk);
0090     void (*get_dccg_ref_freq)(struct dccg *dccg,
0091             unsigned int xtalin_freq_inKhz,
0092             unsigned int *dccg_ref_freq_inKhz);
0093     void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
0094             bool en);
0095     void (*otg_add_pixel)(struct dccg *dccg,
0096             uint32_t otg_inst);
0097     void (*otg_drop_pixel)(struct dccg *dccg,
0098             uint32_t otg_inst);
0099     void (*dccg_init)(struct dccg *dccg);
0100
0101     void (*set_dpstreamclk)(
0102             struct dccg *dccg,
0103             enum streamclk_source src,
0104             int otg_inst,
0105             int dp_hpo_inst);
0106
0107     void (*enable_symclk32_se)(
0108             struct dccg *dccg,
0109             int hpo_se_inst,
0110             enum phyd32clk_clock_source phyd32clk);
0111
0112     void (*disable_symclk32_se)(
0113             struct dccg *dccg,
0114             int hpo_se_inst);
0115
0116     void (*enable_symclk32_le)(
0117             struct dccg *dccg,
0118             int hpo_le_inst,
0119             enum phyd32clk_clock_source phyd32clk);
0120
0121     void (*disable_symclk32_le)(
0122             struct dccg *dccg,
0123             int hpo_le_inst);
0124
0125     void (*set_physymclk)(
0126             struct dccg *dccg,
0127             int phy_inst,
0128             enum physymclk_clock_source clk_src,
0129             bool force_enable);
0130
0131     void (*set_dtbclk_dto)(
0132             struct dccg *dccg,
0133             const struct dtbclk_dto_params *params);
0134
0135     void (*set_audio_dtbclk_dto)(
0136             struct dccg *dccg,
0137             const struct dtbclk_dto_params *params);
0138
0139     void (*set_dispclk_change_mode)(
0140             struct dccg *dccg,
0141             enum dentist_dispclk_change_mode change_mode);
0142
0143     void (*disable_dsc)(
0144         struct dccg *dccg,
0145         int inst);
0146
0147     void (*enable_dsc)(
0148         struct dccg *dccg,
0149         int inst);
0150
0151 void (*set_pixel_rate_div)(
0152         struct dccg *dccg,
0153         uint32_t otg_inst,
0154         enum pixel_rate_div k1,
0155         enum pixel_rate_div k2);
0156
0157 void (*set_valid_pixel_rate)(
0158         struct dccg *dccg,
0159     int ref_dtbclk_khz,
0160         int otg_inst,
0161         int pixclk_khz);
0162
0163 };
0164
0165 #endif //__DAL_DCCG_H__