inc/hw/clk_mgr_internal.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DAL_CLK_MGR_INTERNAL_H__
0027 #define __DAL_CLK_MGR_INTERNAL_H__
0028
0029 #include "clk_mgr.h"
0030 #include "dc.h"
0031
0032 /*
0033  * only thing needed from here is MEMORY_TYPE_MULTIPLIER_CZ, which is also
0034  * used in resource, perhaps this should be defined somewhere more common.
0035  */
0036 #include "resource.h"
0037
0038
0039 /* Starting DID for each range */
0040 enum dentist_base_divider_id {
0041     DENTIST_BASE_DID_1 = 0x08,
0042     DENTIST_BASE_DID_2 = 0x40,
0043     DENTIST_BASE_DID_3 = 0x60,
0044     DENTIST_BASE_DID_4 = 0x7e,
0045     DENTIST_MAX_DID = 0x7f
0046 };
0047
0048 /* Starting point and step size for each divider range.*/
0049 enum dentist_divider_range {
0050     DENTIST_DIVIDER_RANGE_1_START = 8,   /* 2.00  */
0051     DENTIST_DIVIDER_RANGE_1_STEP  = 1,   /* 0.25  */
0052     DENTIST_DIVIDER_RANGE_2_START = 64,  /* 16.00 */
0053     DENTIST_DIVIDER_RANGE_2_STEP  = 2,   /* 0.50  */
0054     DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
0055     DENTIST_DIVIDER_RANGE_3_STEP  = 4,   /* 1.00  */
0056     DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */
0057     DENTIST_DIVIDER_RANGE_4_STEP  = 264, /* 66.00 */
0058     DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
0059 };
0060
0061 /*
0062  ***************************************************************************************
0063  ****************** Clock Manager Private Macros and Defines ***************************
0064  ***************************************************************************************
0065  */
0066
0067 /* Macros */
0068
0069 #define TO_CLK_MGR_INTERNAL(clk_mgr)\
0070     container_of(clk_mgr, struct clk_mgr_internal, base)
0071
0072 #define CTX \
0073     clk_mgr->base.ctx
0074
0075 #define DC_LOGGER \
0076     clk_mgr->base.ctx->logger
0077
0078
0079
0080
0081 #define CLK_BASE(inst) \
0082     CLK_BASE_INNER(inst)
0083
0084 #define CLK_SRI(reg_name, block, inst)\
0085     .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
0086                     mm ## block ## _ ## inst ## _ ## reg_name
0087
0088 #define CLK_COMMON_REG_LIST_DCE_BASE() \
0089     .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
0090     .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
0091
0092 #if defined(CONFIG_DRM_AMD_DC_SI)
0093 #define CLK_COMMON_REG_LIST_DCE60_BASE() \
0094     SR(DENTIST_DISPCLK_CNTL)
0095 #endif
0096
0097 #define CLK_COMMON_REG_LIST_DCN_BASE() \
0098     SR(DENTIST_DISPCLK_CNTL)
0099
0100 #define VBIOS_SMU_MSG_BOX_REG_LIST_RV() \
0101     .MP1_SMN_C2PMSG_91 = mmMP1_SMN_C2PMSG_91, \
0102     .MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \
0103     .MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67
0104
0105 #define CLK_COMMON_REG_LIST_DCN_201() \
0106     SR(DENTIST_DISPCLK_CNTL), \
0107     CLK_SRI(CLK4_CLK_PLL_REQ, CLK4, 0), \
0108     CLK_SRI(CLK4_CLK2_CURRENT_CNT, CLK4, 0)
0109
0110 #define CLK_REG_LIST_NV10() \
0111     SR(DENTIST_DISPCLK_CNTL), \
0112     CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
0113     CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
0114
0115 #define CLK_REG_LIST_DCN3()   \
0116     CLK_COMMON_REG_LIST_DCN_BASE(), \
0117     CLK_SRI(CLK0_CLK_PLL_REQ,   CLK02, 0), \
0118     CLK_SRI(CLK0_CLK2_DFS_CNTL, CLK02, 0)
0119
0120 #define CLK_SF(reg_name, field_name, post_fix)\
0121     .field_name = reg_name ## __ ## field_name ## post_fix
0122
0123 #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
0124     CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
0125     CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
0126
0127 #if defined(CONFIG_DRM_AMD_DC_SI)
0128 #define CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \
0129     CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
0130     CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
0131 #endif
0132
0133 #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
0134     CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
0135     CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
0136
0137 #define CLK_MASK_SH_LIST_RV1(mask_sh) \
0138     CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
0139     CLK_SF(MP1_SMN_C2PMSG_67, CONTENT, mask_sh),\
0140     CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\
0141     CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh),
0142
0143 #define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \
0144     CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
0145     CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
0146     CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh)
0147
0148 #define CLK_MASK_SH_LIST_NV10(mask_sh) \
0149     CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
0150     CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\
0151     CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh)
0152
0153 #define CLK_COMMON_MASK_SH_LIST_DCN201_BASE(mask_sh) \
0154     CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
0155     CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
0156     CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh),\
0157     CLK_SF(CLK4_0_CLK4_CLK_PLL_REQ, FbMult_int, mask_sh)
0158
0159 #define CLK_REG_LIST_DCN32()      \
0160     SR(DENTIST_DISPCLK_CNTL), \
0161     CLK_SR_DCN32(CLK1_CLK_PLL_REQ), \
0162     CLK_SR_DCN32(CLK1_CLK0_DFS_CNTL), \
0163     CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \
0164     CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \
0165     CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \
0166     CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL)
0167
0168 #define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
0169     CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
0170     CLK_SF(CLK1_CLK_PLL_REQ, FbMult_int, mask_sh),\
0171     CLK_SF(CLK1_CLK_PLL_REQ, FbMult_frac, mask_sh)
0172
0173 #define CLK_REG_LIST_DCN321()     \
0174     SR(DENTIST_DISPCLK_CNTL), \
0175     CLK_SR_DCN321(CLK0_CLK_PLL_REQ,   CLK01, 0), \
0176     CLK_SR_DCN321(CLK0_CLK0_DFS_CNTL, CLK01, 0), \
0177     CLK_SR_DCN321(CLK0_CLK1_DFS_CNTL, CLK01, 0), \
0178     CLK_SR_DCN321(CLK0_CLK2_DFS_CNTL, CLK01, 0), \
0179     CLK_SR_DCN321(CLK0_CLK3_DFS_CNTL, CLK01, 0), \
0180     CLK_SR_DCN321(CLK0_CLK4_DFS_CNTL, CLK01, 0)
0181
0182 #define CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) \
0183     CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
0184     CLK_SF(CLK0_CLK_PLL_REQ, FbMult_int, mask_sh),\
0185     CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh)
0186
0187 #define CLK_REG_FIELD_LIST(type) \
0188     type DPREFCLK_SRC_SEL; \
0189     type DENTIST_DPREFCLK_WDIVIDER; \
0190     type DENTIST_DISPCLK_WDIVIDER; \
0191     type DENTIST_DISPCLK_CHG_DONE;
0192
0193 /*
0194  ***************************************************************************************
0195  ****************** Clock Manager Private Structures ***********************************
0196  ***************************************************************************************
0197  */
0198 #define CLK20_REG_FIELD_LIST(type) \
0199     type DENTIST_DPPCLK_WDIVIDER; \
0200     type DENTIST_DPPCLK_CHG_DONE; \
0201     type FbMult_int; \
0202     type FbMult_frac;
0203
0204 #define VBIOS_SMU_REG_FIELD_LIST(type) \
0205     type CONTENT;
0206
0207 struct clk_mgr_shift {
0208     CLK_REG_FIELD_LIST(uint8_t)
0209     CLK20_REG_FIELD_LIST(uint8_t)
0210     VBIOS_SMU_REG_FIELD_LIST(uint32_t)
0211 };
0212
0213 struct clk_mgr_mask {
0214     CLK_REG_FIELD_LIST(uint32_t)
0215     CLK20_REG_FIELD_LIST(uint32_t)
0216     VBIOS_SMU_REG_FIELD_LIST(uint32_t)
0217 };
0218
0219 struct clk_mgr_registers {
0220     uint32_t DPREFCLK_CNTL;
0221     uint32_t DENTIST_DISPCLK_CNTL;
0222     uint32_t CLK4_CLK2_CURRENT_CNT;
0223     uint32_t CLK4_CLK_PLL_REQ;
0224
0225     uint32_t CLK3_CLK2_DFS_CNTL;
0226     uint32_t CLK3_CLK_PLL_REQ;
0227
0228     uint32_t CLK0_CLK2_DFS_CNTL;
0229     uint32_t CLK0_CLK_PLL_REQ;
0230
0231     uint32_t CLK1_CLK_PLL_REQ;
0232     uint32_t CLK1_CLK0_DFS_CNTL;
0233     uint32_t CLK1_CLK1_DFS_CNTL;
0234     uint32_t CLK1_CLK2_DFS_CNTL;
0235     uint32_t CLK1_CLK3_DFS_CNTL;
0236     uint32_t CLK1_CLK4_DFS_CNTL;
0237
0238     uint32_t CLK0_CLK0_DFS_CNTL;
0239     uint32_t CLK0_CLK1_DFS_CNTL;
0240     uint32_t CLK0_CLK3_DFS_CNTL;
0241     uint32_t CLK0_CLK4_DFS_CNTL;
0242
0243     uint32_t MP1_SMN_C2PMSG_67;
0244     uint32_t MP1_SMN_C2PMSG_83;
0245     uint32_t MP1_SMN_C2PMSG_91;
0246 };
0247
0248 enum clock_type {
0249     clock_type_dispclk = 1,
0250     clock_type_dcfclk,
0251     clock_type_socclk,
0252     clock_type_pixelclk,
0253     clock_type_phyclk,
0254     clock_type_dppclk,
0255     clock_type_fclk,
0256     clock_type_dcfdsclk,
0257     clock_type_dscclk,
0258     clock_type_uclk,
0259     clock_type_dramclk,
0260 };
0261
0262
0263 struct state_dependent_clocks {
0264     int display_clk_khz;
0265     int pixel_clk_khz;
0266 };
0267
0268 struct clk_mgr_internal {
0269     struct clk_mgr base;
0270     int smu_ver;
0271     struct pp_smu_funcs *pp_smu;
0272     struct clk_mgr_internal_funcs *funcs;
0273
0274     struct dccg *dccg;
0275
0276     /*
0277      * For backwards compatbility with previous implementation
0278      * TODO: remove these after everything transitions to new pattern
0279      * Rationale is that clk registers change a lot across DCE versions
0280      * and a shared data structure doesn't really make sense.
0281      */
0282     const struct clk_mgr_registers *regs;
0283     const struct clk_mgr_shift *clk_mgr_shift;
0284     const struct clk_mgr_mask *clk_mgr_mask;
0285
0286     struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
0287
0288     /*TODO: figure out which of the below fields should be here vs in asic specific portion */
0289     /* Cache the status of DFS-bypass feature*/
0290     bool dfs_bypass_enabled;
0291     /* True if the DFS-bypass feature is enabled and active. */
0292     bool dfs_bypass_active;
0293
0294     uint32_t dfs_ref_freq_khz;
0295     /*
0296      * Cache the display clock returned by VBIOS if DFS-bypass is enabled.
0297      * This is basically "Crystal Frequency In KHz" (XTALIN) frequency
0298      */
0299     int dfs_bypass_disp_clk;
0300
0301     /**
0302      * @ss_on_dprefclk:
0303      *
0304      * True if spread spectrum is enabled on the DP ref clock.
0305      */
0306     bool ss_on_dprefclk;
0307
0308     /**
0309      * @xgmi_enabled:
0310      *
0311      * True if xGMI is enabled. On VG20, both audio and display clocks need
0312      * to be adjusted with the WAFL link's SS info if xGMI is enabled.
0313      */
0314     bool xgmi_enabled;
0315
0316     /**
0317      * @dprefclk_ss_percentage:
0318      *
0319      * DPREFCLK SS percentage (if down-spread enabled).
0320      *
0321      * Note that if XGMI is enabled, the SS info (percentage and divider)
0322      * from the WAFL link is used instead. This is decided during
0323      * dce_clk_mgr initialization.
0324      */
0325     int dprefclk_ss_percentage;
0326
0327     /**
0328      * @dprefclk_ss_divider:
0329      *
0330      * DPREFCLK SS percentage Divider (100 or 1000).
0331      */
0332     int dprefclk_ss_divider;
0333
0334     enum dm_pp_clocks_state max_clks_state;
0335     enum dm_pp_clocks_state cur_min_clks_state;
0336     bool periodic_retraining_disabled;
0337
0338     unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
0339
0340     bool smu_present;
0341     void *wm_range_table;
0342     long long wm_range_table_addr;
0343
0344     bool dpm_present;
0345 };
0346
0347 struct clk_mgr_internal_funcs {
0348     int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
0349     int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);
0350 };
0351
0352
0353 /*
0354  ***************************************************************************************
0355  ****************** Clock Manager Level Helper functions *******************************
0356  ***************************************************************************************
0357  */
0358
0359
0360 static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk)
0361 {
0362     return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
0363 }
0364
0365 static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
0366 {
0367     if (cur_support != calc_support) {
0368         if (calc_support && safe_to_lower)
0369             return true;
0370         else if (!calc_support && !safe_to_lower)
0371             return true;
0372     }
0373
0374     return false;
0375 }
0376
0377 static inline int khz_to_mhz_ceil(int khz)
0378 {
0379     return (khz + 999) / 1000;
0380 }
0381
0382 int clk_mgr_helper_get_active_display_cnt(
0383         struct dc *dc,
0384         struct dc_state *context);
0385
0386 int clk_mgr_helper_get_active_plane_cnt(
0387         struct dc *dc,
0388         struct dc_state *context);
0389
0390
0391
0392 #endif //__DAL_CLK_MGR_INTERNAL_H__