dc/inc/dcn_calcs.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 /**
0027  * Bandwidth and Watermark calculations interface.
0028  * (Refer to "DCEx_mode_support.xlsm" from Perforce.)
0029  */
0030 #ifndef __DCN_CALCS_H__
0031 #define __DCN_CALCS_H__
0032
0033 #include "bw_fixed.h"
0034 #include "../dml/display_mode_lib.h"
0035
0036
0037 struct dc;
0038 struct dc_state;
0039
0040 /*******************************************************************************
0041  * DCN data structures.
0042  ******************************************************************************/
0043
0044 #define number_of_planes   6
0045 #define number_of_planes_minus_one   5
0046 #define number_of_states   4
0047 #define number_of_states_plus_one   5
0048
0049 #define ddr4_dram_width   64
0050 #define ddr4_dram_factor_single_Channel   16
0051 enum dcn_bw_defs {
0052     dcn_bw_v_min0p65,
0053     dcn_bw_v_mid0p72,
0054     dcn_bw_v_nom0p8,
0055     dcn_bw_v_max0p9,
0056     dcn_bw_v_max0p91,
0057     dcn_bw_no_support = 5,
0058     dcn_bw_yes,
0059     dcn_bw_hor,
0060     dcn_bw_vert,
0061     dcn_bw_override,
0062     dcn_bw_rgb_sub_64,
0063     dcn_bw_rgb_sub_32,
0064     dcn_bw_rgb_sub_16,
0065     dcn_bw_no,
0066     dcn_bw_sw_linear,
0067     dcn_bw_sw_4_kb_d,
0068     dcn_bw_sw_4_kb_d_x,
0069     dcn_bw_sw_64_kb_d,
0070     dcn_bw_sw_64_kb_d_t,
0071     dcn_bw_sw_64_kb_d_x,
0072     dcn_bw_sw_var_d,
0073     dcn_bw_sw_var_d_x,
0074     dcn_bw_yuv420_sub_8,
0075     dcn_bw_sw_4_kb_s,
0076     dcn_bw_sw_4_kb_s_x,
0077     dcn_bw_sw_64_kb_s,
0078     dcn_bw_sw_64_kb_s_t,
0079     dcn_bw_sw_64_kb_s_x,
0080     dcn_bw_writeback,
0081     dcn_bw_444,
0082     dcn_bw_dp,
0083     dcn_bw_420,
0084     dcn_bw_hdmi,
0085     dcn_bw_sw_var_s,
0086     dcn_bw_sw_var_s_x,
0087     dcn_bw_yuv420_sub_10,
0088     dcn_bw_supported_in_v_active,
0089     dcn_bw_supported_in_v_blank,
0090     dcn_bw_not_supported,
0091     dcn_bw_na,
0092     dcn_bw_encoder_8bpc,
0093     dcn_bw_encoder_10bpc,
0094     dcn_bw_encoder_12bpc,
0095     dcn_bw_encoder_16bpc,
0096 };
0097
0098 /*bounding box parameters*/
0099 /*mode parameters*/
0100 /*system configuration*/
0101 /* display configuration*/
0102 struct dcn_bw_internal_vars {
0103     float voltage[number_of_states_plus_one + 1];
0104     float max_dispclk[number_of_states_plus_one + 1];
0105     float max_dppclk[number_of_states_plus_one + 1];
0106     float dcfclk_per_state[number_of_states_plus_one + 1];
0107     float phyclk_per_state[number_of_states_plus_one + 1];
0108     float fabric_and_dram_bandwidth_per_state[number_of_states_plus_one + 1];
0109     float sr_exit_time;
0110     float sr_enter_plus_exit_time;
0111     float dram_clock_change_latency;
0112     float urgent_latency;
0113     float write_back_latency;
0114     float percent_of_ideal_drambw_received_after_urg_latency;
0115     float dcfclkv_max0p9;
0116     float dcfclkv_nom0p8;
0117     float dcfclkv_mid0p72;
0118     float dcfclkv_min0p65;
0119     float max_dispclk_vmax0p9;
0120     float max_dppclk_vmax0p9;
0121     float max_dispclk_vnom0p8;
0122     float max_dppclk_vnom0p8;
0123     float max_dispclk_vmid0p72;
0124     float max_dppclk_vmid0p72;
0125     float max_dispclk_vmin0p65;
0126     float max_dppclk_vmin0p65;
0127     float socclk;
0128     float fabric_and_dram_bandwidth_vmax0p9;
0129     float fabric_and_dram_bandwidth_vnom0p8;
0130     float fabric_and_dram_bandwidth_vmid0p72;
0131     float fabric_and_dram_bandwidth_vmin0p65;
0132     float round_trip_ping_latency_cycles;
0133     float urgent_out_of_order_return_per_channel;
0134     float number_of_channels;
0135     float vmm_page_size;
0136     float return_bus_width;
0137     float rob_buffer_size_in_kbyte;
0138     float det_buffer_size_in_kbyte;
0139     float dpp_output_buffer_pixels;
0140     float opp_output_buffer_lines;
0141     float pixel_chunk_size_in_kbyte;
0142     float pte_chunk_size;
0143     float meta_chunk_size;
0144     float writeback_chunk_size;
0145     enum dcn_bw_defs odm_capability;
0146     enum dcn_bw_defs dsc_capability;
0147     float line_buffer_size;
0148     enum dcn_bw_defs is_line_buffer_bpp_fixed;
0149     float line_buffer_fixed_bpp;
0150     float max_line_buffer_lines;
0151     float writeback_luma_buffer_size;
0152     float writeback_chroma_buffer_size;
0153     float max_num_dpp;
0154     float max_num_writeback;
0155     float max_dchub_topscl_throughput;
0156     float max_pscl_tolb_throughput;
0157     float max_lb_tovscl_throughput;
0158     float max_vscl_tohscl_throughput;
0159     float max_hscl_ratio;
0160     float max_vscl_ratio;
0161     float max_hscl_taps;
0162     float max_vscl_taps;
0163     float under_scan_factor;
0164     float phyclkv_max0p9;
0165     float phyclkv_nom0p8;
0166     float phyclkv_mid0p72;
0167     float phyclkv_min0p65;
0168     float pte_buffer_size_in_requests;
0169     float dispclk_ramping_margin;
0170     float downspreading;
0171     float max_inter_dcn_tile_repeaters;
0172     enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
0173     enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed;
0174     int mode;
0175     float viewport_width[number_of_planes_minus_one + 1];
0176     float htotal[number_of_planes_minus_one + 1];
0177     float vtotal[number_of_planes_minus_one + 1];
0178     float v_sync_plus_back_porch[number_of_planes_minus_one + 1];
0179     float vactive[number_of_planes_minus_one + 1];
0180     float pixel_clock[number_of_planes_minus_one + 1]; /*MHz*/
0181     float viewport_height[number_of_planes_minus_one + 1];
0182     enum dcn_bw_defs dcc_enable[number_of_planes_minus_one + 1];
0183     float dcc_rate[number_of_planes_minus_one + 1];
0184     enum dcn_bw_defs source_scan[number_of_planes_minus_one + 1];
0185     float lb_bit_per_pixel[number_of_planes_minus_one + 1];
0186     enum dcn_bw_defs source_pixel_format[number_of_planes_minus_one + 1];
0187     enum dcn_bw_defs source_surface_mode[number_of_planes_minus_one + 1];
0188     enum dcn_bw_defs output_format[number_of_planes_minus_one + 1];
0189     enum dcn_bw_defs output_deep_color[number_of_planes_minus_one + 1];
0190     enum dcn_bw_defs output[number_of_planes_minus_one + 1];
0191     float scaler_rec_out_width[number_of_planes_minus_one + 1];
0192     float scaler_recout_height[number_of_planes_minus_one + 1];
0193     float underscan_output[number_of_planes_minus_one + 1];
0194     float interlace_output[number_of_planes_minus_one + 1];
0195     float override_hta_ps[number_of_planes_minus_one + 1];
0196     float override_vta_ps[number_of_planes_minus_one + 1];
0197     float override_hta_pschroma[number_of_planes_minus_one + 1];
0198     float override_vta_pschroma[number_of_planes_minus_one + 1];
0199     float urgent_latency_support_us[number_of_planes_minus_one + 1];
0200     float h_ratio[number_of_planes_minus_one + 1];
0201     float v_ratio[number_of_planes_minus_one + 1];
0202     float htaps[number_of_planes_minus_one + 1];
0203     float vtaps[number_of_planes_minus_one + 1];
0204     float hta_pschroma[number_of_planes_minus_one + 1];
0205     float vta_pschroma[number_of_planes_minus_one + 1];
0206     enum dcn_bw_defs pte_enable;
0207     enum dcn_bw_defs synchronized_vblank;
0208     enum dcn_bw_defs ta_pscalculation;
0209     int voltage_override_level;
0210     int number_of_active_planes;
0211     int voltage_level;
0212     enum dcn_bw_defs immediate_flip_supported;
0213     float dcfclk;
0214     float max_phyclk;
0215     float fabric_and_dram_bandwidth;
0216     float dpp_per_plane_per_ratio[1 + 1][number_of_planes_minus_one + 1];
0217     enum dcn_bw_defs dispclk_dppclk_support_per_ratio[1 + 1];
0218     float required_dispclk_per_ratio[1 + 1];
0219     enum dcn_bw_defs error_message[1 + 1];
0220     int dispclk_dppclk_ratio;
0221     float dpp_per_plane[number_of_planes_minus_one + 1];
0222     float det_buffer_size_y[number_of_planes_minus_one + 1];
0223     float det_buffer_size_c[number_of_planes_minus_one + 1];
0224     float swath_height_y[number_of_planes_minus_one + 1];
0225     float swath_height_c[number_of_planes_minus_one + 1];
0226     enum dcn_bw_defs final_error_message;
0227     float frequency;
0228     float header_line;
0229     float header;
0230     enum dcn_bw_defs voltage_override;
0231     enum dcn_bw_defs allow_different_hratio_vratio;
0232     float acceptable_quality_hta_ps;
0233     float acceptable_quality_vta_ps;
0234     float no_of_dpp[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
0235     float swath_width_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
0236     float swath_height_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
0237     float swath_height_cper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
0238     float urgent_latency_support_us_per_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
0239     float v_ratio_pre_ywith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
0240     float v_ratio_pre_cwith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
0241     float required_prefetch_pixel_data_bw_with_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
0242     float v_ratio_pre_ywithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
0243     float v_ratio_pre_cwithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
0244     float required_prefetch_pixel_data_bw_without_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
0245     enum dcn_bw_defs prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
0246     enum dcn_bw_defs prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
0247     enum dcn_bw_defs v_ratio_in_prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
0248     enum dcn_bw_defs v_ratio_in_prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
0249     float required_dispclk[number_of_states_plus_one + 1][1 + 1];
0250     enum dcn_bw_defs dispclk_dppclk_support[number_of_states_plus_one + 1][1 + 1];
0251     enum dcn_bw_defs total_available_pipes_support[number_of_states_plus_one + 1][1 + 1];
0252     float total_number_of_active_dpp[number_of_states_plus_one + 1][1 + 1];
0253     float total_number_of_dcc_active_dpp[number_of_states_plus_one + 1][1 + 1];
0254     enum dcn_bw_defs urgent_latency_support[number_of_states_plus_one + 1][1 + 1];
0255     enum dcn_bw_defs mode_support_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
0256     enum dcn_bw_defs mode_support_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
0257     float return_bw_per_state[number_of_states_plus_one + 1];
0258     enum dcn_bw_defs dio_support[number_of_states_plus_one + 1];
0259     float urgent_round_trip_and_out_of_order_latency_per_state[number_of_states_plus_one + 1];
0260     enum dcn_bw_defs rob_support[number_of_states_plus_one + 1];
0261     enum dcn_bw_defs bandwidth_support[number_of_states_plus_one + 1];
0262     float prefetch_bw[number_of_planes_minus_one + 1];
0263     float meta_pte_bytes_per_frame[number_of_planes_minus_one + 1];
0264     float meta_row_bytes[number_of_planes_minus_one + 1];
0265     float dpte_bytes_per_row[number_of_planes_minus_one + 1];
0266     float prefetch_lines_y[number_of_planes_minus_one + 1];
0267     float prefetch_lines_c[number_of_planes_minus_one + 1];
0268     float max_num_sw_y[number_of_planes_minus_one + 1];
0269     float max_num_sw_c[number_of_planes_minus_one + 1];
0270     float line_times_for_prefetch[number_of_planes_minus_one + 1];
0271     float lines_for_meta_pte_with_immediate_flip[number_of_planes_minus_one + 1];
0272     float lines_for_meta_pte_without_immediate_flip[number_of_planes_minus_one + 1];
0273     float lines_for_meta_and_dpte_row_with_immediate_flip[number_of_planes_minus_one + 1];
0274     float lines_for_meta_and_dpte_row_without_immediate_flip[number_of_planes_minus_one + 1];
0275     float min_dppclk_using_single_dpp[number_of_planes_minus_one + 1];
0276     float swath_width_ysingle_dpp[number_of_planes_minus_one + 1];
0277     float byte_per_pixel_in_dety[number_of_planes_minus_one + 1];
0278     float byte_per_pixel_in_detc[number_of_planes_minus_one + 1];
0279     float number_of_dpp_required_for_det_and_lb_size[number_of_planes_minus_one + 1];
0280     float required_phyclk[number_of_planes_minus_one + 1];
0281     float read256_block_height_y[number_of_planes_minus_one + 1];
0282     float read256_block_width_y[number_of_planes_minus_one + 1];
0283     float read256_block_height_c[number_of_planes_minus_one + 1];
0284     float read256_block_width_c[number_of_planes_minus_one + 1];
0285     float max_swath_height_y[number_of_planes_minus_one + 1];
0286     float max_swath_height_c[number_of_planes_minus_one + 1];
0287     float min_swath_height_y[number_of_planes_minus_one + 1];
0288     float min_swath_height_c[number_of_planes_minus_one + 1];
0289     float read_bandwidth[number_of_planes_minus_one + 1];
0290     float write_bandwidth[number_of_planes_minus_one + 1];
0291     float pscl_factor[number_of_planes_minus_one + 1];
0292     float pscl_factor_chroma[number_of_planes_minus_one + 1];
0293     enum dcn_bw_defs scale_ratio_support;
0294     enum dcn_bw_defs source_format_pixel_and_scan_support;
0295     float total_read_bandwidth_consumed_gbyte_per_second;
0296     float total_write_bandwidth_consumed_gbyte_per_second;
0297     float total_bandwidth_consumed_gbyte_per_second;
0298     enum dcn_bw_defs dcc_enabled_in_any_plane;
0299     float return_bw_todcn_per_state;
0300     float critical_point;
0301     enum dcn_bw_defs writeback_latency_support;
0302     float required_output_bw;
0303     float total_number_of_active_writeback;
0304     enum dcn_bw_defs total_available_writeback_support;
0305     float maximum_swath_width;
0306     float number_of_dpp_required_for_det_size;
0307     float number_of_dpp_required_for_lb_size;
0308     float min_dispclk_using_single_dpp;
0309     float min_dispclk_using_dual_dpp;
0310     enum dcn_bw_defs viewport_size_support;
0311     float swath_width_granularity_y;
0312     float rounded_up_max_swath_size_bytes_y;
0313     float swath_width_granularity_c;
0314     float rounded_up_max_swath_size_bytes_c;
0315     float lines_in_det_luma;
0316     float lines_in_det_chroma;
0317     float effective_lb_latency_hiding_source_lines_luma;
0318     float effective_lb_latency_hiding_source_lines_chroma;
0319     float effective_detlb_lines_luma;
0320     float effective_detlb_lines_chroma;
0321     float projected_dcfclk_deep_sleep;
0322     float meta_req_height_y;
0323     float meta_req_width_y;
0324     float meta_surface_width_y;
0325     float meta_surface_height_y;
0326     float meta_pte_bytes_per_frame_y;
0327     float meta_row_bytes_y;
0328     float macro_tile_block_size_bytes_y;
0329     float macro_tile_block_height_y;
0330     float data_pte_req_height_y;
0331     float data_pte_req_width_y;
0332     float dpte_bytes_per_row_y;
0333     float meta_req_height_c;
0334     float meta_req_width_c;
0335     float meta_surface_width_c;
0336     float meta_surface_height_c;
0337     float meta_pte_bytes_per_frame_c;
0338     float meta_row_bytes_c;
0339     float macro_tile_block_size_bytes_c;
0340     float macro_tile_block_height_c;
0341     float macro_tile_block_width_c;
0342     float data_pte_req_height_c;
0343     float data_pte_req_width_c;
0344     float dpte_bytes_per_row_c;
0345     float v_init_y;
0346     float max_partial_sw_y;
0347     float v_init_c;
0348     float max_partial_sw_c;
0349     float dst_x_after_scaler;
0350     float dst_y_after_scaler;
0351     float time_calc;
0352     float v_update_offset[number_of_planes_minus_one + 1][2];
0353     float total_repeater_delay;
0354     float v_update_width[number_of_planes_minus_one + 1][2];
0355     float v_ready_offset[number_of_planes_minus_one + 1][2];
0356     float time_setup;
0357     float extra_latency;
0358     float maximum_vstartup;
0359     float bw_available_for_immediate_flip;
0360     float total_immediate_flip_bytes[number_of_planes_minus_one + 1];
0361     float time_for_meta_pte_with_immediate_flip;
0362     float time_for_meta_pte_without_immediate_flip;
0363     float time_for_meta_and_dpte_row_with_immediate_flip;
0364     float time_for_meta_and_dpte_row_without_immediate_flip;
0365     float line_times_to_request_prefetch_pixel_data_with_immediate_flip;
0366     float line_times_to_request_prefetch_pixel_data_without_immediate_flip;
0367     float maximum_read_bandwidth_with_prefetch_with_immediate_flip;
0368     float maximum_read_bandwidth_with_prefetch_without_immediate_flip;
0369     float voltage_level_with_immediate_flip;
0370     float voltage_level_without_immediate_flip;
0371     float total_number_of_active_dpp_per_ratio[1 + 1];
0372     float byte_per_pix_dety;
0373     float byte_per_pix_detc;
0374     float read256_bytes_block_height_y;
0375     float read256_bytes_block_width_y;
0376     float read256_bytes_block_height_c;
0377     float read256_bytes_block_width_c;
0378     float maximum_swath_height_y;
0379     float maximum_swath_height_c;
0380     float minimum_swath_height_y;
0381     float minimum_swath_height_c;
0382     float swath_width;
0383     float prefetch_bandwidth[number_of_planes_minus_one + 1];
0384     float v_init_pre_fill_y[number_of_planes_minus_one + 1];
0385     float v_init_pre_fill_c[number_of_planes_minus_one + 1];
0386     float max_num_swath_y[number_of_planes_minus_one + 1];
0387     float max_num_swath_c[number_of_planes_minus_one + 1];
0388     float prefill_y[number_of_planes_minus_one + 1];
0389     float prefill_c[number_of_planes_minus_one + 1];
0390     float v_startup[number_of_planes_minus_one + 1];
0391     enum dcn_bw_defs allow_dram_clock_change_during_vblank[number_of_planes_minus_one + 1];
0392     float allow_dram_self_refresh_during_vblank[number_of_planes_minus_one + 1];
0393     float v_ratio_prefetch_y[number_of_planes_minus_one + 1];
0394     float v_ratio_prefetch_c[number_of_planes_minus_one + 1];
0395     float destination_lines_for_prefetch[number_of_planes_minus_one + 1];
0396     float destination_lines_to_request_vm_inv_blank[number_of_planes_minus_one + 1];
0397     float destination_lines_to_request_row_in_vblank[number_of_planes_minus_one + 1];
0398     float min_ttuv_blank[number_of_planes_minus_one + 1];
0399     float byte_per_pixel_dety[number_of_planes_minus_one + 1];
0400     float byte_per_pixel_detc[number_of_planes_minus_one + 1];
0401     float swath_width_y[number_of_planes_minus_one + 1];
0402     float lines_in_dety[number_of_planes_minus_one + 1];
0403     float lines_in_dety_rounded_down_to_swath[number_of_planes_minus_one + 1];
0404     float lines_in_detc[number_of_planes_minus_one + 1];
0405     float lines_in_detc_rounded_down_to_swath[number_of_planes_minus_one + 1];
0406     float full_det_buffering_time_y[number_of_planes_minus_one + 1];
0407     float full_det_buffering_time_c[number_of_planes_minus_one + 1];
0408     float active_dram_clock_change_latency_margin[number_of_planes_minus_one + 1];
0409     float v_blank_dram_clock_change_latency_margin[number_of_planes_minus_one + 1];
0410     float dcfclk_deep_sleep_per_plane[number_of_planes_minus_one + 1];
0411     float read_bandwidth_plane_luma[number_of_planes_minus_one + 1];
0412     float read_bandwidth_plane_chroma[number_of_planes_minus_one + 1];
0413     float display_pipe_line_delivery_time_luma[number_of_planes_minus_one + 1];
0414     float display_pipe_line_delivery_time_chroma[number_of_planes_minus_one + 1];
0415     float display_pipe_line_delivery_time_luma_prefetch[number_of_planes_minus_one + 1];
0416     float display_pipe_line_delivery_time_chroma_prefetch[number_of_planes_minus_one + 1];
0417     float pixel_pte_bytes_per_row[number_of_planes_minus_one + 1];
0418     float meta_pte_bytes_frame[number_of_planes_minus_one + 1];
0419     float meta_row_byte[number_of_planes_minus_one + 1];
0420     float prefetch_source_lines_y[number_of_planes_minus_one + 1];
0421     float prefetch_source_lines_c[number_of_planes_minus_one + 1];
0422     float pscl_throughput[number_of_planes_minus_one + 1];
0423     float pscl_throughput_chroma[number_of_planes_minus_one + 1];
0424     float output_bpphdmi[number_of_planes_minus_one + 1];
0425     float output_bppdp4_lane_hbr[number_of_planes_minus_one + 1];
0426     float output_bppdp4_lane_hbr2[number_of_planes_minus_one + 1];
0427     float output_bppdp4_lane_hbr3[number_of_planes_minus_one + 1];
0428     float max_vstartup_lines[number_of_planes_minus_one + 1];
0429     float dispclk_with_ramping;
0430     float dispclk_without_ramping;
0431     float dppclk_using_single_dpp_luma;
0432     float dppclk_using_single_dpp;
0433     float dppclk_using_single_dpp_chroma;
0434     enum dcn_bw_defs odm_capable;
0435     float dispclk;
0436     float dppclk;
0437     float return_bandwidth_to_dcn;
0438     enum dcn_bw_defs dcc_enabled_any_plane;
0439     float return_bw;
0440     float critical_compression;
0441     float total_data_read_bandwidth;
0442     float total_active_dpp;
0443     float total_dcc_active_dpp;
0444     float urgent_round_trip_and_out_of_order_latency;
0445     float last_pixel_of_line_extra_watermark;
0446     float data_fabric_line_delivery_time_luma;
0447     float data_fabric_line_delivery_time_chroma;
0448     float urgent_extra_latency;
0449     float urgent_watermark;
0450     float ptemeta_urgent_watermark;
0451     float dram_clock_change_watermark;
0452     float total_active_writeback;
0453     float writeback_dram_clock_change_watermark;
0454     float min_full_det_buffering_time;
0455     float frame_time_for_min_full_det_buffering_time;
0456     float average_read_bandwidth_gbyte_per_second;
0457     float part_of_burst_that_fits_in_rob;
0458     float stutter_burst_time;
0459     float stutter_efficiency_not_including_vblank;
0460     float smallest_vblank;
0461     float v_blank_time;
0462     float stutter_efficiency;
0463     float dcf_clk_deep_sleep;
0464     float stutter_exit_watermark;
0465     float stutter_enter_plus_exit_watermark;
0466     float effective_det_plus_lb_lines_luma;
0467     float urgent_latency_support_us_luma;
0468     float effective_det_plus_lb_lines_chroma;
0469     float urgent_latency_support_us_chroma;
0470     float min_urgent_latency_support_us;
0471     float non_urgent_latency_tolerance;
0472     float block_height256_bytes_y;
0473     float block_height256_bytes_c;
0474     float meta_request_width_y;
0475     float meta_surf_width_y;
0476     float meta_surf_height_y;
0477     float meta_pte_bytes_frame_y;
0478     float meta_row_byte_y;
0479     float macro_tile_size_byte_y;
0480     float macro_tile_height_y;
0481     float pixel_pte_req_height_y;
0482     float pixel_pte_req_width_y;
0483     float pixel_pte_bytes_per_row_y;
0484     float meta_request_width_c;
0485     float meta_surf_width_c;
0486     float meta_surf_height_c;
0487     float meta_pte_bytes_frame_c;
0488     float meta_row_byte_c;
0489     float macro_tile_size_bytes_c;
0490     float macro_tile_height_c;
0491     float pixel_pte_req_height_c;
0492     float pixel_pte_req_width_c;
0493     float pixel_pte_bytes_per_row_c;
0494     float max_partial_swath_y;
0495     float max_partial_swath_c;
0496     float t_calc;
0497     float next_prefetch_mode;
0498     float v_startup_lines;
0499     enum dcn_bw_defs planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw;
0500     enum dcn_bw_defs planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4;
0501     enum dcn_bw_defs planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2;
0502     enum dcn_bw_defs v_ratio_prefetch_more_than4;
0503     enum dcn_bw_defs destination_line_times_for_prefetch_less_than2;
0504     float prefetch_mode;
0505     float dstx_after_scaler;
0506     float dsty_after_scaler;
0507     float v_update_offset_pix[number_of_planes_minus_one + 1];
0508     float total_repeater_delay_time;
0509     float v_update_width_pix[number_of_planes_minus_one + 1];
0510     float v_ready_offset_pix[number_of_planes_minus_one + 1];
0511     float t_setup;
0512     float t_wait;
0513     float bandwidth_available_for_immediate_flip;
0514     float tot_immediate_flip_bytes;
0515     float max_rd_bandwidth;
0516     float time_for_fetching_meta_pte;
0517     float time_for_fetching_row_in_vblank;
0518     float lines_to_request_prefetch_pixel_data;
0519     float required_prefetch_pix_data_bw;
0520     enum dcn_bw_defs prefetch_mode_supported;
0521     float active_dp_ps;
0522     float lb_latency_hiding_source_lines_y;
0523     float lb_latency_hiding_source_lines_c;
0524     float effective_lb_latency_hiding_y;
0525     float effective_lb_latency_hiding_c;
0526     float dpp_output_buffer_lines_y;
0527     float dpp_output_buffer_lines_c;
0528     float dppopp_buffering_y;
0529     float max_det_buffering_time_y;
0530     float active_dram_clock_change_latency_margin_y;
0531     float dppopp_buffering_c;
0532     float max_det_buffering_time_c;
0533     float active_dram_clock_change_latency_margin_c;
0534     float writeback_dram_clock_change_latency_margin;
0535     float min_active_dram_clock_change_margin;
0536     float v_blank_of_min_active_dram_clock_change_margin;
0537     float second_min_active_dram_clock_change_margin;
0538     float min_vblank_dram_clock_change_margin;
0539     float dram_clock_change_margin;
0540     float dram_clock_change_support;
0541     float wr_bandwidth;
0542     float max_used_bw;
0543 };
0544
0545 struct dcn_soc_bounding_box {
0546     float sr_exit_time; /*us*/
0547     float sr_enter_plus_exit_time; /*us*/
0548     float urgent_latency; /*us*/
0549     float write_back_latency; /*us*/
0550     float percent_of_ideal_drambw_received_after_urg_latency; /*%*/
0551     int max_request_size; /*bytes*/
0552     float dcfclkv_max0p9; /*MHz*/
0553     float dcfclkv_nom0p8; /*MHz*/
0554     float dcfclkv_mid0p72; /*MHz*/
0555     float dcfclkv_min0p65; /*MHz*/
0556     float max_dispclk_vmax0p9; /*MHz*/
0557     float max_dispclk_vmid0p72; /*MHz*/
0558     float max_dispclk_vnom0p8; /*MHz*/
0559     float max_dispclk_vmin0p65; /*MHz*/
0560     float max_dppclk_vmax0p9; /*MHz*/
0561     float max_dppclk_vnom0p8; /*MHz*/
0562     float max_dppclk_vmid0p72; /*MHz*/
0563     float max_dppclk_vmin0p65; /*MHz*/
0564     float socclk; /*MHz*/
0565     float fabric_and_dram_bandwidth_vmax0p9; /*GB/s*/
0566     float fabric_and_dram_bandwidth_vnom0p8; /*GB/s*/
0567     float fabric_and_dram_bandwidth_vmid0p72; /*GB/s*/
0568     float fabric_and_dram_bandwidth_vmin0p65; /*GB/s*/
0569     float phyclkv_max0p9; /*MHz*/
0570     float phyclkv_nom0p8; /*MHz*/
0571     float phyclkv_mid0p72; /*MHz*/
0572     float phyclkv_min0p65; /*MHz*/
0573     float downspreading; /*%*/
0574     int round_trip_ping_latency_cycles; /*DCFCLK Cycles*/
0575     int urgent_out_of_order_return_per_channel; /*bytes*/
0576     int number_of_channels;
0577     int vmm_page_size; /*bytes*/
0578     float dram_clock_change_latency; /*us*/
0579     int return_bus_width; /*bytes*/
0580     float percent_disp_bw_limit; /*%*/
0581 };
0582 extern const struct dcn_soc_bounding_box dcn10_soc_defaults;
0583
0584 struct dcn_ip_params {
0585     float rob_buffer_size_in_kbyte;
0586     float det_buffer_size_in_kbyte;
0587     float dpp_output_buffer_pixels;
0588     float opp_output_buffer_lines;
0589     float pixel_chunk_size_in_kbyte;
0590     enum dcn_bw_defs pte_enable;
0591     int pte_chunk_size; /*kbytes*/
0592     int meta_chunk_size; /*kbytes*/
0593     int writeback_chunk_size; /*kbytes*/
0594     enum dcn_bw_defs odm_capability;
0595     enum dcn_bw_defs dsc_capability;
0596     int line_buffer_size; /*bit*/
0597     int max_line_buffer_lines;
0598     enum dcn_bw_defs is_line_buffer_bpp_fixed;
0599     int line_buffer_fixed_bpp;
0600     int writeback_luma_buffer_size; /*kbytes*/
0601     int writeback_chroma_buffer_size; /*kbytes*/
0602     int max_num_dpp;
0603     int max_num_writeback;
0604     int max_dchub_topscl_throughput; /*pixels/dppclk*/
0605     int max_pscl_tolb_throughput; /*pixels/dppclk*/
0606     int max_lb_tovscl_throughput; /*pixels/dppclk*/
0607     int max_vscl_tohscl_throughput; /*pixels/dppclk*/
0608     float max_hscl_ratio;
0609     float max_vscl_ratio;
0610     int max_hscl_taps;
0611     int max_vscl_taps;
0612     int pte_buffer_size_in_requests;
0613     float dispclk_ramping_margin; /*%*/
0614     float under_scan_factor;
0615     int max_inter_dcn_tile_repeaters;
0616     enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
0617     enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed;
0618     int dcfclk_cstate_latency;
0619 };
0620 extern const struct dcn_ip_params dcn10_ip_defaults;
0621
0622 bool dcn_validate_bandwidth(
0623         struct dc *dc,
0624         struct dc_state *context,
0625         bool fast_validate);
0626
0627 unsigned int dcn_find_dcfclk_suits_all(
0628     const struct dc *dc,
0629     struct dc_clocks *clocks);
0630
0631 void dcn_bw_update_from_pplib(struct dc *dc);
0632 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc);
0633 void dcn_bw_sync_calcs_and_dml(struct dc *dc);
0634
0635 enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode);
0636
0637 #endif /* __DCN_CALCS_H__ */
0638