dc/inc/dc_link_dp.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_LINK_DP_H__
0027 #define __DC_LINK_DP_H__
0028
0029 #define LINK_TRAINING_ATTEMPTS 4
0030 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
0031 #define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/
0032 #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/
0033 #define MAX_MTP_SLOT_COUNT 64
0034 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
0035 #define TRAINING_AUX_RD_INTERVAL 100 //us
0036 #define LINK_AUX_WAKE_TIMEOUT_MS 1500 // Timeout when trying to wake unresponsive DPRX.
0037
0038 struct dc_link;
0039 struct dc_stream_state;
0040 struct dc_link_settings;
0041
0042 enum {
0043     LINK_TRAINING_MAX_RETRY_COUNT = 5,
0044     /* to avoid infinite loop where-in the receiver
0045      * switches between different VS
0046      */
0047     LINK_TRAINING_MAX_CR_RETRY = 100,
0048     /*
0049      * Some receivers fail to train on first try and are good
0050      * on subsequent tries. 2 retries should be plenty. If we
0051      * don't have a successful training then we don't expect to
0052      * ever get one.
0053      */
0054     LINK_TRAINING_MAX_VERIFY_RETRY = 2,
0055     PEAK_FACTOR_X1000 = 1006,
0056 };
0057
0058 struct dc_link_settings dp_get_max_link_cap(struct dc_link *link);
0059
0060 bool dp_verify_link_cap_with_retries(
0061     struct dc_link *link,
0062     struct dc_link_settings *known_limit_link_setting,
0063     int attempts);
0064
0065 bool dp_validate_mode_timing(
0066     struct dc_link *link,
0067     const struct dc_crtc_timing *timing);
0068
0069 bool decide_edp_link_settings(struct dc_link *link,
0070         struct dc_link_settings *link_setting,
0071         uint32_t req_bw);
0072
0073 bool decide_link_settings(
0074     struct dc_stream_state *stream,
0075     struct dc_link_settings *link_setting);
0076
0077 bool perform_link_training_with_retries(
0078     const struct dc_link_settings *link_setting,
0079     bool skip_video_pattern,
0080     int attempts,
0081     struct pipe_ctx *pipe_ctx,
0082     enum signal_type signal,
0083     bool do_fallback);
0084
0085 bool hpd_rx_irq_check_link_loss_status(
0086     struct dc_link *link,
0087     union hpd_irq_data *hpd_irq_dpcd_data);
0088
0089 bool is_mst_supported(struct dc_link *link);
0090
0091 bool detect_dp_sink_caps(struct dc_link *link);
0092
0093 void detect_edp_sink_caps(struct dc_link *link);
0094
0095 bool is_dp_active_dongle(const struct dc_link *link);
0096
0097 bool is_dp_branch_device(const struct dc_link *link);
0098
0099 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing);
0100
0101 void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
0102
0103 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
0104 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
0105
0106 bool dp_overwrite_extended_receiver_cap(struct dc_link *link);
0107
0108 void dpcd_set_source_specific_data(struct dc_link *link);
0109
0110 void dpcd_write_cable_id_to_dprx(struct dc_link *link);
0111
0112 /* Write DPCD link configuration data. */
0113 enum dc_status dpcd_set_link_settings(
0114     struct dc_link *link,
0115     const struct link_training_settings *lt_settings);
0116 /* Write DPCD drive settings. */
0117 enum dc_status dpcd_set_lane_settings(
0118     struct dc_link *link,
0119     const struct link_training_settings *link_training_setting,
0120     uint32_t offset);
0121 /* Read training status and adjustment requests from DPCD. */
0122 enum dc_status dp_get_lane_status_and_lane_adjust(
0123     struct dc_link *link,
0124     const struct link_training_settings *link_training_setting,
0125     union lane_status ln_status[LANE_COUNT_DP_MAX],
0126     union lane_align_status_updated *ln_align,
0127     union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
0128     uint32_t offset);
0129
0130 void dp_wait_for_training_aux_rd_interval(
0131     struct dc_link *link,
0132     uint32_t wait_in_micro_secs);
0133
0134 bool dp_is_cr_done(enum dc_lane_count ln_count,
0135     union lane_status *dpcd_lane_status);
0136
0137 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
0138     union lane_status *dpcd_lane_status);
0139
0140 bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
0141     union lane_status *dpcd_lane_status);
0142 bool dp_is_symbol_locked(enum dc_lane_count ln_count,
0143     union lane_status *dpcd_lane_status);
0144 bool dp_is_interlane_aligned(union lane_align_status_updated align_status);
0145
0146 bool dp_is_max_vs_reached(
0147     const struct link_training_settings *lt_settings);
0148 void dp_hw_to_dpcd_lane_settings(
0149     const struct link_training_settings *lt_settings,
0150     const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
0151     union dpcd_training_lane dpcd_lane_settings[]);
0152 void dp_decide_lane_settings(
0153     const struct link_training_settings *lt_settings,
0154     const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
0155     struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
0156     union dpcd_training_lane dpcd_lane_settings[]);
0157
0158 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval);
0159
0160 enum dpcd_training_patterns
0161     dc_dp_training_pattern_to_dpcd_training_pattern(
0162     struct dc_link *link,
0163     enum dc_dp_training_pattern pattern);
0164
0165 uint8_t dc_dp_initialize_scrambling_data_symbols(
0166     struct dc_link *link,
0167     enum dc_dp_training_pattern pattern);
0168
0169 enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready);
0170 void dp_set_fec_enable(struct dc_link *link, bool enable);
0171 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
0172 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update);
0173 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
0174 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
0175 bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);
0176
0177 /* Initialize output parameter lt_settings. */
0178 void dp_decide_training_settings(
0179     struct dc_link *link,
0180     const struct dc_link_settings *link_setting,
0181     struct link_training_settings *lt_settings);
0182
0183 /* Convert PHY repeater count read from DPCD uint8_t. */
0184 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count);
0185
0186 /* Check DPCD training status registers to detect link loss. */
0187 enum link_training_result dp_check_link_loss_status(
0188         struct dc_link *link,
0189         const struct link_training_settings *link_training_setting);
0190
0191 enum dc_status dpcd_configure_lttpr_mode(
0192         struct dc_link *link,
0193         struct link_training_settings *lt_settings);
0194
0195 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings);
0196 bool dp_retrieve_lttpr_cap(struct dc_link *link);
0197 bool dpcd_write_128b_132b_sst_payload_allocation_table(
0198         const struct dc_stream_state *stream,
0199         struct dc_link *link,
0200         struct link_mst_stream_allocation_table *proposed_table,
0201         bool allocate);
0202
0203 enum dc_status dpcd_configure_channel_coding(
0204         struct dc_link *link,
0205         struct link_training_settings *lt_settings);
0206
0207 bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link);
0208
0209 struct fixed31_32 calculate_sst_avg_time_slots_per_mtp(
0210         const struct dc_stream_state *stream,
0211         const struct dc_link *link);
0212 void enable_dp_hpo_output(struct dc_link *link,
0213         const struct link_resource *link_res,
0214         const struct dc_link_settings *link_settings);
0215 void disable_dp_hpo_output(struct dc_link *link,
0216         const struct link_resource *link_res,
0217         enum signal_type signal);
0218
0219 void setup_dp_hpo_stream(struct pipe_ctx *pipe_ctx, bool enable);
0220 bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx);
0221 void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd);
0222 void dp_receiver_power_ctrl(struct dc_link *link, bool on);
0223 void dp_source_sequence_trace(struct dc_link *link, uint8_t dp_test_mode);
0224 void dp_enable_link_phy(
0225     struct dc_link *link,
0226     const struct link_resource *link_res,
0227     enum signal_type signal,
0228     enum clock_source_id clock_source,
0229     const struct dc_link_settings *link_settings);
0230 void edp_add_delay_for_T9(struct dc_link *link);
0231 bool edp_receiver_ready_T9(struct dc_link *link);
0232 bool edp_receiver_ready_T7(struct dc_link *link);
0233
0234 void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_res,
0235         enum signal_type signal);
0236
0237 void dp_disable_link_phy_mst(struct dc_link *link, const struct link_resource *link_res,
0238         enum signal_type signal);
0239
0240 bool dp_set_hw_training_pattern(
0241         struct dc_link *link,
0242         const struct link_resource *link_res,
0243         enum dc_dp_training_pattern pattern,
0244         uint32_t offset);
0245
0246 void dp_set_hw_lane_settings(
0247         struct dc_link *link,
0248         const struct link_resource *link_res,
0249         const struct link_training_settings *link_settings,
0250         uint32_t offset);
0251
0252 void dp_set_hw_test_pattern(
0253         struct dc_link *link,
0254         const struct link_resource *link_res,
0255         enum dp_test_pattern test_pattern,
0256         uint8_t *custom_pattern,
0257         uint32_t custom_pattern_size);
0258
0259 void dp_retrain_link_dp_test(struct dc_link *link,
0260         struct dc_link_settings *link_setting,
0261         bool skip_video_pattern);
0262 #endif /* __DC_LINK_DP_H__ */