dc/inc/clock_source.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_CLOCK_SOURCE_H__
0027 #define __DC_CLOCK_SOURCE_H__
0028
0029 #include "dc_types.h"
0030 #include "include/grph_object_id.h"
0031 #include "include/bios_parser_types.h"
0032
0033 struct clock_source;
0034
0035 struct spread_spectrum_data {
0036     uint32_t percentage;        /*> In unit of 0.01% or 0.001%*/
0037     uint32_t percentage_divider;    /*> 100 or 1000 */
0038     uint32_t freq_range_khz;
0039     uint32_t modulation_freq_hz;
0040
0041     struct spread_spectrum_flags flags;
0042 };
0043
0044 struct delta_sigma_data {
0045     uint32_t feedback_amount;
0046     uint32_t nfrac_amount;
0047     uint32_t ds_frac_size;
0048     uint32_t ds_frac_amount;
0049 };
0050
0051 /**
0052  *  Pixel Clock Parameters structure
0053  *  These parameters are required as input
0054  *  when calculating Pixel Clock Dividers for requested Pixel Clock
0055  */
0056 struct pixel_clk_flags {
0057     uint32_t ENABLE_SS:1;
0058     uint32_t DISPLAY_BLANKED:1;
0059     uint32_t PROGRAM_PIXEL_CLOCK:1;
0060     uint32_t PROGRAM_ID_CLOCK:1;
0061     uint32_t SUPPORT_YCBCR420:1;
0062 };
0063
0064 /**
0065  *  Display Port HW De spread of Reference Clock related Parameters structure
0066  *  Store it once at boot for later usage
0067   */
0068 struct csdp_ref_clk_ds_params {
0069     bool hw_dso_n_dp_ref_clk;
0070 /* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
0071     uint32_t avg_dp_ref_clk_khz;
0072 /* Average DP Reference clock (in KHz)*/
0073     uint32_t ss_percentage_on_dp_ref_clk;
0074 /* DP Reference clock SS percentage
0075  * (not to be mixed with DP IDCLK SS from PLL Settings)*/
0076     uint32_t ss_percentage_divider;
0077 /* DP Reference clock SS percentage divider */
0078 };
0079
0080 struct pixel_clk_params {
0081     uint32_t requested_pix_clk_100hz;
0082 /*> Requested Pixel Clock
0083  * (based on Video Timing standard used for requested mode)*/
0084     uint32_t requested_sym_clk; /* in KHz */
0085 /*> Requested Sym Clock (relevant only for display port)*/
0086     uint32_t dp_ref_clk; /* in KHz */
0087 /*> DP reference clock - calculated only for DP signal for specific cases*/
0088     struct graphics_object_id encoder_object_id;
0089 /*> Encoder object Id - needed by VBIOS Exec table*/
0090     enum signal_type signal_type;
0091 /*> signalType -> Encoder Mode - needed by VBIOS Exec table*/
0092     enum controller_id controller_id;
0093 /*> ControllerId - which controller using this PLL*/
0094     enum dc_color_depth color_depth;
0095     struct csdp_ref_clk_ds_params de_spread_params;
0096 /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
0097     enum dc_pixel_encoding pixel_encoding;
0098     struct pixel_clk_flags flags;
0099 };
0100
0101 /**
0102  *  Pixel Clock Dividers structure with desired Pixel Clock
0103  *  (adjusted after VBIOS exec table),
0104  *  with actually calculated Clock and reference Crystal frequency
0105  */
0106 struct pll_settings {
0107     uint32_t actual_pix_clk_100hz;
0108     uint32_t adjusted_pix_clk_100hz;
0109     uint32_t calculated_pix_clk_100hz;
0110     uint32_t vco_freq;
0111     uint32_t reference_freq;
0112     uint32_t reference_divider;
0113     uint32_t feedback_divider;
0114     uint32_t fract_feedback_divider;
0115     uint32_t pix_clk_post_divider;
0116     uint32_t ss_percentage;
0117     bool use_external_clk;
0118 };
0119
0120 struct calc_pll_clock_source_init_data {
0121     struct dc_bios *bp;
0122     uint32_t min_pix_clk_pll_post_divider;
0123     uint32_t max_pix_clk_pll_post_divider;
0124     uint32_t min_pll_ref_divider;
0125     uint32_t max_pll_ref_divider;
0126     uint32_t min_override_input_pxl_clk_pll_freq_khz;
0127 /* if not 0, override the firmware info */
0128
0129     uint32_t max_override_input_pxl_clk_pll_freq_khz;
0130 /* if not 0, override the firmware info */
0131
0132     uint32_t num_fract_fb_divider_decimal_point;
0133 /* number of decimal point for fractional feedback divider value */
0134
0135     uint32_t num_fract_fb_divider_decimal_point_precision;
0136 /* number of decimal point to round off for fractional feedback divider value*/
0137     struct dc_context *ctx;
0138
0139 };
0140
0141 struct calc_pll_clock_source {
0142     uint32_t ref_freq_khz;
0143     uint32_t min_pix_clock_pll_post_divider;
0144     uint32_t max_pix_clock_pll_post_divider;
0145     uint32_t min_pll_ref_divider;
0146     uint32_t max_pll_ref_divider;
0147
0148     uint32_t max_vco_khz;
0149     uint32_t min_vco_khz;
0150     uint32_t min_pll_input_freq_khz;
0151     uint32_t max_pll_input_freq_khz;
0152
0153     uint32_t fract_fb_divider_decimal_points_num;
0154     uint32_t fract_fb_divider_factor;
0155     uint32_t fract_fb_divider_precision;
0156     uint32_t fract_fb_divider_precision_factor;
0157     struct dc_context *ctx;
0158 };
0159
0160 struct clock_source_funcs {
0161     bool (*cs_power_down)(
0162             struct clock_source *);
0163     bool (*program_pix_clk)(
0164             struct clock_source *,
0165             struct pixel_clk_params *,
0166             enum dp_link_encoding encoding,
0167             struct pll_settings *);
0168     uint32_t (*get_pix_clk_dividers)(
0169             struct clock_source *,
0170             struct pixel_clk_params *,
0171             struct pll_settings *);
0172     bool (*get_pixel_clk_frequency_100hz)(
0173             const struct clock_source *clock_source,
0174             unsigned int inst,
0175             unsigned int *pixel_clk_khz);
0176     bool (*override_dp_pix_clk)(
0177             struct clock_source *clock_source,
0178             unsigned int inst,
0179             unsigned int pixel_clk,
0180             unsigned int ref_clk);
0181 };
0182
0183 struct clock_source {
0184     const struct clock_source_funcs *funcs;
0185     struct dc_context *ctx;
0186     enum clock_source_id id;
0187     bool dp_clk_src;
0188 };
0189
0190 #endif