dc/gpio/ddc_regs.h

0001 /*
0002  * Copyright 2012-16 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_
0027 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_
0028
0029 #include "gpio_regs.h"
0030
0031 /****************************** new register headers */
0032 /*** following in header */
0033
0034 #define DDC_GPIO_REG_LIST_ENTRY(type,cd,id) \
0035     .type ## _reg =   REG(DC_GPIO_DDC ## id ## _ ## type),\
0036     .type ## _mask =  DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\
0037     .type ## _shift = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## __SHIFT
0038
0039 #define DDC_GPIO_REG_LIST(cd,id) \
0040     {\
0041     DDC_GPIO_REG_LIST_ENTRY(MASK,cd,id),\
0042     DDC_GPIO_REG_LIST_ENTRY(A,cd,id),\
0043     DDC_GPIO_REG_LIST_ENTRY(EN,cd,id),\
0044     DDC_GPIO_REG_LIST_ENTRY(Y,cd,id)\
0045     }
0046
0047 #define DDC_REG_LIST(cd,id) \
0048     DDC_GPIO_REG_LIST(cd,id),\
0049     .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
0050
0051     #define DDC_REG_LIST_DCN2(cd, id) \
0052     DDC_GPIO_REG_LIST(cd, id),\
0053     .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\
0054     .phy_aux_cntl = REG(PHY_AUX_CNTL), \
0055     .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
0056
0057 #define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\
0058     .type ## _reg =   REG(DC_GPIO_DDCVGA_ ## type),\
0059     .type ## _mask =  DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\
0060     .type ## _shift = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## __SHIFT
0061
0062 #define DDC_GPIO_VGA_REG_LIST(cd) \
0063     {\
0064     DDC_GPIO_VGA_REG_LIST_ENTRY(MASK,cd),\
0065     DDC_GPIO_VGA_REG_LIST_ENTRY(A,cd),\
0066     DDC_GPIO_VGA_REG_LIST_ENTRY(EN,cd),\
0067     DDC_GPIO_VGA_REG_LIST_ENTRY(Y,cd)\
0068     }
0069
0070 #define DDC_VGA_REG_LIST(cd) \
0071     DDC_GPIO_VGA_REG_LIST(cd),\
0072     .ddc_setup = mmDC_I2C_DDCVGA_SETUP
0073
0074 #define DDC_GPIO_I2C_REG_LIST_ENTRY(type,cd) \
0075     .type ## _reg =   REG(DC_GPIO_I2CPAD_ ## type),\
0076     .type ## _mask =  DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\
0077     .type ## _shift = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## __SHIFT
0078
0079 #define DDC_GPIO_I2C_REG_LIST(cd) \
0080     {\
0081     DDC_GPIO_I2C_REG_LIST_ENTRY(MASK,cd),\
0082     DDC_GPIO_I2C_REG_LIST_ENTRY(A,cd),\
0083     DDC_GPIO_I2C_REG_LIST_ENTRY(EN,cd),\
0084     DDC_GPIO_I2C_REG_LIST_ENTRY(Y,cd)\
0085     }
0086
0087 #define DDC_I2C_REG_LIST(cd) \
0088     DDC_GPIO_I2C_REG_LIST(cd),\
0089     .ddc_setup = 0
0090
0091 #define DDC_I2C_REG_LIST_DCN2(cd) \
0092     DDC_GPIO_I2C_REG_LIST(cd),\
0093     .ddc_setup = 0,\
0094     .phy_aux_cntl = REG(PHY_AUX_CNTL), \
0095     .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
0096 #define DDC_MASK_SH_LIST_COMMON(mask_sh) \
0097         SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
0098         SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\
0099         SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_MODE, mask_sh),\
0100         SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1DATA_PD_EN, mask_sh),\
0101         SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1CLK_PD_EN, mask_sh),\
0102         SF_DDC(DC_GPIO_DDC1_MASK, AUX_PAD1_MODE, mask_sh)
0103
0104 #define DDC_MASK_SH_LIST(mask_sh) \
0105         DDC_MASK_SH_LIST_COMMON(mask_sh),\
0106         SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\
0107         SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh)
0108
0109 #define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \
0110     {DDC_MASK_SH_LIST_COMMON(mask_sh),\
0111     0,\
0112     0,\
0113     (PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\
0114     (DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)}
0115
0116 struct ddc_registers {
0117     struct gpio_registers gpio;
0118     uint32_t ddc_setup;
0119     uint32_t phy_aux_cntl;
0120     uint32_t dc_gpio_aux_ctrl_5;
0121 };
0122
0123 struct ddc_sh_mask {
0124     /* i2c_dd_setup */
0125     uint32_t DC_I2C_DDC1_ENABLE;
0126     uint32_t DC_I2C_DDC1_EDID_DETECT_ENABLE;
0127     uint32_t DC_I2C_DDC1_EDID_DETECT_MODE;
0128     /* ddc1_mask */
0129     uint32_t DC_GPIO_DDC1DATA_PD_EN;
0130     uint32_t DC_GPIO_DDC1CLK_PD_EN;
0131     uint32_t AUX_PAD1_MODE;
0132     /* i2cpad_mask */
0133     uint32_t DC_GPIO_SDA_PD_DIS;
0134     uint32_t DC_GPIO_SCL_PD_DIS;
0135     //phy_aux_cntl
0136     uint32_t AUX_PAD_RXSEL;
0137     uint32_t DDC_PAD_I2CMODE;
0138 };
0139
0140
0141
0142 /*** following in dc_resource */
0143
0144 #define ddc_data_regs(id) \
0145 {\
0146     DDC_REG_LIST(DATA,id)\
0147 }
0148
0149 #define ddc_clk_regs(id) \
0150 {\
0151     DDC_REG_LIST(CLK,id)\
0152 }
0153
0154 #define ddc_vga_data_regs \
0155 {\
0156     DDC_VGA_REG_LIST(DATA)\
0157 }
0158
0159 #define ddc_vga_clk_regs \
0160 {\
0161     DDC_VGA_REG_LIST(CLK)\
0162 }
0163
0164 #define ddc_i2c_data_regs \
0165 {\
0166     DDC_I2C_REG_LIST(SDA)\
0167 }
0168
0169 #define ddc_i2c_clk_regs \
0170 {\
0171     DDC_I2C_REG_LIST(SCL)\
0172 }
0173 #define ddc_data_regs_dcn2(id) \
0174 {\
0175     DDC_REG_LIST_DCN2(DATA, id)\
0176 }
0177
0178 #define ddc_clk_regs_dcn2(id) \
0179 {\
0180     DDC_REG_LIST_DCN2(CLK, id)\
0181 }
0182
0183 #define ddc_i2c_data_regs_dcn2 \
0184 {\
0185     DDC_I2C_REG_LIST_DCN2(SDA)\
0186 }
0187
0188 #define ddc_i2c_clk_regs_dcn2 \
0189 {\
0190     DDC_REG_LIST_DCN2(SCL)\
0191 }
0192
0193
0194 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */