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0001 /*
0002  * Copyright 2022 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 /*
0027  * Pre-requisites: headers required by header of this unit
0028  */
0029 #include "hw_translate_dcn32.h"
0030 
0031 #include "dm_services.h"
0032 #include "include/gpio_types.h"
0033 #include "../hw_translate.h"
0034 
0035 #include "dcn/dcn_3_2_0_offset.h"
0036 #include "dcn/dcn_3_2_0_sh_mask.h"
0037 
0038 #define DCN_BASE__INST0_SEG2                       0x000034C0
0039 
0040 /* begin *********************
0041  * macros to expend register list macro defined in HW object header file */
0042 
0043 /* DCN */
0044 #define block HPD
0045 #define reg_num 0
0046 
0047 #undef BASE_INNER
0048 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0049 
0050 #define BASE(seg) BASE_INNER(seg)
0051 
0052 #undef REG
0053 #define REG(reg_name)\
0054         BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
0055 #define SF_HPD(reg_name, field_name, post_fix)\
0056     .field_name = reg_name ## __ ## field_name ## post_fix
0057 
0058 
0059 /* macros to expend register list macro defined in HW object header file
0060  * end *********************/
0061 
0062 
0063 static bool offset_to_id(
0064     uint32_t offset,
0065     uint32_t mask,
0066     enum gpio_id *id,
0067     uint32_t *en)
0068 {
0069     switch (offset) {
0070     /* GENERIC */
0071     case REG(DC_GPIO_GENERIC_A):
0072         *id = GPIO_ID_GENERIC;
0073         switch (mask) {
0074         case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
0075             *en = GPIO_GENERIC_A;
0076             return true;
0077         case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
0078             *en = GPIO_GENERIC_B;
0079             return true;
0080         case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
0081             *en = GPIO_GENERIC_C;
0082             return true;
0083         case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
0084             *en = GPIO_GENERIC_D;
0085             return true;
0086         case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
0087             *en = GPIO_GENERIC_E;
0088             return true;
0089         case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
0090             *en = GPIO_GENERIC_F;
0091             return true;
0092         default:
0093             ASSERT_CRITICAL(false);
0094             return false;
0095         }
0096     break;
0097     /* HPD */
0098     case REG(DC_GPIO_HPD_A):
0099         *id = GPIO_ID_HPD;
0100         switch (mask) {
0101         case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
0102             *en = GPIO_HPD_1;
0103             return true;
0104         case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
0105             *en = GPIO_HPD_2;
0106             return true;
0107         case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
0108             *en = GPIO_HPD_3;
0109             return true;
0110         case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
0111             *en = GPIO_HPD_4;
0112             return true;
0113         case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
0114             *en = GPIO_HPD_5;
0115             return true;
0116         default:
0117             ASSERT_CRITICAL(false);
0118             return false;
0119         }
0120     break;
0121     /* REG(DC_GPIO_GENLK_MASK */
0122     case REG(DC_GPIO_GENLK_A):
0123         *id = GPIO_ID_GSL;
0124         switch (mask) {
0125         case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
0126             *en = GPIO_GSL_GENLOCK_CLOCK;
0127             return true;
0128         case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
0129             *en = GPIO_GSL_GENLOCK_VSYNC;
0130             return true;
0131         case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
0132             *en = GPIO_GSL_SWAPLOCK_A;
0133             return true;
0134         case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
0135             *en = GPIO_GSL_SWAPLOCK_B;
0136             return true;
0137         default:
0138             ASSERT_CRITICAL(false);
0139             return false;
0140         }
0141     break;
0142     /* DDC */
0143     /* we don't care about the GPIO_ID for DDC
0144      * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
0145      * directly in the create method */
0146     case REG(DC_GPIO_DDC1_A):
0147         *en = GPIO_DDC_LINE_DDC1;
0148         return true;
0149     case REG(DC_GPIO_DDC2_A):
0150         *en = GPIO_DDC_LINE_DDC2;
0151         return true;
0152     case REG(DC_GPIO_DDC3_A):
0153         *en = GPIO_DDC_LINE_DDC3;
0154         return true;
0155     case REG(DC_GPIO_DDC4_A):
0156         *en = GPIO_DDC_LINE_DDC4;
0157         return true;
0158     case REG(DC_GPIO_DDC5_A):
0159         *en = GPIO_DDC_LINE_DDC5;
0160         return true;
0161     case REG(DC_GPIO_DDCVGA_A):
0162         *en = GPIO_DDC_LINE_DDC_VGA;
0163         return true;
0164     default:
0165         ASSERT_CRITICAL(false);
0166         return false;
0167     }
0168 }
0169 
0170 static bool id_to_offset(
0171     enum gpio_id id,
0172     uint32_t en,
0173     struct gpio_pin_info *info)
0174 {
0175     bool result = true;
0176 
0177     switch (id) {
0178     case GPIO_ID_DDC_DATA:
0179         info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK;
0180         switch (en) {
0181         case GPIO_DDC_LINE_DDC1:
0182             info->offset = REG(DC_GPIO_DDC1_A);
0183         break;
0184         case GPIO_DDC_LINE_DDC2:
0185             info->offset = REG(DC_GPIO_DDC2_A);
0186         break;
0187         case GPIO_DDC_LINE_DDC3:
0188             info->offset = REG(DC_GPIO_DDC3_A);
0189         break;
0190         case GPIO_DDC_LINE_DDC4:
0191             info->offset = REG(DC_GPIO_DDC4_A);
0192         break;
0193         case GPIO_DDC_LINE_DDC5:
0194             info->offset = REG(DC_GPIO_DDC5_A);
0195         break;
0196         case GPIO_DDC_LINE_DDC_VGA:
0197             info->offset = REG(DC_GPIO_DDCVGA_A);
0198         break;
0199         case GPIO_DDC_LINE_I2C_PAD:
0200         default:
0201             ASSERT_CRITICAL(false);
0202             result = false;
0203         }
0204     break;
0205     case GPIO_ID_DDC_CLOCK:
0206         info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK;
0207         switch (en) {
0208         case GPIO_DDC_LINE_DDC1:
0209             info->offset = REG(DC_GPIO_DDC1_A);
0210         break;
0211         case GPIO_DDC_LINE_DDC2:
0212             info->offset = REG(DC_GPIO_DDC2_A);
0213         break;
0214         case GPIO_DDC_LINE_DDC3:
0215             info->offset = REG(DC_GPIO_DDC3_A);
0216         break;
0217         case GPIO_DDC_LINE_DDC4:
0218             info->offset = REG(DC_GPIO_DDC4_A);
0219         break;
0220         case GPIO_DDC_LINE_DDC5:
0221             info->offset = REG(DC_GPIO_DDC5_A);
0222         break;
0223         case GPIO_DDC_LINE_DDC_VGA:
0224             info->offset = REG(DC_GPIO_DDCVGA_A);
0225         break;
0226         case GPIO_DDC_LINE_I2C_PAD:
0227         default:
0228             ASSERT_CRITICAL(false);
0229             result = false;
0230         }
0231     break;
0232     case GPIO_ID_GENERIC:
0233         info->offset = REG(DC_GPIO_GENERIC_A);
0234         switch (en) {
0235         case GPIO_GENERIC_A:
0236             info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
0237         break;
0238         case GPIO_GENERIC_B:
0239             info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
0240         break;
0241         case GPIO_GENERIC_C:
0242             info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
0243         break;
0244         case GPIO_GENERIC_D:
0245             info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
0246         break;
0247         case GPIO_GENERIC_E:
0248             info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
0249         break;
0250         case GPIO_GENERIC_F:
0251             info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
0252         break;
0253         default:
0254             ASSERT_CRITICAL(false);
0255             result = false;
0256         }
0257     break;
0258     case GPIO_ID_HPD:
0259         info->offset = REG(DC_GPIO_HPD_A);
0260         switch (en) {
0261         case GPIO_HPD_1:
0262             info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
0263         break;
0264         case GPIO_HPD_2:
0265             info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
0266         break;
0267         case GPIO_HPD_3:
0268             info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
0269         break;
0270         case GPIO_HPD_4:
0271             info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
0272         break;
0273         case GPIO_HPD_5:
0274             info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
0275         break;
0276         default:
0277             ASSERT_CRITICAL(false);
0278             result = false;
0279         }
0280     break;
0281     case GPIO_ID_GSL:
0282         switch (en) {
0283         case GPIO_GSL_GENLOCK_CLOCK:
0284                 /*not implmented*/
0285             ASSERT_CRITICAL(false);
0286             result = false;
0287         break;
0288         case GPIO_GSL_GENLOCK_VSYNC:
0289             /*not implmented*/
0290             ASSERT_CRITICAL(false);
0291             result = false;
0292         break;
0293         case GPIO_GSL_SWAPLOCK_A:
0294             /*not implmented*/
0295             ASSERT_CRITICAL(false);
0296             result = false;
0297         break;
0298         case GPIO_GSL_SWAPLOCK_B:
0299             /*not implmented*/
0300             ASSERT_CRITICAL(false);
0301             result = false;
0302 
0303         break;
0304         default:
0305             ASSERT_CRITICAL(false);
0306             result = false;
0307         }
0308     break;
0309     case GPIO_ID_SYNC:
0310     case GPIO_ID_VIP_PAD:
0311     default:
0312         ASSERT_CRITICAL(false);
0313         result = false;
0314     }
0315 
0316     if (result) {
0317         info->offset_y = info->offset + 2;
0318         info->offset_en = info->offset + 1;
0319         info->offset_mask = info->offset - 1;
0320 
0321         info->mask_y = info->mask;
0322         info->mask_en = info->mask;
0323         info->mask_mask = info->mask;
0324     }
0325 
0326     return result;
0327 }
0328 
0329 /* function table */
0330 static const struct hw_translate_funcs funcs = {
0331     .offset_to_id = offset_to_id,
0332     .id_to_offset = id_to_offset,
0333 };
0334 
0335 /*
0336  * dal_hw_translate_dcn32_init
0337  *
0338  * @brief
0339  * Initialize Hw translate function pointers.
0340  *
0341  * @param
0342  * struct hw_translate *tr - [out] struct of function pointers
0343  *
0344  */
0345 void dal_hw_translate_dcn32_init(struct hw_translate *tr)
0346 {
0347     tr->funcs = &funcs;
0348 }
0349
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