dml/dsc/rc_calc_fpu.h

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __RC_CALC_FPU_H__
0027 #define __RC_CALC_FPU_H__
0028
0029 #include "os_types.h"
0030 #include <drm/display/drm_dsc.h>
0031
0032 #define QP_SET_SIZE 15
0033
0034 typedef int qp_set[QP_SET_SIZE];
0035
0036 struct rc_params {
0037     int      rc_quant_incr_limit0;
0038     int      rc_quant_incr_limit1;
0039     int      initial_fullness_offset;
0040     int      initial_xmit_delay;
0041     int      first_line_bpg_offset;
0042     int      second_line_bpg_offset;
0043     int      flatness_min_qp;
0044     int      flatness_max_qp;
0045     int      flatness_det_thresh;
0046     qp_set   qp_min;
0047     qp_set   qp_max;
0048     qp_set   ofs;
0049     int      rc_model_size;
0050     int      rc_edge_factor;
0051     int      rc_tgt_offset_hi;
0052     int      rc_tgt_offset_lo;
0053     int      rc_buf_thresh[QP_SET_SIZE - 1];
0054 };
0055
0056 enum colour_mode {
0057     CM_RGB,   /* 444 RGB */
0058     CM_444,   /* 444 YUV or simple 422 */
0059     CM_422,   /* native 422 */
0060     CM_420    /* native 420 */
0061 };
0062
0063 enum bits_per_comp {
0064     BPC_8  =  8,
0065     BPC_10 = 10,
0066     BPC_12 = 12
0067 };
0068
0069 enum max_min {
0070     DAL_MM_MIN = 0,
0071     DAL_MM_MAX = 1
0072 };
0073
0074 struct qp_entry {
0075     float         bpp;
0076     const qp_set  qps;
0077 };
0078
0079 typedef struct qp_entry qp_table[];
0080
0081 void _do_calc_rc_params(struct rc_params *rc,
0082         enum colour_mode cm,
0083         enum bits_per_comp bpc,
0084         u16 drm_bpp,
0085         bool is_navite_422_or_420,
0086         int slice_width,
0087         int slice_height,
0088         int minor_version);
0089
0090 #endif