dc/dml/dml_wrapper_translation.c

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifdef DML_WRAPPER_TRANSLATION_
0027
0028 static void gfx10array_mode_to_dml_params(
0029         enum array_mode_values array_mode,
0030         enum legacy_tiling_compat_level compat_level,
0031         unsigned int *sw_mode)
0032 {
0033     switch (array_mode) {
0034     case DC_ARRAY_LINEAR_ALLIGNED:
0035     case DC_ARRAY_LINEAR_GENERAL:
0036         *sw_mode = dm_sw_linear;
0037         break;
0038     case DC_ARRAY_2D_TILED_THIN1:
0039 // DC_LEGACY_TILING_ADDR_GEN_ZERO - undefined as per current code hence removed
0040 #if 0
0041         if (compat_level == DC_LEGACY_TILING_ADDR_GEN_ZERO)
0042             *sw_mode = dm_sw_gfx7_2d_thin_l_vp;
0043         else
0044             *sw_mode = dm_sw_gfx7_2d_thin_gl;
0045 #endif
0046         break;
0047     default:
0048         ASSERT(0); /* Not supported */
0049         break;
0050     }
0051 }
0052
0053 static void swizzle_to_dml_params(
0054         enum swizzle_mode_values swizzle,
0055         unsigned int *sw_mode)
0056 {
0057     switch (swizzle) {
0058     case DC_SW_LINEAR:
0059         *sw_mode = dm_sw_linear;
0060         break;
0061     case DC_SW_4KB_S:
0062         *sw_mode = dm_sw_4kb_s;
0063         break;
0064     case DC_SW_4KB_S_X:
0065         *sw_mode = dm_sw_4kb_s_x;
0066         break;
0067     case DC_SW_4KB_D:
0068         *sw_mode = dm_sw_4kb_d;
0069         break;
0070     case DC_SW_4KB_D_X:
0071         *sw_mode = dm_sw_4kb_d_x;
0072         break;
0073     case DC_SW_64KB_S:
0074         *sw_mode = dm_sw_64kb_s;
0075         break;
0076     case DC_SW_64KB_S_X:
0077         *sw_mode = dm_sw_64kb_s_x;
0078         break;
0079     case DC_SW_64KB_S_T:
0080         *sw_mode = dm_sw_64kb_s_t;
0081         break;
0082     case DC_SW_64KB_D:
0083         *sw_mode = dm_sw_64kb_d;
0084         break;
0085     case DC_SW_64KB_D_X:
0086         *sw_mode = dm_sw_64kb_d_x;
0087         break;
0088     case DC_SW_64KB_D_T:
0089         *sw_mode = dm_sw_64kb_d_t;
0090         break;
0091     case DC_SW_64KB_R_X:
0092         *sw_mode = dm_sw_64kb_r_x;
0093         break;
0094     case DC_SW_VAR_S:
0095         *sw_mode = dm_sw_var_s;
0096         break;
0097     case DC_SW_VAR_S_X:
0098         *sw_mode = dm_sw_var_s_x;
0099         break;
0100     case DC_SW_VAR_D:
0101         *sw_mode = dm_sw_var_d;
0102         break;
0103     case DC_SW_VAR_D_X:
0104         *sw_mode = dm_sw_var_d_x;
0105         break;
0106
0107     default:
0108         ASSERT(0); /* Not supported */
0109         break;
0110     }
0111 }
0112
0113 static void dc_timing_to_dml_timing(const struct dc_crtc_timing *timing, struct _vcs_dpi_display_pipe_dest_params_st *dest)
0114 {
0115     dest->hblank_start = timing->h_total - timing->h_front_porch;
0116     dest->hblank_end = dest->hblank_start
0117             - timing->h_addressable
0118             - timing->h_border_left
0119             - timing->h_border_right;
0120     dest->vblank_start = timing->v_total - timing->v_front_porch;
0121     dest->vblank_end = dest->vblank_start
0122             - timing->v_addressable
0123             - timing->v_border_top
0124             - timing->v_border_bottom;
0125     dest->htotal = timing->h_total;
0126     dest->vtotal = timing->v_total;
0127     dest->hactive = timing->h_addressable;
0128     dest->vactive = timing->v_addressable;
0129     dest->interlaced = timing->flags.INTERLACE;
0130     dest->pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
0131     if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
0132         dest->pixel_rate_mhz *= 2;
0133 }
0134
0135 static enum odm_combine_mode get_dml_odm_combine(const struct pipe_ctx *pipe)
0136 {
0137     int odm_split_count = 0;
0138     enum odm_combine_mode combine_mode = dm_odm_combine_mode_disabled;
0139     struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
0140
0141     // Traverse pipe tree to determine odm split count
0142     while (next_pipe) {
0143         odm_split_count++;
0144         next_pipe = next_pipe->next_odm_pipe;
0145     }
0146     pipe = pipe->prev_odm_pipe;
0147     while (pipe) {
0148         odm_split_count++;
0149         pipe = pipe->prev_odm_pipe;
0150     }
0151
0152     // Translate split to DML odm combine factor
0153     switch (odm_split_count) {
0154     case 1:
0155         combine_mode = dm_odm_combine_mode_2to1;
0156         break;
0157     case 3:
0158         combine_mode = dm_odm_combine_mode_4to1;
0159         break;
0160     default:
0161         combine_mode = dm_odm_combine_mode_disabled;
0162     }
0163
0164     return combine_mode;
0165 }
0166
0167 static int get_dml_output_type(enum signal_type dc_signal)
0168 {
0169     int dml_output_type = -1;
0170
0171     switch (dc_signal) {
0172     case SIGNAL_TYPE_DISPLAY_PORT_MST:
0173     case SIGNAL_TYPE_DISPLAY_PORT:
0174         dml_output_type = dm_dp;
0175         break;
0176     case SIGNAL_TYPE_EDP:
0177         dml_output_type = dm_edp;
0178         break;
0179     case SIGNAL_TYPE_HDMI_TYPE_A:
0180     case SIGNAL_TYPE_DVI_SINGLE_LINK:
0181     case SIGNAL_TYPE_DVI_DUAL_LINK:
0182         dml_output_type = dm_hdmi;
0183         break;
0184     default:
0185         break;
0186     }
0187
0188     return dml_output_type;
0189 }
0190
0191 static void populate_color_depth_and_encoding_from_timing(const struct dc_crtc_timing *timing, struct _vcs_dpi_display_output_params_st *dout)
0192 {
0193     int output_bpc = 0;
0194
0195     switch (timing->display_color_depth) {
0196     case COLOR_DEPTH_666:
0197         output_bpc = 6;
0198         break;
0199     case COLOR_DEPTH_888:
0200         output_bpc = 8;
0201         break;
0202     case COLOR_DEPTH_101010:
0203         output_bpc = 10;
0204         break;
0205     case COLOR_DEPTH_121212:
0206         output_bpc = 12;
0207         break;
0208     case COLOR_DEPTH_141414:
0209         output_bpc = 14;
0210         break;
0211     case COLOR_DEPTH_161616:
0212         output_bpc = 16;
0213         break;
0214     case COLOR_DEPTH_999:
0215         output_bpc = 9;
0216         break;
0217     case COLOR_DEPTH_111111:
0218         output_bpc = 11;
0219         break;
0220     default:
0221         output_bpc = 8;
0222         break;
0223     }
0224
0225     switch (timing->pixel_encoding) {
0226     case PIXEL_ENCODING_RGB:
0227     case PIXEL_ENCODING_YCBCR444:
0228         dout->output_format = dm_444;
0229         dout->output_bpp = output_bpc * 3;
0230         break;
0231     case PIXEL_ENCODING_YCBCR420:
0232         dout->output_format = dm_420;
0233         dout->output_bpp = (output_bpc * 3.0) / 2;
0234         break;
0235     case PIXEL_ENCODING_YCBCR422:
0236         if (timing->flags.DSC && !timing->dsc_cfg.ycbcr422_simple)
0237             dout->output_format = dm_n422;
0238         else
0239             dout->output_format = dm_s422;
0240         dout->output_bpp = output_bpc * 2;
0241         break;
0242     default:
0243         dout->output_format = dm_444;
0244         dout->output_bpp = output_bpc * 3;
0245     }
0246 }
0247
0248 static enum source_format_class dc_source_format_to_dml_source_format(enum surface_pixel_format dc_format)
0249 {
0250     enum source_format_class dml_format = dm_444_32;
0251
0252     switch (dc_format) {
0253     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
0254     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
0255         dml_format = dm_420_8;
0256         break;
0257     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
0258     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
0259         dml_format = dm_420_10;
0260         break;
0261     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
0262     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
0263     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
0264         dml_format = dm_444_64;
0265         break;
0266     case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
0267     case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
0268         dml_format = dm_444_16;
0269         break;
0270     case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
0271         dml_format = dm_444_8;
0272         break;
0273     case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
0274         dml_format = dm_rgbe_alpha;
0275         break;
0276     default:
0277         dml_format = dm_444_32;
0278         break;
0279     }
0280
0281     return dml_format;
0282 }
0283
0284 #endif