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0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "display_rq_dlg_helpers.h"
0027 #include "dml_logger.h"
0028 
0029 void print__rq_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_params_st *rq_param)
0030 {
0031     dml_print("DML_RQ_DLG_CALC: ***************************\n");
0032     dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST\n");
0033     dml_print("DML_RQ_DLG_CALC:  <LUMA>\n");
0034     print__data_rq_sizing_params_st(mode_lib, &rq_param->sizing.rq_l);
0035     dml_print("DML_RQ_DLG_CALC:  <CHROMA> ===\n");
0036     print__data_rq_sizing_params_st(mode_lib, &rq_param->sizing.rq_c);
0037 
0038     dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
0039     print__data_rq_dlg_params_st(mode_lib, &rq_param->dlg.rq_l);
0040     dml_print("DML_RQ_DLG_CALC: <CHROMA>\n");
0041     print__data_rq_dlg_params_st(mode_lib, &rq_param->dlg.rq_c);
0042 
0043     dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
0044     print__data_rq_misc_params_st(mode_lib, &rq_param->misc.rq_l);
0045     dml_print("DML_RQ_DLG_CALC: <CHROMA>\n");
0046     print__data_rq_misc_params_st(mode_lib, &rq_param->misc.rq_c);
0047     dml_print("DML_RQ_DLG_CALC: ***************************\n");
0048 }
0049 
0050 void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing)
0051 {
0052     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0053     dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST\n");
0054     dml_print("DML_RQ_DLG_CALC:    chunk_bytes           = %0d\n", rq_sizing->chunk_bytes);
0055     dml_print("DML_RQ_DLG_CALC:    min_chunk_bytes       = %0d\n", rq_sizing->min_chunk_bytes);
0056     dml_print("DML_RQ_DLG_CALC:    meta_chunk_bytes      = %0d\n", rq_sizing->meta_chunk_bytes);
0057     dml_print(
0058             "DML_RQ_DLG_CALC:    min_meta_chunk_bytes  = %0d\n",
0059             rq_sizing->min_meta_chunk_bytes);
0060     dml_print("DML_RQ_DLG_CALC:    mpte_group_bytes      = %0d\n", rq_sizing->mpte_group_bytes);
0061     dml_print("DML_RQ_DLG_CALC:    dpte_group_bytes      = %0d\n", rq_sizing->dpte_group_bytes);
0062     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0063 }
0064 
0065 void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param)
0066 {
0067     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0068     dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST\n");
0069     dml_print(
0070             "DML_RQ_DLG_CALC:    swath_width_ub              = %0d\n",
0071             rq_dlg_param->swath_width_ub);
0072     dml_print(
0073             "DML_RQ_DLG_CALC:    swath_height                = %0d\n",
0074             rq_dlg_param->swath_height);
0075     dml_print(
0076             "DML_RQ_DLG_CALC:    req_per_swath_ub            = %0d\n",
0077             rq_dlg_param->req_per_swath_ub);
0078     dml_print(
0079             "DML_RQ_DLG_CALC:    meta_pte_bytes_per_frame_ub = %0d\n",
0080             rq_dlg_param->meta_pte_bytes_per_frame_ub);
0081     dml_print(
0082             "DML_RQ_DLG_CALC:    dpte_req_per_row_ub         = %0d\n",
0083             rq_dlg_param->dpte_req_per_row_ub);
0084     dml_print(
0085             "DML_RQ_DLG_CALC:    dpte_groups_per_row_ub      = %0d\n",
0086             rq_dlg_param->dpte_groups_per_row_ub);
0087     dml_print(
0088             "DML_RQ_DLG_CALC:    dpte_row_height             = %0d\n",
0089             rq_dlg_param->dpte_row_height);
0090     dml_print(
0091             "DML_RQ_DLG_CALC:    dpte_bytes_per_row_ub       = %0d\n",
0092             rq_dlg_param->dpte_bytes_per_row_ub);
0093     dml_print(
0094             "DML_RQ_DLG_CALC:    meta_chunks_per_row_ub      = %0d\n",
0095             rq_dlg_param->meta_chunks_per_row_ub);
0096     dml_print(
0097             "DML_RQ_DLG_CALC:    meta_req_per_row_ub         = %0d\n",
0098             rq_dlg_param->meta_req_per_row_ub);
0099     dml_print(
0100             "DML_RQ_DLG_CALC:    meta_row_height             = %0d\n",
0101             rq_dlg_param->meta_row_height);
0102     dml_print(
0103             "DML_RQ_DLG_CALC:    meta_bytes_per_row_ub       = %0d\n",
0104             rq_dlg_param->meta_bytes_per_row_ub);
0105     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0106 }
0107 
0108 void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_misc_params_st *rq_misc_param)
0109 {
0110     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0111     dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST\n");
0112     dml_print(
0113             "DML_RQ_DLG_CALC:     full_swath_bytes   = %0d\n",
0114             rq_misc_param->full_swath_bytes);
0115     dml_print(
0116             "DML_RQ_DLG_CALC:     stored_swath_bytes = %0d\n",
0117             rq_misc_param->stored_swath_bytes);
0118     dml_print("DML_RQ_DLG_CALC:     blk256_width       = %0d\n", rq_misc_param->blk256_width);
0119     dml_print("DML_RQ_DLG_CALC:     blk256_height      = %0d\n", rq_misc_param->blk256_height);
0120     dml_print("DML_RQ_DLG_CALC:     req_width          = %0d\n", rq_misc_param->req_width);
0121     dml_print("DML_RQ_DLG_CALC:     req_height         = %0d\n", rq_misc_param->req_height);
0122     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0123 }
0124 
0125 void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_dlg_params_st *rq_dlg_param)
0126 {
0127     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0128     dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n");
0129     dml_print("DML_RQ_DLG_CALC:  <LUMA>\n");
0130     print__data_rq_dlg_params_st(mode_lib, &rq_dlg_param->rq_l);
0131     dml_print("DML_RQ_DLG_CALC:  <CHROMA>\n");
0132     print__data_rq_dlg_params_st(mode_lib, &rq_dlg_param->rq_c);
0133     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0134 }
0135 
0136 void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param)
0137 {
0138     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0139     dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n");
0140     dml_print("DML_RQ_DLG_CALC:    t_mclk_wm_us         = %3.2f\n", dlg_sys_param->t_mclk_wm_us);
0141     dml_print("DML_RQ_DLG_CALC:    t_urg_wm_us          = %3.2f\n", dlg_sys_param->t_urg_wm_us);
0142     dml_print("DML_RQ_DLG_CALC:    t_sr_wm_us           = %3.2f\n", dlg_sys_param->t_sr_wm_us);
0143     dml_print("DML_RQ_DLG_CALC:    t_extra_us           = %3.2f\n", dlg_sys_param->t_extra_us);
0144     dml_print(
0145             "DML_RQ_DLG_CALC:    deepsleep_dcfclk_mhz = %3.2f\n",
0146             dlg_sys_param->deepsleep_dcfclk_mhz);
0147     dml_print(
0148             "DML_RQ_DLG_CALC:    total_flip_bw        = %3.2f\n",
0149             dlg_sys_param->total_flip_bw);
0150     dml_print(
0151             "DML_RQ_DLG_CALC:    total_flip_bytes     = %i\n",
0152             dlg_sys_param->total_flip_bytes);
0153     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0154 }
0155 
0156 void print__data_rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_regs_st *rq_regs)
0157 {
0158     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0159     dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST\n");
0160     dml_print("DML_RQ_DLG_CALC:    chunk_size              = 0x%0x\n", rq_regs->chunk_size);
0161     dml_print("DML_RQ_DLG_CALC:    min_chunk_size          = 0x%0x\n", rq_regs->min_chunk_size);
0162     dml_print("DML_RQ_DLG_CALC:    meta_chunk_size         = 0x%0x\n", rq_regs->meta_chunk_size);
0163     dml_print(
0164             "DML_RQ_DLG_CALC:    min_meta_chunk_size     = 0x%0x\n",
0165             rq_regs->min_meta_chunk_size);
0166     dml_print("DML_RQ_DLG_CALC:    dpte_group_size         = 0x%0x\n", rq_regs->dpte_group_size);
0167     dml_print("DML_RQ_DLG_CALC:    mpte_group_size         = 0x%0x\n", rq_regs->mpte_group_size);
0168     dml_print("DML_RQ_DLG_CALC:    swath_height            = 0x%0x\n", rq_regs->swath_height);
0169     dml_print(
0170             "DML_RQ_DLG_CALC:    pte_row_height_linear   = 0x%0x\n",
0171             rq_regs->pte_row_height_linear);
0172     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0173 }
0174 
0175 void print__rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_regs_st *rq_regs)
0176 {
0177     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0178     dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST\n");
0179     dml_print("DML_RQ_DLG_CALC:  <LUMA>\n");
0180     print__data_rq_regs_st(mode_lib, &rq_regs->rq_regs_l);
0181     dml_print("DML_RQ_DLG_CALC:  <CHROMA>\n");
0182     print__data_rq_regs_st(mode_lib, &rq_regs->rq_regs_c);
0183     dml_print("DML_RQ_DLG_CALC:    drq_expansion_mode  = 0x%0x\n", rq_regs->drq_expansion_mode);
0184     dml_print("DML_RQ_DLG_CALC:    prq_expansion_mode  = 0x%0x\n", rq_regs->prq_expansion_mode);
0185     dml_print("DML_RQ_DLG_CALC:    mrq_expansion_mode  = 0x%0x\n", rq_regs->mrq_expansion_mode);
0186     dml_print("DML_RQ_DLG_CALC:    crq_expansion_mode  = 0x%0x\n", rq_regs->crq_expansion_mode);
0187     dml_print("DML_RQ_DLG_CALC:    plane1_base_address = 0x%0x\n", rq_regs->plane1_base_address);
0188     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0189 }
0190 
0191 void print__dlg_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_regs_st *dlg_regs)
0192 {
0193     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0194     dml_print("DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST\n");
0195     dml_print(
0196             "DML_RQ_DLG_CALC:    refcyc_h_blank_end              = 0x%0x\n",
0197             dlg_regs->refcyc_h_blank_end);
0198     dml_print(
0199             "DML_RQ_DLG_CALC:    dlg_vblank_end                  = 0x%0x\n",
0200             dlg_regs->dlg_vblank_end);
0201     dml_print(
0202             "DML_RQ_DLG_CALC:    min_dst_y_next_start            = 0x%0x\n",
0203             dlg_regs->min_dst_y_next_start);
0204     dml_print(
0205             "DML_RQ_DLG_CALC:    refcyc_per_htotal               = 0x%0x\n",
0206             dlg_regs->refcyc_per_htotal);
0207     dml_print(
0208             "DML_RQ_DLG_CALC:    refcyc_x_after_scaler           = 0x%0x\n",
0209             dlg_regs->refcyc_x_after_scaler);
0210     dml_print(
0211             "DML_RQ_DLG_CALC:    dst_y_after_scaler              = 0x%0x\n",
0212             dlg_regs->dst_y_after_scaler);
0213     dml_print(
0214             "DML_RQ_DLG_CALC:    dst_y_prefetch                  = 0x%0x\n",
0215             dlg_regs->dst_y_prefetch);
0216     dml_print(
0217             "DML_RQ_DLG_CALC:    dst_y_per_vm_vblank             = 0x%0x\n",
0218             dlg_regs->dst_y_per_vm_vblank);
0219     dml_print(
0220             "DML_RQ_DLG_CALC:    dst_y_per_row_vblank            = 0x%0x\n",
0221             dlg_regs->dst_y_per_row_vblank);
0222     dml_print(
0223             "DML_RQ_DLG_CALC:    dst_y_per_vm_flip               = 0x%0x\n",
0224             dlg_regs->dst_y_per_vm_flip);
0225     dml_print(
0226             "DML_RQ_DLG_CALC:    dst_y_per_row_flip              = 0x%0x\n",
0227             dlg_regs->dst_y_per_row_flip);
0228     dml_print(
0229             "DML_RQ_DLG_CALC:    ref_freq_to_pix_freq            = 0x%0x\n",
0230             dlg_regs->ref_freq_to_pix_freq);
0231     dml_print(
0232             "DML_RQ_DLG_CALC:    vratio_prefetch                 = 0x%0x\n",
0233             dlg_regs->vratio_prefetch);
0234     dml_print(
0235             "DML_RQ_DLG_CALC:    vratio_prefetch_c               = 0x%0x\n",
0236             dlg_regs->vratio_prefetch_c);
0237     dml_print(
0238             "DML_RQ_DLG_CALC:    refcyc_per_pte_group_vblank_l   = 0x%0x\n",
0239             dlg_regs->refcyc_per_pte_group_vblank_l);
0240     dml_print(
0241             "DML_RQ_DLG_CALC:    refcyc_per_pte_group_vblank_c   = 0x%0x\n",
0242             dlg_regs->refcyc_per_pte_group_vblank_c);
0243     dml_print(
0244             "DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_vblank_l  = 0x%0x\n",
0245             dlg_regs->refcyc_per_meta_chunk_vblank_l);
0246     dml_print(
0247             "DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_vblank_c  = 0x%0x\n",
0248             dlg_regs->refcyc_per_meta_chunk_vblank_c);
0249     dml_print(
0250             "DML_RQ_DLG_CALC:    refcyc_per_pte_group_flip_l     = 0x%0x\n",
0251             dlg_regs->refcyc_per_pte_group_flip_l);
0252     dml_print(
0253             "DML_RQ_DLG_CALC:    refcyc_per_pte_group_flip_c     = 0x%0x\n",
0254             dlg_regs->refcyc_per_pte_group_flip_c);
0255     dml_print(
0256             "DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_flip_l    = 0x%0x\n",
0257             dlg_regs->refcyc_per_meta_chunk_flip_l);
0258     dml_print(
0259             "DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_flip_c    = 0x%0x\n",
0260             dlg_regs->refcyc_per_meta_chunk_flip_c);
0261     dml_print(
0262             "DML_RQ_DLG_CALC:    dst_y_per_pte_row_nom_l         = 0x%0x\n",
0263             dlg_regs->dst_y_per_pte_row_nom_l);
0264     dml_print(
0265             "DML_RQ_DLG_CALC:    dst_y_per_pte_row_nom_c         = 0x%0x\n",
0266             dlg_regs->dst_y_per_pte_row_nom_c);
0267     dml_print(
0268             "DML_RQ_DLG_CALC:    refcyc_per_pte_group_nom_l      = 0x%0x\n",
0269             dlg_regs->refcyc_per_pte_group_nom_l);
0270     dml_print(
0271             "DML_RQ_DLG_CALC:    refcyc_per_pte_group_nom_c      = 0x%0x\n",
0272             dlg_regs->refcyc_per_pte_group_nom_c);
0273     dml_print(
0274             "DML_RQ_DLG_CALC:    dst_y_per_meta_row_nom_l        = 0x%0x\n",
0275             dlg_regs->dst_y_per_meta_row_nom_l);
0276     dml_print(
0277             "DML_RQ_DLG_CALC:    dst_y_per_meta_row_nom_c        = 0x%0x\n",
0278             dlg_regs->dst_y_per_meta_row_nom_c);
0279     dml_print(
0280             "DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_nom_l     = 0x%0x\n",
0281             dlg_regs->refcyc_per_meta_chunk_nom_l);
0282     dml_print(
0283             "DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_nom_c     = 0x%0x\n",
0284             dlg_regs->refcyc_per_meta_chunk_nom_c);
0285     dml_print(
0286             "DML_RQ_DLG_CALC:    refcyc_per_line_delivery_pre_l  = 0x%0x\n",
0287             dlg_regs->refcyc_per_line_delivery_pre_l);
0288     dml_print(
0289             "DML_RQ_DLG_CALC:    refcyc_per_line_delivery_pre_c  = 0x%0x\n",
0290             dlg_regs->refcyc_per_line_delivery_pre_c);
0291     dml_print(
0292             "DML_RQ_DLG_CALC:    refcyc_per_line_delivery_l      = 0x%0x\n",
0293             dlg_regs->refcyc_per_line_delivery_l);
0294     dml_print(
0295             "DML_RQ_DLG_CALC:    refcyc_per_line_delivery_c      = 0x%0x\n",
0296             dlg_regs->refcyc_per_line_delivery_c);
0297     dml_print(
0298             "DML_RQ_DLG_CALC:    chunk_hdl_adjust_cur0           = 0x%0x\n",
0299             dlg_regs->chunk_hdl_adjust_cur0);
0300     dml_print(
0301             "DML_RQ_DLG_CALC:    dst_y_offset_cur1               = 0x%0x\n",
0302             dlg_regs->dst_y_offset_cur1);
0303     dml_print(
0304             "DML_RQ_DLG_CALC:    chunk_hdl_adjust_cur1           = 0x%0x\n",
0305             dlg_regs->chunk_hdl_adjust_cur1);
0306     dml_print(
0307             "DML_RQ_DLG_CALC:    vready_after_vcount0            = 0x%0x\n",
0308             dlg_regs->vready_after_vcount0);
0309     dml_print(
0310             "DML_RQ_DLG_CALC:    dst_y_delta_drq_limit           = 0x%0x\n",
0311             dlg_regs->dst_y_delta_drq_limit);
0312     dml_print(
0313             "DML_RQ_DLG_CALC:    xfc_reg_transfer_delay          = 0x%0x\n",
0314             dlg_regs->xfc_reg_transfer_delay);
0315     dml_print(
0316             "DML_RQ_DLG_CALC:    xfc_reg_precharge_delay         = 0x%0x\n",
0317             dlg_regs->xfc_reg_precharge_delay);
0318     dml_print(
0319             "DML_RQ_DLG_CALC:    xfc_reg_remote_surface_flip_latency = 0x%0x\n",
0320             dlg_regs->xfc_reg_remote_surface_flip_latency);
0321     dml_print(
0322             "DML_RQ_DLG_CALC:    refcyc_per_vm_dmdata            = 0x%0x\n",
0323             dlg_regs->refcyc_per_vm_dmdata);
0324 
0325     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0326 }
0327 
0328 void print__ttu_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_ttu_regs_st *ttu_regs)
0329 {
0330     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0331     dml_print("DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST\n");
0332     dml_print(
0333             "DML_RQ_DLG_CALC:    qos_level_low_wm                  = 0x%0x\n",
0334             ttu_regs->qos_level_low_wm);
0335     dml_print(
0336             "DML_RQ_DLG_CALC:    qos_level_high_wm                 = 0x%0x\n",
0337             ttu_regs->qos_level_high_wm);
0338     dml_print(
0339             "DML_RQ_DLG_CALC:    min_ttu_vblank                    = 0x%0x\n",
0340             ttu_regs->min_ttu_vblank);
0341     dml_print(
0342             "DML_RQ_DLG_CALC:    qos_level_flip                    = 0x%0x\n",
0343             ttu_regs->qos_level_flip);
0344     dml_print(
0345             "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_l     = 0x%0x\n",
0346             ttu_regs->refcyc_per_req_delivery_pre_l);
0347     dml_print(
0348             "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_l         = 0x%0x\n",
0349             ttu_regs->refcyc_per_req_delivery_l);
0350     dml_print(
0351             "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_c     = 0x%0x\n",
0352             ttu_regs->refcyc_per_req_delivery_pre_c);
0353     dml_print(
0354             "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_c         = 0x%0x\n",
0355             ttu_regs->refcyc_per_req_delivery_c);
0356     dml_print(
0357             "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_cur0      = 0x%0x\n",
0358             ttu_regs->refcyc_per_req_delivery_cur0);
0359     dml_print(
0360             "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_cur0  = 0x%0x\n",
0361             ttu_regs->refcyc_per_req_delivery_pre_cur0);
0362     dml_print(
0363             "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_cur1      = 0x%0x\n",
0364             ttu_regs->refcyc_per_req_delivery_cur1);
0365     dml_print(
0366             "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_cur1  = 0x%0x\n",
0367             ttu_regs->refcyc_per_req_delivery_pre_cur1);
0368     dml_print(
0369             "DML_RQ_DLG_CALC:    qos_level_fixed_l                 = 0x%0x\n",
0370             ttu_regs->qos_level_fixed_l);
0371     dml_print(
0372             "DML_RQ_DLG_CALC:    qos_ramp_disable_l                = 0x%0x\n",
0373             ttu_regs->qos_ramp_disable_l);
0374     dml_print(
0375             "DML_RQ_DLG_CALC:    qos_level_fixed_c                 = 0x%0x\n",
0376             ttu_regs->qos_level_fixed_c);
0377     dml_print(
0378             "DML_RQ_DLG_CALC:    qos_ramp_disable_c                = 0x%0x\n",
0379             ttu_regs->qos_ramp_disable_c);
0380     dml_print(
0381             "DML_RQ_DLG_CALC:    qos_level_fixed_cur0              = 0x%0x\n",
0382             ttu_regs->qos_level_fixed_cur0);
0383     dml_print(
0384             "DML_RQ_DLG_CALC:    qos_ramp_disable_cur0             = 0x%0x\n",
0385             ttu_regs->qos_ramp_disable_cur0);
0386     dml_print(
0387             "DML_RQ_DLG_CALC:    qos_level_fixed_cur1              = 0x%0x\n",
0388             ttu_regs->qos_level_fixed_cur1);
0389     dml_print(
0390             "DML_RQ_DLG_CALC:    qos_ramp_disable_cur1             = 0x%0x\n",
0391             ttu_regs->qos_ramp_disable_cur1);
0392     dml_print("DML_RQ_DLG_CALC: =====================================\n");
0393 }
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