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0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 
0027 #ifndef __DML2_DISPLAY_MODE_VBA_H__
0028 #define __DML2_DISPLAY_MODE_VBA_H__
0029 
0030 struct display_mode_lib;
0031 
0032 void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
0033 
0034 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
0035 
0036 dml_get_attr_decl(clk_dcf_deepsleep);
0037 dml_get_attr_decl(wm_urgent);
0038 dml_get_attr_decl(wm_memory_trip);
0039 dml_get_attr_decl(wm_writeback_urgent);
0040 dml_get_attr_decl(wm_stutter_exit);
0041 dml_get_attr_decl(wm_stutter_enter_exit);
0042 dml_get_attr_decl(wm_z8_stutter_exit);
0043 dml_get_attr_decl(wm_z8_stutter_enter_exit);
0044 dml_get_attr_decl(stutter_efficiency_z8);
0045 dml_get_attr_decl(stutter_num_bursts_z8);
0046 dml_get_attr_decl(wm_dram_clock_change);
0047 dml_get_attr_decl(wm_writeback_dram_clock_change);
0048 dml_get_attr_decl(stutter_efficiency_no_vblank);
0049 dml_get_attr_decl(stutter_efficiency);
0050 dml_get_attr_decl(stutter_period);
0051 dml_get_attr_decl(urgent_latency);
0052 dml_get_attr_decl(urgent_extra_latency);
0053 dml_get_attr_decl(nonurgent_latency);
0054 dml_get_attr_decl(dram_clock_change_latency);
0055 dml_get_attr_decl(dispclk_calculated);
0056 dml_get_attr_decl(total_data_read_bw);
0057 dml_get_attr_decl(return_bw);
0058 dml_get_attr_decl(tcalc);
0059 dml_get_attr_decl(fraction_of_urgent_bandwidth);
0060 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
0061 dml_get_attr_decl(cstate_max_cap_mode);
0062 dml_get_attr_decl(comp_buffer_size_kbytes);
0063 dml_get_attr_decl(pixel_chunk_size_in_kbyte);
0064 dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte);
0065 dml_get_attr_decl(meta_chunk_size_in_kbyte);
0066 dml_get_attr_decl(min_pixel_chunk_size_in_byte);
0067 dml_get_attr_decl(min_meta_chunk_size_in_byte);
0068 dml_get_attr_decl(fclk_watermark);
0069 dml_get_attr_decl(usr_retraining_watermark);
0070 dml_get_attr_decl(comp_buffer_reserved_space_kbytes);
0071 dml_get_attr_decl(comp_buffer_reserved_space_64bytes);
0072 dml_get_attr_decl(comp_buffer_reserved_space_zs);
0073 dml_get_attr_decl(unbounded_request_enabled);
0074 
0075 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
0076 
0077 dml_get_pipe_attr_decl(dsc_delay);
0078 dml_get_pipe_attr_decl(dppclk_calculated);
0079 dml_get_pipe_attr_decl(dscclk_calculated);
0080 dml_get_pipe_attr_decl(min_ttu_vblank);
0081 dml_get_pipe_attr_decl(min_ttu_vblank_in_us);
0082 dml_get_pipe_attr_decl(vratio_prefetch_l);
0083 dml_get_pipe_attr_decl(vratio_prefetch_c);
0084 dml_get_pipe_attr_decl(dst_x_after_scaler);
0085 dml_get_pipe_attr_decl(dst_y_after_scaler);
0086 dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
0087 dml_get_pipe_attr_decl(dst_y_per_row_vblank);
0088 dml_get_pipe_attr_decl(dst_y_prefetch);
0089 dml_get_pipe_attr_decl(dst_y_per_vm_flip);
0090 dml_get_pipe_attr_decl(dst_y_per_row_flip);
0091 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l);
0092 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c);
0093 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l);
0094 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c);
0095 dml_get_pipe_attr_decl(dpte_row_height_linear_c);
0096 dml_get_pipe_attr_decl(swath_height_l);
0097 dml_get_pipe_attr_decl(swath_height_c);
0098 dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes);
0099 dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes);
0100 dml_get_pipe_attr_decl(dpte_group_size_in_bytes);
0101 dml_get_pipe_attr_decl(vm_group_size_in_bytes);
0102 dml_get_pipe_attr_decl(det_buffer_size_kbytes);
0103 dml_get_pipe_attr_decl(dpte_row_height_linear_l);
0104 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us);
0105 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us);
0106 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us);
0107 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us);
0108 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us);
0109 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us);
0110 dml_get_pipe_attr_decl(pte_buffer_mode);
0111 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
0112 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
0113 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
0114 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip);
0115 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank_in_us);
0116 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip_in_us);
0117 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank_in_us);
0118 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip_in_us);
0119 dml_get_pipe_attr_decl(refcyc_per_vm_dmdata_in_us);
0120 dml_get_pipe_attr_decl(dmdata_dl_delta_in_us);
0121 dml_get_pipe_attr_decl(refcyc_per_line_delivery_l_in_us);
0122 dml_get_pipe_attr_decl(refcyc_per_line_delivery_c_in_us);
0123 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_l_in_us);
0124 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_c_in_us);
0125 dml_get_pipe_attr_decl(refcyc_per_req_delivery_l_in_us);
0126 dml_get_pipe_attr_decl(refcyc_per_req_delivery_c_in_us);
0127 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_l_in_us);
0128 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_c_in_us);
0129 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_in_us);
0130 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_pre_in_us);
0131 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_l_in_us);
0132 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_c_in_us);
0133 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_l_in_us);
0134 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us);
0135 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us);
0136 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us);
0137 
0138 dml_get_pipe_attr_decl(vstartup);
0139 dml_get_pipe_attr_decl(vupdate_offset);
0140 dml_get_pipe_attr_decl(vupdate_width);
0141 dml_get_pipe_attr_decl(vready_offset);
0142 dml_get_pipe_attr_decl(vready_at_or_after_vsync);
0143 dml_get_pipe_attr_decl(min_dst_y_next_start);
0144 dml_get_pipe_attr_decl(vstartup_calculated);
0145 dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall);
0146 
0147 double get_total_immediate_flip_bytes(
0148         struct display_mode_lib *mode_lib,
0149         const display_e2e_pipe_params_st *pipes,
0150         unsigned int num_pipes);
0151 double get_total_immediate_flip_bw(
0152         struct display_mode_lib *mode_lib,
0153         const display_e2e_pipe_params_st *pipes,
0154         unsigned int num_pipes);
0155 double get_total_prefetch_bw(
0156         struct display_mode_lib *mode_lib,
0157         const display_e2e_pipe_params_st *pipes,
0158         unsigned int num_pipes);
0159 unsigned int dml_get_voltage_level(
0160         struct display_mode_lib *mode_lib,
0161         const display_e2e_pipe_params_st *pipes,
0162         unsigned int num_pipes);
0163 
0164 unsigned int get_total_surface_size_in_mall_bytes(
0165         struct display_mode_lib *mode_lib,
0166         const display_e2e_pipe_params_st *pipes,
0167         unsigned int num_pipes);
0168 
0169 bool get_is_phantom_pipe(struct display_mode_lib *mode_lib,
0170         const display_e2e_pipe_params_st *pipes,
0171         unsigned int num_pipes,
0172         unsigned int pipe_idx);
0173 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
0174 
0175 void Calculate256BBlockSizes(
0176         enum source_format_class SourcePixelFormat,
0177         enum dm_swizzle_mode SurfaceTiling,
0178         unsigned int BytePerPixelY,
0179         unsigned int BytePerPixelC,
0180         unsigned int *BlockHeight256BytesY,
0181         unsigned int *BlockHeight256BytesC,
0182         unsigned int *BlockWidth256BytesY,
0183         unsigned int *BlockWidth256BytesC);
0184 
0185 struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation {
0186     unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX];
0187     double dummy_single_array[2][DC__NUM_DPP__MAX];
0188     unsigned int dummy_long_array[2][DC__NUM_DPP__MAX];
0189     double dummy_double_array[2][DC__NUM_DPP__MAX];
0190     bool dummy_boolean_array[DC__NUM_DPP__MAX];
0191     bool dummy_boolean;
0192     bool dummy_boolean2;
0193     enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX];
0194     DmlPipe SurfaceParameters[DC__NUM_DPP__MAX];
0195     bool dummy_boolean_array2[2][DC__NUM_DPP__MAX];
0196     unsigned int ReorderBytes;
0197     unsigned int VMDataOnlyReturnBW;
0198     double HostVMInefficiencyFactor;
0199     DmlPipe myPipe;
0200     SOCParametersList mmSOCParameters;
0201     double dummy_unit_vector[DC__NUM_DPP__MAX];
0202     double dummy_single[2];
0203     enum clock_change_support dummy_dramchange_support;
0204     enum dm_fclock_change_support dummy_fclkchange_support;
0205     bool dummy_USRRetrainingSupport;
0206 };
0207 
0208 struct dml32_ModeSupportAndSystemConfigurationFull {
0209     unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX];
0210     double dummy_double_array[2][DC__NUM_DPP__MAX];
0211     DmlPipe SurfParameters[DC__NUM_DPP__MAX];
0212     double dummy_single[5];
0213     double dummy_single2[5];
0214     SOCParametersList mSOCParameters;
0215     unsigned int MaximumSwathWidthSupportLuma;
0216     unsigned int MaximumSwathWidthSupportChroma;
0217     double DSTYAfterScaler[DC__NUM_DPP__MAX];
0218     double DSTXAfterScaler[DC__NUM_DPP__MAX];
0219     double MaxTotalVActiveRDBandwidth;
0220     bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
0221     enum odm_combine_mode dummy_odm_mode[DC__NUM_DPP__MAX];
0222     DmlPipe myPipe;
0223     unsigned int dummy_integer[4];
0224     unsigned int TotalNumberOfActiveOTG;
0225     unsigned int TotalNumberOfActiveHDMIFRL;
0226     unsigned int TotalNumberOfActiveDP2p0;
0227     unsigned int TotalNumberOfActiveDP2p0Outputs;
0228     unsigned int TotalDSCUnitsRequired;
0229     unsigned int ReorderingBytes;
0230     unsigned int TotalSlots;
0231     unsigned int NumberOfDPPDSC;
0232     unsigned int NumberOfDPPNoDSC;
0233     unsigned int NextPrefetchModeState;
0234     bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
0235     bool MPCCombineMethodAsPossible;
0236     bool FullFrameMALLPStateMethod;
0237     bool SubViewportMALLPStateMethod;
0238     bool PhantomPipeMALLPStateMethod;
0239     bool NoChroma;
0240     bool TotalAvailablePipesSupportNoDSC;
0241     bool TotalAvailablePipesSupportDSC;
0242     enum odm_combine_mode ODMModeNoDSC;
0243     enum odm_combine_mode ODMModeDSC;
0244     double RequiredDISPCLKPerSurfaceNoDSC;
0245     double RequiredDISPCLKPerSurfaceDSC;
0246     double BWOfNonCombinedSurfaceOfMaximumBandwidth;
0247     double VMDataOnlyReturnBWPerState;
0248     double HostVMInefficiencyFactor;
0249     bool dummy_boolean[2];
0250 };
0251 
0252 struct dummy_vars {
0253     struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
0254     DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation;
0255     struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull;
0256 };
0257 
0258 struct vba_vars_st {
0259     ip_params_st ip;
0260     soc_bounding_box_st soc;
0261 
0262     int maxMpcComb;
0263     bool UseMaximumVStartup;
0264 
0265     double WritebackDISPCLK;
0266     double DPPCLKUsingSingleDPPLuma;
0267     double DPPCLKUsingSingleDPPChroma;
0268     double DISPCLKWithRamping;
0269     double DISPCLKWithoutRamping;
0270     double GlobalDPPCLK;
0271     double DISPCLKWithRampingRoundedToDFSGranularity;
0272     double DISPCLKWithoutRampingRoundedToDFSGranularity;
0273     double MaxDispclkRoundedToDFSGranularity;
0274     bool DCCEnabledAnyPlane;
0275     double ReturnBandwidthToDCN;
0276     unsigned int TotalActiveDPP;
0277     unsigned int TotalDCCActiveDPP;
0278     double UrgentRoundTripAndOutOfOrderLatency;
0279     double StutterPeriod;
0280     double FrameTimeForMinFullDETBufferingTime;
0281     double AverageReadBandwidth;
0282     double TotalRowReadBandwidth;
0283     double PartOfBurstThatFitsInROB;
0284     double StutterBurstTime;
0285     unsigned int NextPrefetchMode;
0286     double NextMaxVStartup;
0287     double VBlankTime;
0288     double SmallestVBlank;
0289     enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only
0290     double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
0291     double EffectiveDETPlusLBLinesLuma;
0292     double EffectiveDETPlusLBLinesChroma;
0293     double UrgentLatencySupportUsLuma;
0294     double UrgentLatencySupportUsChroma;
0295     unsigned int DSCFormatFactor;
0296 
0297     bool DummyPStateCheck;
0298     bool DRAMClockChangeSupportsVActive;
0299     bool PrefetchModeSupported;
0300     bool PrefetchAndImmediateFlipSupported;
0301     enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
0302     double XFCRemoteSurfaceFlipDelay;
0303     double TInitXFill;
0304     double TslvChk;
0305     double SrcActiveDrainRate;
0306     bool ImmediateFlipSupported;
0307     enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only
0308 
0309     bool PrefetchERROR;
0310 
0311     unsigned int VStartupLines;
0312     unsigned int ActiveDPPs;
0313     unsigned int LBLatencyHidingSourceLinesY;
0314     unsigned int LBLatencyHidingSourceLinesC;
0315     double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
0316     double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only
0317     double MinActiveDRAMClockChangeMargin;
0318     double InitFillLevel;
0319     double FinalFillMargin;
0320     double FinalFillLevel;
0321     double RemainingFillLevel;
0322     double TFinalxFill;
0323 
0324     //
0325     // SOC Bounding Box Parameters
0326     //
0327     double SRExitTime;
0328     double SREnterPlusExitTime;
0329     double UrgentLatencyPixelDataOnly;
0330     double UrgentLatencyPixelMixedWithVMData;
0331     double UrgentLatencyVMDataOnly;
0332     double UrgentLatency; // max of the above three
0333     double USRRetrainingLatency;
0334     double SMNLatency;
0335     double FCLKChangeLatency;
0336     unsigned int MALLAllocatedForDCNFinal;
0337     double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation;
0338     double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE;
0339     double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE;
0340     double WritebackLatency;
0341     double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
0342     double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
0343     double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support
0344     double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support
0345     double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support
0346     double NumberOfChannels;
0347     double DRAMChannelWidth;
0348     double FabricDatapathToDCNDataReturn;
0349     double ReturnBusWidth;
0350     double Downspreading;
0351     double DISPCLKDPPCLKDSCCLKDownSpreading;
0352     double DISPCLKDPPCLKVCOSpeed;
0353     double RoundTripPingLatencyCycles;
0354     double UrgentOutOfOrderReturnPerChannel;
0355     double UrgentOutOfOrderReturnPerChannelPixelDataOnly;
0356     double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData;
0357     double UrgentOutOfOrderReturnPerChannelVMDataOnly;
0358     unsigned int VMMPageSize;
0359     double DRAMClockChangeLatency;
0360     double XFCBusTransportTime;
0361     bool UseUrgentBurstBandwidth;
0362     double XFCXBUFLatencyTolerance;
0363 
0364     //
0365     // IP Parameters
0366     //
0367     unsigned int ROBBufferSizeInKByte;
0368     unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX];
0369     double DETBufferSizeInTime;
0370     unsigned int DPPOutputBufferPixels;
0371     unsigned int OPPOutputBufferLines;
0372     unsigned int PixelChunkSizeInKByte;
0373     double ReturnBW;
0374     bool GPUVMEnable;
0375     bool HostVMEnable;
0376     unsigned int GPUVMMaxPageTableLevels;
0377     unsigned int HostVMMaxPageTableLevels;
0378     unsigned int HostVMCachedPageTableLevels;
0379     unsigned int OverrideGPUVMPageTableLevels;
0380     unsigned int OverrideHostVMPageTableLevels;
0381     unsigned int MetaChunkSize;
0382     unsigned int MinMetaChunkSizeBytes;
0383     unsigned int WritebackChunkSize;
0384     bool ODMCapability;
0385     unsigned int NumberOfDSC;
0386     unsigned int LineBufferSize;
0387     unsigned int MaxLineBufferLines;
0388     unsigned int WritebackInterfaceLumaBufferSize;
0389     unsigned int WritebackInterfaceChromaBufferSize;
0390     unsigned int WritebackChromaLineBufferWidth;
0391     enum writeback_config WritebackConfiguration;
0392     double MaxDCHUBToPSCLThroughput;
0393     double MaxPSCLToLBThroughput;
0394     unsigned int PTEBufferSizeInRequestsLuma;
0395     unsigned int PTEBufferSizeInRequestsChroma;
0396     double DISPCLKRampingMargin;
0397     unsigned int MaxInterDCNTileRepeaters;
0398     bool XFCSupported;
0399     double XFCSlvChunkSize;
0400     double XFCFillBWOverhead;
0401     double XFCFillConstant;
0402     double XFCTSlvVupdateOffset;
0403     double XFCTSlvVupdateWidth;
0404     double XFCTSlvVreadyOffset;
0405     double DPPCLKDelaySubtotal;
0406     double DPPCLKDelaySCL;
0407     double DPPCLKDelaySCLLBOnly;
0408     double DPPCLKDelayCNVCFormater;
0409     double DPPCLKDelayCNVCCursor;
0410     double DISPCLKDelaySubtotal;
0411     bool ProgressiveToInterlaceUnitInOPP;
0412     unsigned int CompressedBufferSegmentSizeInkByteFinal;
0413     unsigned int CompbufReservedSpace64B;
0414     unsigned int CompbufReservedSpaceZs;
0415     unsigned int LineBufferSizeFinal;
0416     unsigned int MaximumPixelsPerLinePerDSCUnit;
0417     unsigned int AlphaPixelChunkSizeInKByte;
0418     double MinPixelChunkSizeBytes;
0419     unsigned int DCCMetaBufferSizeBytes;
0420     // Pipe/Plane Parameters
0421     int VoltageLevel;
0422     double FabricClock;
0423     double DRAMSpeed;
0424     double DISPCLK;
0425     double SOCCLK;
0426     double DCFCLK;
0427     unsigned int MaxTotalDETInKByte;
0428     unsigned int MinCompressedBufferSizeInKByte;
0429     unsigned int NumberOfActiveSurfaces;
0430     bool ViewportStationary[DC__NUM_DPP__MAX];
0431     unsigned int RefreshRate[DC__NUM_DPP__MAX];
0432     double       OutputBPP[DC__NUM_DPP__MAX];
0433     unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
0434     bool SynchronizeTimingsFinal;
0435     bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
0436     bool ForceOneRowForFrame[DC__NUM_DPP__MAX];
0437     unsigned int ViewportXStartY[DC__NUM_DPP__MAX];
0438     unsigned int ViewportXStartC[DC__NUM_DPP__MAX];
0439     enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX];
0440     bool DRRDisplay[DC__NUM_DPP__MAX];
0441     bool PteBufferMode[DC__NUM_DPP__MAX];
0442     enum dm_output_type OutputType[DC__NUM_DPP__MAX];
0443     enum dm_output_rate OutputRate[DC__NUM_DPP__MAX];
0444 
0445     unsigned int NumberOfActivePlanes;
0446     unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
0447     unsigned int ViewportWidth[DC__NUM_DPP__MAX];
0448     unsigned int ViewportHeight[DC__NUM_DPP__MAX];
0449     unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
0450     unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
0451     unsigned int PitchY[DC__NUM_DPP__MAX];
0452     unsigned int PitchC[DC__NUM_DPP__MAX];
0453     double HRatio[DC__NUM_DPP__MAX];
0454     double VRatio[DC__NUM_DPP__MAX];
0455     unsigned int htaps[DC__NUM_DPP__MAX];
0456     unsigned int vtaps[DC__NUM_DPP__MAX];
0457     unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
0458     unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
0459     unsigned int HTotal[DC__NUM_DPP__MAX];
0460     unsigned int VTotal[DC__NUM_DPP__MAX];
0461     unsigned int VTotal_Max[DC__NUM_DPP__MAX];
0462     unsigned int VTotal_Min[DC__NUM_DPP__MAX];
0463     int DPPPerPlane[DC__NUM_DPP__MAX];
0464     double PixelClock[DC__NUM_DPP__MAX];
0465     double PixelClockBackEnd[DC__NUM_DPP__MAX];
0466     bool DCCEnable[DC__NUM_DPP__MAX];
0467     bool FECEnable[DC__NUM_DPP__MAX];
0468     unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
0469     unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
0470     enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
0471     enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
0472     bool WritebackEnable[DC__NUM_DPP__MAX];
0473     unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX];
0474     double WritebackDestinationWidth[DC__NUM_DPP__MAX];
0475     double WritebackDestinationHeight[DC__NUM_DPP__MAX];
0476     double WritebackSourceHeight[DC__NUM_DPP__MAX];
0477     enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
0478     unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
0479     unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
0480     unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
0481     unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
0482     double WritebackHRatio[DC__NUM_DPP__MAX];
0483     double WritebackVRatio[DC__NUM_DPP__MAX];
0484     unsigned int HActive[DC__NUM_DPP__MAX];
0485     unsigned int VActive[DC__NUM_DPP__MAX];
0486     bool Interlace[DC__NUM_DPP__MAX];
0487     enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
0488     unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
0489     bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
0490     int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
0491     unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
0492     double DCCRate[DC__NUM_DPP__MAX];
0493     double AverageDCCCompressionRate;
0494     enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX];
0495     double OutputBpp[DC__NUM_DPP__MAX];
0496     bool DSCEnabled[DC__NUM_DPP__MAX];
0497     unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
0498     enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
0499     enum output_encoder_class Output[DC__NUM_DPP__MAX];
0500     bool skip_dio_check[DC__NUM_DPP__MAX];
0501     unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
0502     bool SynchronizedVBlank;
0503     unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
0504     unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
0505     unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
0506     bool XFCEnabled[DC__NUM_DPP__MAX];
0507     bool ScalerEnabled[DC__NUM_DPP__MAX];
0508     unsigned int VBlankNom[DC__NUM_DPP__MAX];
0509     bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment;
0510 
0511     // Intermediates/Informational
0512     bool ImmediateFlipSupport;
0513     unsigned int DETBufferSizeY[DC__NUM_DPP__MAX];
0514     unsigned int DETBufferSizeC[DC__NUM_DPP__MAX];
0515     unsigned int SwathHeightY[DC__NUM_DPP__MAX];
0516     unsigned int SwathHeightC[DC__NUM_DPP__MAX];
0517     unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
0518     double LastPixelOfLineExtraWatermark;
0519     double TotalDataReadBandwidth;
0520     unsigned int TotalActiveWriteback;
0521     unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
0522     unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
0523     double BandwidthAvailableForImmediateFlip;
0524     unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
0525     unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
0526     unsigned int MinPrefetchMode;
0527     unsigned int MaxPrefetchMode;
0528     bool AnyLinesForVMOrRowTooLarge;
0529     double MaxVStartup;
0530     bool IgnoreViewportPositioning;
0531     bool ErrorResult[DC__NUM_DPP__MAX];
0532     //
0533     // Calculated dml_ml->vba.Outputs
0534     //
0535     double DCFCLKDeepSleep;
0536     double UrgentWatermark;
0537     double UrgentExtraLatency;
0538     double WritebackUrgentWatermark;
0539     double StutterExitWatermark;
0540     double StutterEnterPlusExitWatermark;
0541     double DRAMClockChangeWatermark;
0542     double WritebackDRAMClockChangeWatermark;
0543     double StutterEfficiency;
0544     double StutterEfficiencyNotIncludingVBlank;
0545     double NonUrgentLatencyTolerance;
0546     double MinActiveDRAMClockChangeLatencySupported;
0547     double Z8StutterEfficiencyBestCase;
0548     unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
0549     double Z8StutterEfficiencyNotIncludingVBlankBestCase;
0550     double StutterPeriodBestCase;
0551     Watermarks      Watermark;
0552     bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
0553     unsigned int CompBufReservedSpaceKBytes;
0554     unsigned int CompBufReservedSpace64B;
0555     unsigned int CompBufReservedSpaceZs;
0556     bool CompBufReservedSpaceNeedAdjustment;
0557 
0558     // These are the clocks calcuated by the library but they are not actually
0559     // used explicitly. They are fetched by tests and then possibly used. The
0560     // ultimate values to use are the ones specified by the parameters to DML
0561     double DISPCLK_calculated;
0562     double DPPCLK_calculated[DC__NUM_DPP__MAX];
0563 
0564     bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
0565 
0566     bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
0567     bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
0568     unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
0569     double VUpdateWidthPix[DC__NUM_DPP__MAX];
0570     double VReadyOffsetPix[DC__NUM_DPP__MAX];
0571 
0572     unsigned int TotImmediateFlipBytes;
0573     double TCalc;
0574 
0575     display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
0576     unsigned int cache_num_pipes;
0577     unsigned int pipe_plane[DC__NUM_DPP__MAX];
0578 
0579     /* vba mode support */
0580     /*inputs*/
0581     bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
0582     double MaxHSCLRatio;
0583     double MaxVSCLRatio;
0584     unsigned int MaxNumWriteback;
0585     bool WritebackLumaAndChromaScalingSupported;
0586     bool Cursor64BppSupport;
0587     double DCFCLKPerState[DC__VOLTAGE_STATES];
0588     double DCFCLKState[DC__VOLTAGE_STATES][2];
0589     double FabricClockPerState[DC__VOLTAGE_STATES];
0590     double SOCCLKPerState[DC__VOLTAGE_STATES];
0591     double PHYCLKPerState[DC__VOLTAGE_STATES];
0592     double DTBCLKPerState[DC__VOLTAGE_STATES];
0593     double MaxDppclk[DC__VOLTAGE_STATES];
0594     double MaxDSCCLK[DC__VOLTAGE_STATES];
0595     double DRAMSpeedPerState[DC__VOLTAGE_STATES];
0596     double MaxDispclk[DC__VOLTAGE_STATES];
0597     int VoltageOverrideLevel;
0598     double PHYCLKD32PerState[DC__VOLTAGE_STATES];
0599 
0600     /*outputs*/
0601     bool ScaleRatioAndTapsSupport;
0602     bool SourceFormatPixelAndScanSupport;
0603     double TotalBandwidthConsumedGBytePerSecond;
0604     bool DCCEnabledInAnyPlane;
0605     bool WritebackLatencySupport;
0606     bool WritebackModeSupport;
0607     bool Writeback10bpc420Supported;
0608     bool BandwidthSupport[DC__VOLTAGE_STATES];
0609     unsigned int TotalNumberOfActiveWriteback;
0610     double CriticalPoint;
0611     double ReturnBWToDCNPerState;
0612     bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0613     bool prefetch_vm_bw_valid;
0614     bool prefetch_row_bw_valid;
0615     bool NumberOfOTGSupport;
0616     bool NonsupportedDSCInputBPC;
0617     bool WritebackScaleRatioAndTapsSupport;
0618     bool CursorSupport;
0619     bool PitchSupport;
0620     enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES];
0621 
0622     /* Mode Support Reason */
0623     bool P2IWith420;
0624     bool DSCOnlyIfNecessaryWithBPP;
0625     bool DSC422NativeNotSupported;
0626     bool LinkRateDoesNotMatchDPVersion;
0627     bool LinkRateForMultistreamNotIndicated;
0628     bool BPPForMultistreamNotIndicated;
0629     bool MultistreamWithHDMIOreDP;
0630     bool MSOOrODMSplitWithNonDPLink;
0631     bool NotEnoughLanesForMSO;
0632     bool ViewportExceedsSurface;
0633 
0634     bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
0635     bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
0636     bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
0637     bool InvalidCombinationOfMALLUseForPState;
0638 
0639     enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX];
0640     double PrefetchLinesYThisState[DC__NUM_DPP__MAX];
0641     double PrefetchLinesCThisState[DC__NUM_DPP__MAX];
0642     double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX];
0643     double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX];
0644     double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX];
0645     double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX];
0646     double MetaRowBytesThisState[DC__NUM_DPP__MAX];
0647     bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0648     bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0649     bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX];
0650     bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX];
0651 
0652     unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
0653     double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0654     unsigned int MacroTileHeightY[DC__NUM_DPP__MAX];
0655     unsigned int MacroTileHeightC[DC__NUM_DPP__MAX];
0656     unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
0657     unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
0658     bool ImmediateFlipRequiredFinal;
0659     bool DCCProgrammingAssumesScanDirectionUnknownFinal;
0660     bool EnoughWritebackUnits;
0661     bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
0662     bool NumberOfDP2p0Support;
0663     unsigned int MaxNumDP2p0Streams;
0664     unsigned int MaxNumDP2p0Outputs;
0665     enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
0666     enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
0667     double WritebackLineBufferLumaBufferSize;
0668     double WritebackLineBufferChromaBufferSize;
0669     double WritebackMinHSCLRatio;
0670     double WritebackMinVSCLRatio;
0671     double WritebackMaxHSCLRatio;
0672     double WritebackMaxVSCLRatio;
0673     double WritebackMaxHSCLTaps;
0674     double WritebackMaxVSCLTaps;
0675     unsigned int MaxNumDPP;
0676     unsigned int MaxNumOTG;
0677     double CursorBufferSize;
0678     double CursorChunkSize;
0679     unsigned int Mode;
0680     double OutputLinkDPLanes[DC__NUM_DPP__MAX];
0681     double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only
0682     double ImmediateFlipBW[DC__NUM_DPP__MAX];
0683     double MaxMaxVStartup[DC__VOLTAGE_STATES][2];
0684 
0685     double WritebackLumaVExtra;
0686     double WritebackChromaVExtra;
0687     double WritebackRequiredDISPCLK;
0688     double MaximumSwathWidthSupport;
0689     double MaximumSwathWidthInDETBuffer;
0690     double MaximumSwathWidthInLineBuffer;
0691     double MaxDispclkRoundedDownToDFSGranularity;
0692     double MaxDppclkRoundedDownToDFSGranularity;
0693     double PlaneRequiredDISPCLKWithoutODMCombine;
0694     double PlaneRequiredDISPCLKWithODMCombine;
0695     double PlaneRequiredDISPCLK;
0696     double TotalNumberOfActiveOTG;
0697     double FECOverhead;
0698     double EffectiveFECOverhead;
0699     double Outbpp;
0700     unsigned int OutbppDSC;
0701     double TotalDSCUnitsRequired;
0702     double bpp;
0703     unsigned int slices;
0704     double SwathWidthGranularityY;
0705     double RoundedUpMaxSwathSizeBytesY;
0706     double SwathWidthGranularityC;
0707     double RoundedUpMaxSwathSizeBytesC;
0708     double EffectiveDETLBLinesLuma;
0709     double EffectiveDETLBLinesChroma;
0710     double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2];
0711     double PDEAndMetaPTEBytesPerFrameY;
0712     double PDEAndMetaPTEBytesPerFrameC;
0713     unsigned int MetaRowBytesY;
0714     unsigned int MetaRowBytesC;
0715     unsigned int DPTEBytesPerRowC;
0716     unsigned int DPTEBytesPerRowY;
0717     double ExtraLatency;
0718     double TimeCalc;
0719     double TWait;
0720     double MaximumReadBandwidthWithPrefetch;
0721     double MaximumReadBandwidthWithoutPrefetch;
0722     double total_dcn_read_bw_with_flip;
0723     double total_dcn_read_bw_with_flip_no_urgent_burst;
0724     double FractionOfUrgentBandwidth;
0725     double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output
0726 
0727     /* ms locals */
0728     double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2];
0729     unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0730     int NoOfDPPThisState[DC__NUM_DPP__MAX];
0731     enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
0732     double SwathWidthYThisState[DC__NUM_DPP__MAX];
0733     unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0734     unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
0735     unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX];
0736     double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0737     double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0738     double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0739     double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0740     double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0741     double RequiredDPPCLKThisState[DC__NUM_DPP__MAX];
0742     bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0743     bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0744     bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2];
0745     bool PrefetchSupported[DC__VOLTAGE_STATES][2];
0746     bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2];
0747     double RequiredDISPCLK[DC__VOLTAGE_STATES][2];
0748     bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2];
0749     bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2];
0750     unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2];
0751     unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2];
0752     bool ModeSupport[DC__VOLTAGE_STATES][2];
0753     double ReturnBWPerState[DC__VOLTAGE_STATES][2];
0754     bool DIOSupport[DC__VOLTAGE_STATES];
0755     bool NotEnoughDSCUnits[DC__VOLTAGE_STATES];
0756     bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
0757     bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
0758     double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES];
0759     bool ROBSupport[DC__VOLTAGE_STATES][2];
0760     //based on rev 99: Dim DCCMetaBufferSizeSupport(NumberOfStates, 1) As Boolean
0761     bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2];
0762     bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
0763     bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2];
0764     double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2];
0765     double PrefetchBW[DC__NUM_DPP__MAX];
0766     double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0767     double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0768     double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0769     double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0770     double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0771     unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
0772     unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
0773     double PrefillY[DC__NUM_DPP__MAX];
0774     double PrefillC[DC__NUM_DPP__MAX];
0775     double LineTimesForPrefetch[DC__NUM_DPP__MAX];
0776     double LinesForMetaPTE[DC__NUM_DPP__MAX];
0777     double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
0778     double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
0779     double SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
0780     double BytePerPixelInDETY[DC__NUM_DPP__MAX];
0781     double BytePerPixelInDETC[DC__NUM_DPP__MAX];
0782     bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
0783     unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
0784     double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
0785     double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
0786     double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
0787     bool ViewportSizeSupport[DC__VOLTAGE_STATES][2];
0788     unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
0789     unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
0790     unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
0791     unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
0792     double MaxSwathHeightY[DC__NUM_DPP__MAX];
0793     double MaxSwathHeightC[DC__NUM_DPP__MAX];
0794     double MinSwathHeightY[DC__NUM_DPP__MAX];
0795     double MinSwathHeightC[DC__NUM_DPP__MAX];
0796     double ReadBandwidthLuma[DC__NUM_DPP__MAX];
0797     double ReadBandwidthChroma[DC__NUM_DPP__MAX];
0798     double ReadBandwidth[DC__NUM_DPP__MAX];
0799     double WriteBandwidth[DC__NUM_DPP__MAX];
0800     double PSCL_FACTOR[DC__NUM_DPP__MAX];
0801     double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
0802     double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0803     double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
0804     double AlignedYPitch[DC__NUM_DPP__MAX];
0805     double AlignedCPitch[DC__NUM_DPP__MAX];
0806     double MaximumSwathWidth[DC__NUM_DPP__MAX];
0807     double cursor_bw[DC__NUM_DPP__MAX];
0808     double cursor_bw_pre[DC__NUM_DPP__MAX];
0809     double Tno_bw[DC__NUM_DPP__MAX];
0810     double prefetch_vmrow_bw[DC__NUM_DPP__MAX];
0811     double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
0812     double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
0813     double final_flip_bw[DC__NUM_DPP__MAX];
0814     bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2];
0815     double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
0816     unsigned int vm_group_bytes[DC__NUM_DPP__MAX];
0817     unsigned int dpte_group_bytes[DC__NUM_DPP__MAX];
0818     unsigned int dpte_row_height[DC__NUM_DPP__MAX];
0819     unsigned int meta_req_height[DC__NUM_DPP__MAX];
0820     unsigned int meta_req_width[DC__NUM_DPP__MAX];
0821     unsigned int meta_row_height[DC__NUM_DPP__MAX];
0822     unsigned int meta_row_width[DC__NUM_DPP__MAX];
0823     unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
0824     unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX];
0825     unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX];
0826     unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
0827     unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX];
0828     bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
0829     double meta_row_bw[DC__NUM_DPP__MAX];
0830     double dpte_row_bw[DC__NUM_DPP__MAX];
0831     double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX];                     // WM
0832     double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX];                     // WM
0833     double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX];
0834     double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX];
0835     enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2];
0836     double UrgentBurstFactorCursor[DC__NUM_DPP__MAX];
0837     double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX];
0838     double UrgentBurstFactorLuma[DC__NUM_DPP__MAX];
0839     double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX];
0840     double UrgentBurstFactorChroma[DC__NUM_DPP__MAX];
0841     double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX];
0842 
0843 
0844     bool           MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
0845     double         SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
0846     double         MaximumSwathWidthInLineBufferLuma;
0847     double         MaximumSwathWidthInLineBufferChroma;
0848     double         MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
0849     double         MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
0850     enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX];
0851     double         dummy1[DC__NUM_DPP__MAX];
0852     double         dummy2[DC__NUM_DPP__MAX];
0853     unsigned int   dummy3[DC__NUM_DPP__MAX];
0854     unsigned int   dummy4[DC__NUM_DPP__MAX];
0855     double         dummy5;
0856     double         dummy6;
0857     double         dummy7[DC__NUM_DPP__MAX];
0858     double         dummy8[DC__NUM_DPP__MAX];
0859     double         dummy13[DC__NUM_DPP__MAX];
0860     double         dummy_double_array[2][DC__NUM_DPP__MAX];
0861     unsigned int        dummyinteger3[DC__NUM_DPP__MAX];
0862     unsigned int        dummyinteger4[DC__NUM_DPP__MAX];
0863     unsigned int        dummyinteger5;
0864     unsigned int        dummyinteger6;
0865     unsigned int        dummyinteger7;
0866     unsigned int        dummyinteger8;
0867     unsigned int        dummyinteger9;
0868     unsigned int        dummyinteger10;
0869     unsigned int        dummyinteger11;
0870     unsigned int        dummy_integer_array[8][DC__NUM_DPP__MAX];
0871 
0872     bool           dummysinglestring;
0873     bool           SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
0874     double         PlaneRequiredDISPCLKWithODMCombine2To1;
0875     double         PlaneRequiredDISPCLKWithODMCombine4To1;
0876     unsigned int   TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2];
0877     bool           LinkDSCEnable;
0878     bool           ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES];
0879     enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX];
0880     double   SwathWidthCThisState[DC__NUM_DPP__MAX];
0881     bool           ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
0882     double         AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
0883     double         AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
0884 
0885     unsigned int NotEnoughUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
0886     unsigned int NotEnoughUrgentLatencyHidingPre;
0887     int PTEBufferSizeInRequestsForLuma;
0888     int PTEBufferSizeInRequestsForChroma;
0889 
0890     // Missing from VBA
0891     int dpte_group_bytes_chroma;
0892     unsigned int vm_group_bytes_chroma;
0893     double dst_x_after_scaler;
0894     double dst_y_after_scaler;
0895     unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
0896 
0897     /* perf locals*/
0898     double PrefetchBandwidth[DC__NUM_DPP__MAX];
0899     double VInitPreFillY[DC__NUM_DPP__MAX];
0900     double VInitPreFillC[DC__NUM_DPP__MAX];
0901     unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
0902     unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
0903     unsigned int VStartup[DC__NUM_DPP__MAX];
0904     double DSTYAfterScaler[DC__NUM_DPP__MAX];
0905     double DSTXAfterScaler[DC__NUM_DPP__MAX];
0906     bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
0907     bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
0908     double VRatioPrefetchY[DC__NUM_DPP__MAX];
0909     double VRatioPrefetchC[DC__NUM_DPP__MAX];
0910     double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
0911     double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
0912     double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
0913     double MinTTUVBlank[DC__NUM_DPP__MAX];
0914     double BytePerPixelDETY[DC__NUM_DPP__MAX];
0915     double BytePerPixelDETC[DC__NUM_DPP__MAX];
0916     double SwathWidthY[DC__NUM_DPP__MAX];
0917     double SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
0918     double CursorRequestDeliveryTime[DC__NUM_DPP__MAX];
0919     double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX];
0920     double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
0921     double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
0922     double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
0923     double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
0924     double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
0925     double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
0926     double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
0927     double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
0928     double MetaRowByte[DC__NUM_DPP__MAX];
0929     double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
0930     double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX];
0931     double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX];
0932     double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
0933     double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
0934     double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
0935     double DSCCLK_calculated[DC__NUM_DPP__MAX];
0936     unsigned int DSCDelay[DC__NUM_DPP__MAX];
0937     unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
0938     double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
0939     double DPPCLK[DC__NUM_DPP__MAX];
0940     unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
0941     unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
0942     unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
0943     double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
0944     unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
0945     unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
0946     unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
0947     unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
0948     double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
0949     double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
0950     double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
0951     double XFCTransferDelay[DC__NUM_DPP__MAX];
0952     double XFCPrechargeDelay[DC__NUM_DPP__MAX];
0953     double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
0954     double XFCPrefetchMargin[DC__NUM_DPP__MAX];
0955     unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
0956     unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
0957     double FullDETBufferingTimeY[DC__NUM_DPP__MAX];                     // WM
0958     double FullDETBufferingTimeC[DC__NUM_DPP__MAX];                     // WM
0959     double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX];
0960     double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX];
0961     double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX];
0962     double TimePerMetaChunkNominal[DC__NUM_DPP__MAX];
0963     double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX];
0964     double TimePerMetaChunkFlip[DC__NUM_DPP__MAX];
0965     unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX];
0966     unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX];
0967     unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX];
0968     unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX];
0969     unsigned int PTERequestSizeY[DC__NUM_DPP__MAX];
0970     unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX];
0971     unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX];
0972     unsigned int PTERequestSizeC[DC__NUM_DPP__MAX];
0973     double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX];
0974     double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX];
0975     double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX];
0976     double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX];
0977     double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX];
0978     double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX];
0979     double TimePerVMGroupVBlank[DC__NUM_DPP__MAX];
0980     double TimePerVMGroupFlip[DC__NUM_DPP__MAX];
0981     double TimePerVMRequestVBlank[DC__NUM_DPP__MAX];
0982     double TimePerVMRequestFlip[DC__NUM_DPP__MAX];
0983     unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
0984     unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
0985     unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
0986     unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
0987     double LinesToFinishSwathTransferStutterCriticalPlane;
0988     unsigned int BytePerPixelYCriticalPlane;
0989     double SwathWidthYCriticalPlane;
0990     double LinesInDETY[DC__NUM_DPP__MAX];
0991     double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
0992 
0993     double SwathWidthSingleDPPC[DC__NUM_DPP__MAX];
0994     double SwathWidthC[DC__NUM_DPP__MAX];
0995     unsigned int BytePerPixelY[DC__NUM_DPP__MAX];
0996     unsigned int BytePerPixelC[DC__NUM_DPP__MAX];
0997     unsigned int dummyinteger1;
0998     unsigned int dummyinteger2;
0999     double FinalDRAMClockChangeLatency;
1000     double Tdmdl_vm[DC__NUM_DPP__MAX];
1001     double Tdmdl[DC__NUM_DPP__MAX];
1002     double TSetup[DC__NUM_DPP__MAX];
1003     unsigned int ThisVStartup;
1004     bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
1005     double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX];
1006     double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX];
1007     double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX];
1008     double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
1009     unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
1010     unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
1011     double VStartupMargin;
1012     bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX];
1013 
1014     /* Missing from VBA */
1015     unsigned int MaximumMaxVStartupLines;
1016     double FabricAndDRAMBandwidth;
1017     double LinesInDETLuma;
1018     double LinesInDETChroma;
1019     unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
1020     unsigned int LinesInDETC[DC__NUM_DPP__MAX];
1021     unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
1022     double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1023     double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
1024     double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES];
1025     bool UrgentLatencySupport[DC__VOLTAGE_STATES][2];
1026     unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1027     unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1028     double qual_row_bw[DC__NUM_DPP__MAX];
1029     double prefetch_row_bw[DC__NUM_DPP__MAX];
1030     double prefetch_vm_bw[DC__NUM_DPP__MAX];
1031 
1032     double PTEGroupSize;
1033     unsigned int PDEProcessingBufIn64KBReqs;
1034 
1035     double MaxTotalVActiveRDBandwidth;
1036     bool DoUrgentLatencyAdjustment;
1037     double UrgentLatencyAdjustmentFabricClockComponent;
1038     double UrgentLatencyAdjustmentFabricClockReference;
1039     double MinUrgentLatencySupportUs;
1040     double MinFullDETBufferingTime;
1041     double AverageReadBandwidthGBytePerSecond;
1042     bool   FirstMainPlane;
1043 
1044     unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
1045     unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
1046     double HRatioChroma[DC__NUM_DPP__MAX];
1047     double VRatioChroma[DC__NUM_DPP__MAX];
1048     int WritebackSourceWidth[DC__NUM_DPP__MAX];
1049 
1050     bool ModeIsSupported;
1051     bool ODMCombine4To1Supported;
1052 
1053     unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
1054     unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
1055     unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
1056     unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
1057     unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
1058     unsigned int WritebackVTaps[DC__NUM_DPP__MAX];
1059     bool DSCEnable[DC__NUM_DPP__MAX];
1060 
1061     double DRAMClockChangeLatencyOverride;
1062 
1063     double GPUVMMinPageSize;
1064     double HostVMMinPageSize;
1065 
1066     bool   MPCCombineEnable[DC__NUM_DPP__MAX];
1067     unsigned int HostVMMaxNonCachedPageTableLevels;
1068     bool   DynamicMetadataVMEnabled;
1069     double       WritebackInterfaceBufferSize;
1070     double       WritebackLineBufferSize;
1071 
1072     double DCCRateLuma[DC__NUM_DPP__MAX];
1073     double DCCRateChroma[DC__NUM_DPP__MAX];
1074 
1075     double PHYCLKD18PerState[DC__VOLTAGE_STATES];
1076 
1077     bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
1078     bool NumberOfHDMIFRLSupport;
1079     unsigned int MaxNumHDMIFRLOutputs;
1080     int    AudioSampleRate[DC__NUM_DPP__MAX];
1081     int    AudioSampleLayout[DC__NUM_DPP__MAX];
1082 
1083     int PercentMarginOverMinimumRequiredDCFCLK;
1084     bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2];
1085     enum immediate_flip_requirement ImmediateFlipRequirement[DC__NUM_DPP__MAX];
1086     unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX];
1087     unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX];
1088     bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
1089     bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1090     int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
1091     int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
1092     double UrgLatency[DC__VOLTAGE_STATES];
1093     double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1094     double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1095     bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1096     bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1097     double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1098     double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1099     double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1100     double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1101     unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1102     unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1103     bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
1104     unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1105     unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1106     unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1107     unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1108     double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2];
1109     double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2];
1110     double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2];
1111     double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2];
1112     double WritebackDelayTime[DC__NUM_DPP__MAX];
1113     unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
1114     unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];
1115     unsigned int dummyinteger17;
1116     unsigned int dummyinteger18;
1117     unsigned int dummyinteger19;
1118     unsigned int dummyinteger20;
1119     unsigned int dummyinteger21;
1120     unsigned int dummyinteger22;
1121     unsigned int dummyinteger23;
1122     unsigned int dummyinteger24;
1123     unsigned int dummyinteger25;
1124     unsigned int dummyinteger26;
1125     unsigned int dummyinteger27;
1126     unsigned int dummyinteger28;
1127     unsigned int dummyinteger29;
1128     bool dummystring[DC__NUM_DPP__MAX];
1129     double BPP;
1130     enum odm_combine_policy ODMCombinePolicy;
1131     bool UseMinimumRequiredDCFCLK;
1132     bool ClampMinDCFCLK;
1133     bool AllowDramClockChangeOneDisplayVactive;
1134 
1135     double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation;
1136     double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency;
1137     double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData;
1138     double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly;
1139     double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly;
1140     double SRExitZ8Time;
1141     double SREnterPlusExitZ8Time;
1142     double Z8StutterExitWatermark;
1143     double Z8StutterEnterPlusExitWatermark;
1144     double Z8StutterEfficiencyNotIncludingVBlank;
1145     double Z8StutterEfficiency;
1146     double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX];
1147     double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX];
1148     double UrgBurstFactorCursor[DC__NUM_DPP__MAX];
1149     double UrgBurstFactorLuma[DC__NUM_DPP__MAX];
1150     double UrgBurstFactorChroma[DC__NUM_DPP__MAX];
1151     double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX];
1152     double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX];
1153     double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX];
1154     bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1155     bool LinkCapacitySupport[DC__NUM_DPP__MAX];
1156     bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];
1157     unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX];
1158     unsigned int VFrontPorch[DC__NUM_DPP__MAX];
1159     int ConfigReturnBufferSizeInKByte;
1160     enum unbounded_requesting_policy UseUnboundedRequesting;
1161     int CompressedBufferSegmentSizeInkByte;
1162     int CompressedBufferSizeInkByte;
1163     int MetaFIFOSizeInKEntries;
1164     int ZeroSizeBufferEntries;
1165     int COMPBUF_RESERVED_SPACE_64B;
1166     int COMPBUF_RESERVED_SPACE_ZS;
1167     bool UnboundedRequestEnabled;
1168     bool DSC422NativeSupport;
1169     bool NoEnoughUrgentLatencyHiding;
1170     bool NoEnoughUrgentLatencyHidingPre;
1171     int NumberOfStutterBurstsPerFrame;
1172     int Z8NumberOfStutterBurstsPerFrame;
1173     unsigned int MaximumDSCBitsPerComponent;
1174     unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
1175     double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
1176     double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
1177     double SurfaceRequiredDISPCLKWithoutODMCombine;
1178     double SurfaceRequiredDISPCLK;
1179     double MinActiveFCLKChangeLatencySupported;
1180     int MinVoltageLevel;
1181     int MaxVoltageLevel;
1182     unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
1183     unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
1184     unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1185     unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX];
1186     unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX];
1187     bool ExceededMALLSize;
1188     bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX];
1189     unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX];
1190     unsigned int CompressedBufferSizeInkByteThisState;
1191     enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2];
1192     bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
1193     enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX];
1194     bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];
1195     bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX];
1196     enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX];
1197     bool UnboundedRequestEnabledThisState;
1198     bool DRAMClockChangeRequirementFinal;
1199     bool FCLKChangeRequirementFinal;
1200     bool USRRetrainingRequiredFinal;
1201     unsigned int DETSizeOverride[DC__NUM_DPP__MAX];
1202     unsigned int nomDETInKByte;
1203     enum mpc_combine_affinity  MPCCombineUse[DC__NUM_DPP__MAX];
1204     bool MPCCombineMethodIncompatible;
1205     unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
1206     bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];
1207     enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX];
1208     unsigned int OutputMultistreamId[DC__NUM_DPP__MAX];
1209     bool OutputMultistreamEn[DC__NUM_DPP__MAX];
1210     bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
1211     double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
1212     double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
1213     bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1214     bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1215     bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
1216     bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];
1217     bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
1218     unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX];
1219     unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX];
1220     unsigned int BlockHeightY[DC__NUM_DPP__MAX];
1221     unsigned int BlockHeightC[DC__NUM_DPP__MAX];
1222     unsigned int BlockWidthY[DC__NUM_DPP__MAX];
1223     unsigned int BlockWidthC[DC__NUM_DPP__MAX];
1224     unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX];
1225     bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];
1226     struct dummy_vars dummy_vars;
1227 };
1228 
1229 bool CalculateMinAndMaxPrefetchMode(
1230         enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
1231         unsigned int *MinPrefetchMode,
1232         unsigned int *MaxPrefetchMode);
1233 
1234 double CalculateWriteBackDISPCLK(
1235         enum source_format_class WritebackPixelFormat,
1236         double PixelClock,
1237         double WritebackHRatio,
1238         double WritebackVRatio,
1239         unsigned int WritebackLumaHTaps,
1240         unsigned int WritebackLumaVTaps,
1241         unsigned int WritebackChromaHTaps,
1242         unsigned int WritebackChromaVTaps,
1243         double WritebackDestinationWidth,
1244         unsigned int HTotal,
1245         unsigned int WritebackChromaLineBufferWidth);
1246 
1247 #endif /* _DML2_DISPLAY_MODE_VBA_H_ */
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