dc/dml/display_mode_structs.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dc_features.h"
0027 #include "display_mode_enums.h"
0028
0029 #ifndef __DISPLAY_MODE_STRUCTS_H__
0030 #define __DISPLAY_MODE_STRUCTS_H__
0031
0032 typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
0033 typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
0034 typedef struct _vcs_dpi_ip_params_st ip_params_st;
0035 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
0036 typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
0037 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
0038 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
0039 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
0040 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
0041 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
0042 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
0043 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
0044 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
0045 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
0046 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
0047 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
0048 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
0049 typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st;
0050 typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st;
0051 typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
0052 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
0053 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
0054 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
0055 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
0056
0057 typedef struct {
0058     double UrgentWatermark;
0059     double WritebackUrgentWatermark;
0060     double DRAMClockChangeWatermark;
0061     double FCLKChangeWatermark;
0062     double WritebackDRAMClockChangeWatermark;
0063     double WritebackFCLKChangeWatermark;
0064     double StutterExitWatermark;
0065     double StutterEnterPlusExitWatermark;
0066     double Z8StutterExitWatermark;
0067     double Z8StutterEnterPlusExitWatermark;
0068     double USRRetrainingWatermark;
0069 } Watermarks;
0070
0071 typedef struct {
0072     double UrgentLatency;
0073     double ExtraLatency;
0074     double WritebackLatency;
0075     double DRAMClockChangeLatency;
0076     double FCLKChangeLatency;
0077     double SRExitTime;
0078     double SREnterPlusExitTime;
0079     double SRExitZ8Time;
0080     double SREnterPlusExitZ8Time;
0081     double USRRetrainingLatencyPlusSMNLatency;
0082 } Latencies;
0083
0084 typedef struct {
0085     double Dppclk;
0086     double Dispclk;
0087     double PixelClock;
0088     double DCFClkDeepSleep;
0089     unsigned int DPPPerSurface;
0090     bool ScalerEnabled;
0091     enum dm_rotation_angle SourceRotation;
0092     unsigned int ViewportHeight;
0093     unsigned int ViewportHeightChroma;
0094     unsigned int BlockWidth256BytesY;
0095     unsigned int BlockHeight256BytesY;
0096     unsigned int BlockWidth256BytesC;
0097     unsigned int BlockHeight256BytesC;
0098     unsigned int BlockWidthY;
0099     unsigned int BlockHeightY;
0100     unsigned int BlockWidthC;
0101     unsigned int BlockHeightC;
0102     unsigned int InterlaceEnable;
0103     unsigned int NumberOfCursors;
0104     unsigned int VBlank;
0105     unsigned int HTotal;
0106     unsigned int HActive;
0107     bool DCCEnable;
0108     enum odm_combine_mode ODMMode;
0109     enum source_format_class SourcePixelFormat;
0110     enum dm_swizzle_mode SurfaceTiling;
0111     unsigned int BytePerPixelY;
0112     unsigned int BytePerPixelC;
0113     bool ProgressiveToInterlaceUnitInOPP;
0114     double VRatio;
0115     double VRatioChroma;
0116     unsigned int VTaps;
0117     unsigned int VTapsChroma;
0118     unsigned int PitchY;
0119     unsigned int DCCMetaPitchY;
0120     unsigned int PitchC;
0121     unsigned int DCCMetaPitchC;
0122     bool ViewportStationary;
0123     unsigned int ViewportXStart;
0124     unsigned int ViewportYStart;
0125     unsigned int ViewportXStartC;
0126     unsigned int ViewportYStartC;
0127     bool FORCE_ONE_ROW_FOR_FRAME;
0128     unsigned int SwathHeightY;
0129     unsigned int SwathHeightC;
0130 } DmlPipe;
0131
0132 typedef struct {
0133     double UrgentLatency;
0134     double ExtraLatency;
0135     double WritebackLatency;
0136     double DRAMClockChangeLatency;
0137     double FCLKChangeLatency;
0138     double SRExitTime;
0139     double SREnterPlusExitTime;
0140     double SRExitZ8Time;
0141     double SREnterPlusExitZ8Time;
0142     double USRRetrainingLatency;
0143     double SMNLatency;
0144 } SOCParametersList;
0145
0146 struct _vcs_dpi_voltage_scaling_st {
0147     int state;
0148     double dscclk_mhz;
0149     double dcfclk_mhz;
0150     double socclk_mhz;
0151     double phyclk_d18_mhz;
0152     double phyclk_d32_mhz;
0153     double dram_speed_mts;
0154     double fabricclk_mhz;
0155     double dispclk_mhz;
0156     double dram_bw_per_chan_gbps;
0157     double phyclk_mhz;
0158     double dppclk_mhz;
0159     double dtbclk_mhz;
0160 };
0161
0162 struct _vcs_dpi_soc_bounding_box_st {
0163     struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
0164     /*
0165      * This is a temporary stash for updating @clock_limits with the PMFW
0166      * clock table. Do not use outside of *update_bw_boudning_box functions.
0167      */
0168     struct _vcs_dpi_voltage_scaling_st _clock_tmp[DC__VOLTAGE_STATES];
0169     unsigned int num_states;
0170     double sr_exit_time_us;
0171     double sr_enter_plus_exit_time_us;
0172     double sr_exit_z8_time_us;
0173     double sr_enter_plus_exit_z8_time_us;
0174     double urgent_latency_us;
0175     double urgent_latency_pixel_data_only_us;
0176     double urgent_latency_pixel_mixed_with_vm_data_us;
0177     double urgent_latency_vm_data_only_us;
0178     double usr_retraining_latency_us;
0179     double smn_latency_us;
0180     double fclk_change_latency_us;
0181     double mall_allocated_for_dcn_mbytes;
0182     double pct_ideal_fabric_bw_after_urgent;
0183     double pct_ideal_dram_bw_after_urgent_strobe;
0184     double max_avg_fabric_bw_use_normal_percent;
0185     double max_avg_dram_bw_use_normal_strobe_percent;
0186     enum dm_prefetch_modes allow_for_pstate_or_stutter_in_vblank_final;
0187     bool dram_clock_change_requirement_final;
0188     double writeback_latency_us;
0189     double ideal_dram_bw_after_urgent_percent;
0190     double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
0191     double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
0192     double pct_ideal_dram_sdp_bw_after_urgent_vm_only;
0193     double pct_ideal_sdp_bw_after_urgent;
0194     double max_avg_sdp_bw_use_normal_percent;
0195     double max_avg_dram_bw_use_normal_percent;
0196     unsigned int max_request_size_bytes;
0197     double downspread_percent;
0198     double dram_page_open_time_ns;
0199     double dram_rw_turnaround_time_ns;
0200     double dram_return_buffer_per_channel_bytes;
0201     double dram_channel_width_bytes;
0202     double fabric_datapath_to_dcn_data_return_bytes;
0203     double dcn_downspread_percent;
0204     double dispclk_dppclk_vco_speed_mhz;
0205     double dfs_vco_period_ps;
0206     unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
0207     unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
0208     unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
0209     unsigned int round_trip_ping_latency_dcfclk_cycles;
0210     unsigned int urgent_out_of_order_return_per_channel_bytes;
0211     unsigned int channel_interleave_bytes;
0212     unsigned int num_banks;
0213     unsigned int num_chans;
0214     unsigned int vmm_page_size_bytes;
0215     unsigned int hostvm_min_page_size_bytes;
0216     unsigned int gpuvm_min_page_size_bytes;
0217     double dram_clock_change_latency_us;
0218     double dummy_pstate_latency_us;
0219     double writeback_dram_clock_change_latency_us;
0220     unsigned int return_bus_width_bytes;
0221     unsigned int voltage_override;
0222     double xfc_bus_transport_time_us;
0223     double xfc_xbuf_latency_tolerance_us;
0224     int use_urgent_burst_bw;
0225     double min_dcfclk;
0226     bool do_urgent_latency_adjustment;
0227     double urgent_latency_adjustment_fabric_clock_component_us;
0228     double urgent_latency_adjustment_fabric_clock_reference_mhz;
0229     bool disable_dram_clock_change_vactive_support;
0230     bool allow_dram_clock_one_display_vactive;
0231     enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank;
0232 };
0233
0234 struct _vcs_dpi_ip_params_st {
0235     bool use_min_dcfclk;
0236     bool clamp_min_dcfclk;
0237     bool gpuvm_enable;
0238     bool hostvm_enable;
0239     bool dsc422_native_support;
0240     unsigned int gpuvm_max_page_table_levels;
0241     unsigned int hostvm_max_page_table_levels;
0242     unsigned int hostvm_cached_page_table_levels;
0243     unsigned int pte_group_size_bytes;
0244     unsigned int max_inter_dcn_tile_repeaters;
0245     unsigned int num_dsc;
0246     unsigned int odm_capable;
0247     unsigned int rob_buffer_size_kbytes;
0248     unsigned int det_buffer_size_kbytes;
0249     unsigned int min_comp_buffer_size_kbytes;
0250     unsigned int dpte_buffer_size_in_pte_reqs_luma;
0251     unsigned int dpte_buffer_size_in_pte_reqs_chroma;
0252     unsigned int pde_proc_buffer_size_64k_reqs;
0253     unsigned int dpp_output_buffer_pixels;
0254     unsigned int opp_output_buffer_lines;
0255     unsigned int pixel_chunk_size_kbytes;
0256     unsigned int alpha_pixel_chunk_size_kbytes;
0257     unsigned int min_pixel_chunk_size_bytes;
0258     unsigned int dcc_meta_buffer_size_bytes;
0259     unsigned char pte_enable;
0260     unsigned int pte_chunk_size_kbytes;
0261     unsigned int meta_chunk_size_kbytes;
0262     unsigned int min_meta_chunk_size_bytes;
0263     unsigned int writeback_chunk_size_kbytes;
0264     unsigned int line_buffer_size_bits;
0265     unsigned int max_line_buffer_lines;
0266     unsigned int writeback_luma_buffer_size_kbytes;
0267     unsigned int writeback_chroma_buffer_size_kbytes;
0268     unsigned int writeback_chroma_line_buffer_width_pixels;
0269
0270     unsigned int writeback_interface_buffer_size_kbytes;
0271     unsigned int writeback_line_buffer_buffer_size;
0272
0273     unsigned int writeback_10bpc420_supported;
0274     double writeback_max_hscl_ratio;
0275     double writeback_max_vscl_ratio;
0276     double writeback_min_hscl_ratio;
0277     double writeback_min_vscl_ratio;
0278     unsigned int maximum_dsc_bits_per_component;
0279     unsigned int maximum_pixels_per_line_per_dsc_unit;
0280     unsigned int writeback_max_hscl_taps;
0281     unsigned int writeback_max_vscl_taps;
0282     unsigned int writeback_line_buffer_luma_buffer_size;
0283     unsigned int writeback_line_buffer_chroma_buffer_size;
0284
0285     unsigned int max_page_table_levels;
0286     unsigned int max_num_dpp;
0287     unsigned int max_num_otg;
0288     unsigned int cursor_chunk_size;
0289     unsigned int cursor_buffer_size;
0290     unsigned int max_num_wb;
0291     unsigned int max_dchub_pscl_bw_pix_per_clk;
0292     unsigned int max_pscl_lb_bw_pix_per_clk;
0293     unsigned int max_lb_vscl_bw_pix_per_clk;
0294     unsigned int max_vscl_hscl_bw_pix_per_clk;
0295     double max_hscl_ratio;
0296     double max_vscl_ratio;
0297     unsigned int hscl_mults;
0298     unsigned int vscl_mults;
0299     unsigned int max_hscl_taps;
0300     unsigned int max_vscl_taps;
0301     unsigned int xfc_supported;
0302     unsigned int ptoi_supported;
0303     unsigned int gfx7_compat_tiling_supported;
0304
0305     bool odm_combine_4to1_supported;
0306     bool dynamic_metadata_vm_enabled;
0307     unsigned int max_num_hdmi_frl_outputs;
0308
0309     unsigned int xfc_fill_constant_bytes;
0310     double dispclk_ramp_margin_percent;
0311     double xfc_fill_bw_overhead_percent;
0312     double underscan_factor;
0313     unsigned int min_vblank_lines;
0314     unsigned int dppclk_delay_subtotal;
0315     unsigned int dispclk_delay_subtotal;
0316     double dcfclk_cstate_latency;
0317     unsigned int dppclk_delay_scl;
0318     unsigned int dppclk_delay_scl_lb_only;
0319     unsigned int dppclk_delay_cnvc_formatter;
0320     unsigned int dppclk_delay_cnvc_cursor;
0321     unsigned int is_line_buffer_bpp_fixed;
0322     unsigned int line_buffer_fixed_bpp;
0323     unsigned int dcc_supported;
0324     unsigned int config_return_buffer_size_in_kbytes;
0325     unsigned int compressed_buffer_segment_size_in_kbytes;
0326     unsigned int meta_fifo_size_in_kentries;
0327     unsigned int zero_size_buffer_entries;
0328     unsigned int compbuf_reserved_space_64b;
0329     unsigned int compbuf_reserved_space_zs;
0330
0331     unsigned int IsLineBufferBppFixed;
0332     unsigned int LineBufferFixedBpp;
0333     unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
0334     unsigned int bug_forcing_LC_req_same_size_fixed;
0335     unsigned int number_of_cursors;
0336     unsigned int max_num_dp2p0_outputs;
0337     unsigned int max_num_dp2p0_streams;
0338     unsigned int VBlankNomDefaultUS;
0339 };
0340
0341 struct _vcs_dpi_display_xfc_params_st {
0342     double xfc_tslv_vready_offset_us;
0343     double xfc_tslv_vupdate_width_us;
0344     double xfc_tslv_vupdate_offset_us;
0345     int xfc_slv_chunk_size_bytes;
0346 };
0347
0348 struct _vcs_dpi_display_pipe_source_params_st {
0349     int source_format;
0350     double dcc_fraction_of_zs_req_luma;
0351     double dcc_fraction_of_zs_req_chroma;
0352     unsigned char dcc;
0353     unsigned int dcc_rate;
0354     unsigned int dcc_rate_chroma;
0355     unsigned char dcc_use_global;
0356     unsigned char vm;
0357     bool unbounded_req_mode;
0358     bool gpuvm;    // gpuvm enabled
0359     bool hostvm;    // hostvm enabled
0360     bool gpuvm_levels_force_en;
0361     unsigned int gpuvm_levels_force;
0362     bool hostvm_levels_force_en;
0363     unsigned int hostvm_levels_force;
0364     int source_scan;
0365     int source_rotation; // new in dml32
0366     unsigned int det_size_override; // use to populate DETSizeOverride in vba struct
0367     int sw_mode;
0368     int macro_tile_size;
0369     unsigned int surface_width_y;
0370     unsigned int surface_height_y;
0371     unsigned int surface_width_c;
0372     unsigned int surface_height_c;
0373     unsigned int viewport_width;
0374     unsigned int viewport_height;
0375     unsigned int viewport_y_y;
0376     unsigned int viewport_y_c;
0377     unsigned int viewport_width_c;
0378     unsigned int viewport_height_c;
0379     unsigned int viewport_width_max;
0380     unsigned int viewport_height_max;
0381     unsigned int viewport_x_y;
0382     unsigned int viewport_x_c;
0383     bool viewport_stationary;
0384     unsigned int dcc_rate_luma;
0385     unsigned int gpuvm_min_page_size_kbytes;
0386     unsigned int use_mall_for_pstate_change;
0387     unsigned int use_mall_for_static_screen;
0388     bool force_one_row_for_frame;
0389     bool pte_buffer_mode;
0390     unsigned int data_pitch;
0391     unsigned int data_pitch_c;
0392     unsigned int meta_pitch;
0393     unsigned int meta_pitch_c;
0394     unsigned int cur0_src_width;
0395     int cur0_bpp;
0396     unsigned int cur1_src_width;
0397     int cur1_bpp;
0398     int num_cursors;
0399     unsigned char is_hsplit;
0400     unsigned char dynamic_metadata_enable;
0401     unsigned int dynamic_metadata_lines_before_active;
0402     unsigned int dynamic_metadata_xmit_bytes;
0403     unsigned int hsplit_grp;
0404     unsigned char xfc_enable;
0405     unsigned char xfc_slave;
0406     unsigned char immediate_flip;
0407     struct _vcs_dpi_display_xfc_params_st xfc_params;
0408     //for vstartuplines calculation freesync
0409     unsigned char v_total_min;
0410     unsigned char v_total_max;
0411 };
0412 struct writeback_st {
0413     int wb_src_height;
0414     int wb_src_width;
0415     int wb_dst_width;
0416     int wb_dst_height;
0417     int wb_pixel_format;
0418     int wb_htaps_luma;
0419     int wb_vtaps_luma;
0420     int wb_htaps_chroma;
0421     int wb_vtaps_chroma;
0422     unsigned int wb_htaps;
0423     unsigned int wb_vtaps;
0424     double wb_hratio;
0425     double wb_vratio;
0426 };
0427
0428 struct display_audio_params_st {
0429     unsigned int   audio_sample_rate_khz;
0430     int            audio_sample_layout;
0431 };
0432
0433 struct _vcs_dpi_display_output_params_st {
0434     int dp_lanes;
0435     double output_bpp;
0436     unsigned int dsc_input_bpc;
0437     int dsc_enable;
0438     int wb_enable;
0439     int num_active_wb;
0440     int output_type;
0441     int is_virtual;
0442     int output_format;
0443     int dsc_slices;
0444     int max_audio_sample_rate;
0445     struct writeback_st wb;
0446     struct display_audio_params_st audio;
0447     unsigned int output_bpc;
0448     int dp_rate;
0449     unsigned int dp_multistream_id;
0450     bool dp_multistream_en;
0451 };
0452
0453 struct _vcs_dpi_scaler_ratio_depth_st {
0454     double hscl_ratio;
0455     double vscl_ratio;
0456     double hscl_ratio_c;
0457     double vscl_ratio_c;
0458     double vinit;
0459     double vinit_c;
0460     double vinit_bot;
0461     double vinit_bot_c;
0462     int lb_depth;
0463     int scl_enable;
0464 };
0465
0466 struct _vcs_dpi_scaler_taps_st {
0467     unsigned int htaps;
0468     unsigned int vtaps;
0469     unsigned int htaps_c;
0470     unsigned int vtaps_c;
0471 };
0472
0473 struct _vcs_dpi_display_pipe_dest_params_st {
0474     unsigned int recout_width;
0475     unsigned int recout_height;
0476     unsigned int full_recout_width;
0477     unsigned int full_recout_height;
0478     unsigned int hblank_start;
0479     unsigned int hblank_end;
0480     unsigned int vblank_start;
0481     unsigned int vblank_end;
0482     unsigned int htotal;
0483     unsigned int vtotal;
0484     unsigned int vfront_porch;
0485     unsigned int vactive;
0486     unsigned int hactive;
0487     unsigned int vstartup_start;
0488     unsigned int vupdate_offset;
0489     unsigned int vupdate_width;
0490     unsigned int vready_offset;
0491     unsigned char interlaced;
0492     double pixel_rate_mhz;
0493     unsigned char synchronized_vblank_all_planes;
0494     unsigned char otg_inst;
0495     unsigned int odm_combine;
0496     unsigned char use_maximum_vstartup;
0497     unsigned int vtotal_max;
0498     unsigned int vtotal_min;
0499     unsigned int refresh_rate;
0500     bool synchronize_timings;
0501     unsigned int odm_combine_policy;
0502     bool drr_display;
0503 };
0504
0505 struct _vcs_dpi_display_pipe_params_st {
0506     display_pipe_source_params_st src;
0507     display_pipe_dest_params_st dest;
0508     scaler_ratio_depth_st scale_ratio_depth;
0509     scaler_taps_st scale_taps;
0510 };
0511
0512 struct _vcs_dpi_display_clocks_and_cfg_st {
0513     int voltage;
0514     double dppclk_mhz;
0515     double refclk_mhz;
0516     double dispclk_mhz;
0517     double dcfclk_mhz;
0518     double socclk_mhz;
0519 };
0520
0521 struct _vcs_dpi_display_e2e_pipe_params_st {
0522     display_pipe_params_st pipe;
0523     display_output_params_st dout;
0524     display_clocks_and_cfg_st clks_cfg;
0525 };
0526
0527 struct _vcs_dpi_display_data_rq_misc_params_st {
0528     unsigned int full_swath_bytes;
0529     unsigned int stored_swath_bytes;
0530     unsigned int blk256_height;
0531     unsigned int blk256_width;
0532     unsigned int req_height;
0533     unsigned int req_width;
0534 };
0535
0536 struct _vcs_dpi_display_data_rq_sizing_params_st {
0537     unsigned int chunk_bytes;
0538     unsigned int min_chunk_bytes;
0539     unsigned int meta_chunk_bytes;
0540     unsigned int min_meta_chunk_bytes;
0541     unsigned int mpte_group_bytes;
0542     unsigned int dpte_group_bytes;
0543 };
0544
0545 struct _vcs_dpi_display_data_rq_dlg_params_st {
0546     unsigned int swath_width_ub;
0547     unsigned int swath_height;
0548     unsigned int req_per_swath_ub;
0549     unsigned int meta_pte_bytes_per_frame_ub;
0550     unsigned int dpte_req_per_row_ub;
0551     unsigned int dpte_groups_per_row_ub;
0552     unsigned int dpte_row_height;
0553     unsigned int dpte_bytes_per_row_ub;
0554     unsigned int meta_chunks_per_row_ub;
0555     unsigned int meta_req_per_row_ub;
0556     unsigned int meta_row_height;
0557     unsigned int meta_bytes_per_row_ub;
0558 };
0559
0560 struct _vcs_dpi_display_rq_dlg_params_st {
0561     display_data_rq_dlg_params_st rq_l;
0562     display_data_rq_dlg_params_st rq_c;
0563 };
0564
0565 struct _vcs_dpi_display_rq_sizing_params_st {
0566     display_data_rq_sizing_params_st rq_l;
0567     display_data_rq_sizing_params_st rq_c;
0568 };
0569
0570 struct _vcs_dpi_display_rq_misc_params_st {
0571     display_data_rq_misc_params_st rq_l;
0572     display_data_rq_misc_params_st rq_c;
0573 };
0574
0575 struct _vcs_dpi_display_rq_params_st {
0576     unsigned char yuv420;
0577     unsigned char yuv420_10bpc;
0578     unsigned char rgbe_alpha;
0579     display_rq_misc_params_st misc;
0580     display_rq_sizing_params_st sizing;
0581     display_rq_dlg_params_st dlg;
0582 };
0583
0584 struct _vcs_dpi_display_dlg_regs_st {
0585     unsigned int refcyc_h_blank_end;
0586     unsigned int dlg_vblank_end;
0587     unsigned int min_dst_y_next_start;
0588     unsigned int optimized_min_dst_y_next_start;
0589     unsigned int optimized_min_dst_y_next_start_us;
0590     unsigned int refcyc_per_htotal;
0591     unsigned int refcyc_x_after_scaler;
0592     unsigned int dst_y_after_scaler;
0593     unsigned int dst_y_prefetch;
0594     unsigned int dst_y_per_vm_vblank;
0595     unsigned int dst_y_per_row_vblank;
0596     unsigned int dst_y_per_vm_flip;
0597     unsigned int dst_y_per_row_flip;
0598     unsigned int ref_freq_to_pix_freq;
0599     unsigned int vratio_prefetch;
0600     unsigned int vratio_prefetch_c;
0601     unsigned int refcyc_per_pte_group_vblank_l;
0602     unsigned int refcyc_per_pte_group_vblank_c;
0603     unsigned int refcyc_per_meta_chunk_vblank_l;
0604     unsigned int refcyc_per_meta_chunk_vblank_c;
0605     unsigned int refcyc_per_pte_group_flip_l;
0606     unsigned int refcyc_per_pte_group_flip_c;
0607     unsigned int refcyc_per_meta_chunk_flip_l;
0608     unsigned int refcyc_per_meta_chunk_flip_c;
0609     unsigned int dst_y_per_pte_row_nom_l;
0610     unsigned int dst_y_per_pte_row_nom_c;
0611     unsigned int refcyc_per_pte_group_nom_l;
0612     unsigned int refcyc_per_pte_group_nom_c;
0613     unsigned int dst_y_per_meta_row_nom_l;
0614     unsigned int dst_y_per_meta_row_nom_c;
0615     unsigned int refcyc_per_meta_chunk_nom_l;
0616     unsigned int refcyc_per_meta_chunk_nom_c;
0617     unsigned int refcyc_per_line_delivery_pre_l;
0618     unsigned int refcyc_per_line_delivery_pre_c;
0619     unsigned int refcyc_per_line_delivery_l;
0620     unsigned int refcyc_per_line_delivery_c;
0621     unsigned int chunk_hdl_adjust_cur0;
0622     unsigned int chunk_hdl_adjust_cur1;
0623     unsigned int vready_after_vcount0;
0624     unsigned int dst_y_offset_cur0;
0625     unsigned int dst_y_offset_cur1;
0626     unsigned int xfc_reg_transfer_delay;
0627     unsigned int xfc_reg_precharge_delay;
0628     unsigned int xfc_reg_remote_surface_flip_latency;
0629     unsigned int xfc_reg_prefetch_margin;
0630     unsigned int dst_y_delta_drq_limit;
0631     unsigned int refcyc_per_vm_group_vblank;
0632     unsigned int refcyc_per_vm_group_flip;
0633     unsigned int refcyc_per_vm_req_vblank;
0634     unsigned int refcyc_per_vm_req_flip;
0635     unsigned int refcyc_per_vm_dmdata;
0636     unsigned int dmdata_dl_delta;
0637 };
0638
0639 struct _vcs_dpi_display_ttu_regs_st {
0640     unsigned int qos_level_low_wm;
0641     unsigned int qos_level_high_wm;
0642     unsigned int min_ttu_vblank;
0643     unsigned int qos_level_flip;
0644     unsigned int refcyc_per_req_delivery_l;
0645     unsigned int refcyc_per_req_delivery_c;
0646     unsigned int refcyc_per_req_delivery_cur0;
0647     unsigned int refcyc_per_req_delivery_cur1;
0648     unsigned int refcyc_per_req_delivery_pre_l;
0649     unsigned int refcyc_per_req_delivery_pre_c;
0650     unsigned int refcyc_per_req_delivery_pre_cur0;
0651     unsigned int refcyc_per_req_delivery_pre_cur1;
0652     unsigned int qos_level_fixed_l;
0653     unsigned int qos_level_fixed_c;
0654     unsigned int qos_level_fixed_cur0;
0655     unsigned int qos_level_fixed_cur1;
0656     unsigned int qos_ramp_disable_l;
0657     unsigned int qos_ramp_disable_c;
0658     unsigned int qos_ramp_disable_cur0;
0659     unsigned int qos_ramp_disable_cur1;
0660 };
0661
0662 struct _vcs_dpi_display_data_rq_regs_st {
0663     unsigned int chunk_size;
0664     unsigned int min_chunk_size;
0665     unsigned int meta_chunk_size;
0666     unsigned int min_meta_chunk_size;
0667     unsigned int dpte_group_size;
0668     unsigned int mpte_group_size;
0669     unsigned int swath_height;
0670     unsigned int pte_row_height_linear;
0671 };
0672
0673 struct _vcs_dpi_display_rq_regs_st {
0674     display_data_rq_regs_st rq_regs_l;
0675     display_data_rq_regs_st rq_regs_c;
0676     unsigned int drq_expansion_mode;
0677     unsigned int prq_expansion_mode;
0678     unsigned int mrq_expansion_mode;
0679     unsigned int crq_expansion_mode;
0680     unsigned int plane1_base_address;
0681     unsigned int aperture_low_addr;   // bits [47:18]
0682     unsigned int aperture_high_addr;  // bits [47:18]
0683 };
0684
0685 struct _vcs_dpi_display_dlg_sys_params_st {
0686     double t_mclk_wm_us;
0687     double t_urg_wm_us;
0688     double t_sr_wm_us;
0689     double t_extra_us;
0690     double mem_trip_us;
0691     double deepsleep_dcfclk_mhz;
0692     double total_flip_bw;
0693     unsigned int total_flip_bytes;
0694 };
0695
0696 struct _vcs_dpi_display_arb_params_st {
0697     int max_req_outstanding;
0698     int min_req_outstanding;
0699     int sat_level_us;
0700     int hvm_min_req_outstand_commit_threshold;
0701     int hvm_max_qos_commit_threshold;
0702     int compbuf_reserved_space_kbytes;
0703 };
0704
0705 #endif /*__DISPLAY_MODE_STRUCTS_H__*/