dc/dml/display_mode_enums.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 #ifndef __DISPLAY_MODE_ENUMS_H__
0026 #define __DISPLAY_MODE_ENUMS_H__
0027
0028 enum output_encoder_class {
0029     dm_dp = 0,
0030     dm_hdmi = 1,
0031     dm_wb = 2,
0032     dm_edp = 3,
0033     dm_dp2p0 = 5,
0034 };
0035 enum output_format_class {
0036     dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
0037 };
0038 enum source_format_class {
0039     dm_444_16 = 0,
0040     dm_444_32 = 1,
0041     dm_444_64 = 2,
0042     dm_420_8 = 3,
0043     dm_420_10 = 4,
0044     dm_420_12 = 5,
0045     dm_422_8 = 6,
0046     dm_422_10 = 7,
0047     dm_444_8 = 8,
0048     dm_mono_8 = dm_444_8,
0049     dm_mono_16 = dm_444_16,
0050     dm_rgbe = 9,
0051     dm_rgbe_alpha = 10,
0052 };
0053 enum output_bpc_class {
0054     dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
0055 };
0056 enum scan_direction_class {
0057     dm_horz = 0, dm_vert = 1
0058 };
0059 enum dm_swizzle_mode {
0060     dm_sw_linear = 0,
0061     dm_sw_256b_s = 1,
0062     dm_sw_256b_d = 2,
0063     dm_sw_SPARE_0 = 3,
0064     dm_sw_SPARE_1 = 4,
0065     dm_sw_4kb_s = 5,
0066     dm_sw_4kb_d = 6,
0067     dm_sw_SPARE_2 = 7,
0068     dm_sw_SPARE_3 = 8,
0069     dm_sw_64kb_s = 9,
0070     dm_sw_64kb_d = 10,
0071     dm_sw_SPARE_4 = 11,
0072     dm_sw_SPARE_5 = 12,
0073     dm_sw_var_s = 13,
0074     dm_sw_var_d = 14,
0075     dm_sw_SPARE_6 = 15,
0076     dm_sw_SPARE_7 = 16,
0077     dm_sw_64kb_s_t = 17,
0078     dm_sw_64kb_d_t = 18,
0079     dm_sw_SPARE_10 = 19,
0080     dm_sw_SPARE_11 = 20,
0081     dm_sw_4kb_s_x = 21,
0082     dm_sw_4kb_d_x = 22,
0083     dm_sw_SPARE_12 = 23,
0084     dm_sw_SPARE_13 = 24,
0085     dm_sw_64kb_s_x = 25,
0086     dm_sw_64kb_d_x = 26,
0087     dm_sw_64kb_r_x = 27,
0088     dm_sw_SPARE_15 = 28,
0089     dm_sw_var_s_x = 29,
0090     dm_sw_var_d_x = 30,
0091     dm_sw_var_r_x = 31,
0092     dm_sw_gfx7_2d_thin_l_vp,
0093     dm_sw_gfx7_2d_thin_gl,
0094 };
0095 enum lb_depth {
0096     dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
0097     dm_lb_19 = 5
0098 };
0099 enum voltage_state {
0100     dm_vmin = 0, dm_vmid = 1, dm_vnom = 2, dm_vmax = 3
0101 };
0102 enum source_macro_tile_size {
0103     dm_4k_tile = 0, dm_64k_tile = 1, dm_256k_tile = 2
0104 };
0105 enum cursor_bpp {
0106     dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2
0107 };
0108 enum clock_change_support {
0109     dm_dram_clock_change_uninitialized = 0,
0110     dm_dram_clock_change_vactive,
0111     dm_dram_clock_change_vblank,
0112     dm_dram_clock_change_vactive_w_mall_full_frame,
0113     dm_dram_clock_change_vactive_w_mall_sub_vp,
0114     dm_dram_clock_change_vblank_w_mall_full_frame,
0115     dm_dram_clock_change_vblank_w_mall_sub_vp,
0116     dm_dram_clock_change_unsupported
0117 };
0118
0119 enum output_standard {
0120     dm_std_uninitialized = 0,
0121     dm_std_cvtr2,
0122     dm_std_cvt
0123 };
0124
0125 enum mpc_combine_affinity {
0126     dm_mpc_always_when_possible,
0127     dm_mpc_reduce_voltage,
0128     dm_mpc_reduce_voltage_and_clocks,
0129     dm_mpc_never
0130 };
0131
0132 enum RequestType {
0133     REQ_256Bytes, REQ_128BytesNonContiguous, REQ_128BytesContiguous, REQ_NA
0134 };
0135
0136 enum self_refresh_affinity {
0137     dm_try_to_allow_self_refresh_and_mclk_switch,
0138     dm_allow_self_refresh_and_mclk_switch,
0139     dm_allow_self_refresh,
0140     dm_neither_self_refresh_nor_mclk_switch
0141 };
0142
0143 enum dm_validation_status {
0144     DML_VALIDATION_OK,
0145     DML_FAIL_SCALE_RATIO_TAP,
0146     DML_FAIL_SOURCE_PIXEL_FORMAT,
0147     DML_FAIL_VIEWPORT_SIZE,
0148     DML_FAIL_TOTAL_V_ACTIVE_BW,
0149     DML_FAIL_DIO_SUPPORT,
0150     DML_FAIL_NOT_ENOUGH_DSC,
0151     DML_FAIL_DSC_CLK_REQUIRED,
0152     DML_FAIL_DSC_VALIDATION_FAILURE,
0153     DML_FAIL_URGENT_LATENCY,
0154     DML_FAIL_REORDERING_BUFFER,
0155     DML_FAIL_DISPCLK_DPPCLK,
0156     DML_FAIL_TOTAL_AVAILABLE_PIPES,
0157     DML_FAIL_NUM_OTG,
0158     DML_FAIL_WRITEBACK_MODE,
0159     DML_FAIL_WRITEBACK_LATENCY,
0160     DML_FAIL_WRITEBACK_SCALE_RATIO_TAP,
0161     DML_FAIL_CURSOR_SUPPORT,
0162     DML_FAIL_PITCH_SUPPORT,
0163     DML_FAIL_PTE_BUFFER_SIZE,
0164     DML_FAIL_HOST_VM_IMMEDIATE_FLIP,
0165     DML_FAIL_DSC_INPUT_BPC,
0166     DML_FAIL_PREFETCH_SUPPORT,
0167     DML_FAIL_V_RATIO_PREFETCH,
0168 };
0169
0170 enum writeback_config {
0171     dm_normal,
0172     dm_whole_buffer_for_single_stream_no_interleave,
0173     dm_whole_buffer_for_single_stream_interleave,
0174 };
0175
0176 enum odm_combine_mode {
0177     dm_odm_combine_mode_disabled,
0178     dm_odm_combine_mode_2to1,
0179     dm_odm_combine_mode_4to1,
0180     dm_odm_split_mode_1to2,
0181     dm_odm_mode_mso_1to2,
0182     dm_odm_mode_mso_1to4
0183 };
0184
0185 enum odm_combine_policy {
0186     dm_odm_combine_policy_dal,
0187     dm_odm_combine_policy_none,
0188     dm_odm_combine_policy_2to1,
0189     dm_odm_combine_policy_4to1,
0190     dm_odm_split_policy_1to2,
0191     dm_odm_mso_policy_1to2,
0192     dm_odm_mso_policy_1to4,
0193 };
0194
0195 enum immediate_flip_requirement {
0196     dm_immediate_flip_not_required,
0197     dm_immediate_flip_required,
0198     dm_immediate_flip_opportunistic,
0199 };
0200
0201 enum unbounded_requesting_policy {
0202     dm_unbounded_requesting,
0203     dm_unbounded_requesting_edp_only,
0204     dm_unbounded_requesting_disable
0205 };
0206
0207 enum dm_rotation_angle {
0208     dm_rotation_0,
0209     dm_rotation_90,
0210     dm_rotation_180,
0211     dm_rotation_270,
0212     dm_rotation_0m,
0213     dm_rotation_90m,
0214     dm_rotation_180m,
0215     dm_rotation_270m,
0216 };
0217
0218 enum dm_use_mall_for_pstate_change_mode {
0219     dm_use_mall_pstate_change_disable,
0220     dm_use_mall_pstate_change_full_frame,
0221     dm_use_mall_pstate_change_sub_viewport,
0222     dm_use_mall_pstate_change_phantom_pipe
0223 };
0224
0225 enum dm_use_mall_for_static_screen_mode {
0226     dm_use_mall_static_screen_disable,
0227     dm_use_mall_static_screen_optimize,
0228     dm_use_mall_static_screen_enable,
0229 };
0230
0231 enum dm_output_link_dp_rate {
0232     dm_dp_rate_na,
0233     dm_dp_rate_hbr,
0234     dm_dp_rate_hbr2,
0235     dm_dp_rate_hbr3,
0236     dm_dp_rate_uhbr10,
0237     dm_dp_rate_uhbr13p5,
0238     dm_dp_rate_uhbr20,
0239 };
0240
0241 enum dm_fclock_change_support {
0242     dm_fclock_change_vactive,
0243     dm_fclock_change_vblank,
0244     dm_fclock_change_unsupported,
0245 };
0246
0247 enum dm_prefetch_modes {
0248     dm_prefetch_support_uclk_fclk_and_stutter_if_possible,
0249     dm_prefetch_support_uclk_fclk_and_stutter,
0250     dm_prefetch_support_fclk_and_stutter,
0251     dm_prefetch_support_stutter,
0252     dm_prefetch_support_none,
0253 };
0254 enum dm_output_type {
0255     dm_output_type_unknown,
0256     dm_output_type_dp,
0257     dm_output_type_edp,
0258     dm_output_type_dp2p0,
0259     dm_output_type_hdmi,
0260     dm_output_type_hdmifrl,
0261 };
0262
0263 enum dm_output_rate {
0264     dm_output_rate_unknown,
0265     dm_output_rate_dp_rate_hbr,
0266     dm_output_rate_dp_rate_hbr2,
0267     dm_output_rate_dp_rate_hbr3,
0268     dm_output_rate_dp_rate_uhbr10,
0269     dm_output_rate_dp_rate_uhbr13p5,
0270     dm_output_rate_dp_rate_uhbr20,
0271     dm_output_rate_hdmi_rate_3x3,
0272     dm_output_rate_hdmi_rate_6x3,
0273     dm_output_rate_hdmi_rate_6x4,
0274     dm_output_rate_hdmi_rate_8x4,
0275     dm_output_rate_hdmi_rate_10x4,
0276     dm_output_rate_hdmi_rate_12x4,
0277 };
0278 #endif