dml/dcn32/dcn32_fpu.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright 2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: AMD
0024  *
0025  */
0026
0027 #ifndef __DCN32_FPU_H__
0028 #define __DCN32_FPU_H__
0029
0030 #include "clk_mgr_internal.h"
0031
0032 #define DCN3_2_DEFAULT_DET_SIZE 256
0033 #define DCN3_2_MAX_DET_SIZE 1152
0034 #define DCN3_2_MIN_DET_SIZE 128
0035 #define DCN3_2_MIN_COMPBUF_SIZE_KB 128
0036
0037 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr);
0038
0039 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
0040                           struct dc_state *context,
0041                           display_e2e_pipe_params_st *pipes,
0042                           int pipe_cnt);
0043
0044 bool dcn32_predict_pipe_split(struct dc_state *context,
0045                   display_pipe_params_st pipe,
0046                   int index);
0047
0048 void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table,
0049                     unsigned int *num_entries,
0050                     struct _vcs_dpi_voltage_scaling_st *entry);
0051
0052 void dcn32_set_phantom_stream_timing(struct dc *dc,
0053                      struct dc_state *context,
0054                      struct pipe_ctx *ref_pipe,
0055                      struct dc_stream_state *phantom_stream,
0056                      display_e2e_pipe_params_st *pipes,
0057                      unsigned int pipe_cnt,
0058                      unsigned int dc_pipe_idx);
0059
0060 bool dcn32_internal_validate_bw(struct dc *dc,
0061                 struct dc_state *context,
0062                 display_e2e_pipe_params_st *pipes,
0063                 int *pipe_cnt_out,
0064                 int *vlevel_out,
0065                 bool fast_validate);
0066
0067 void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
0068                 display_e2e_pipe_params_st *pipes,
0069                 int pipe_cnt,
0070                 int vlevel);
0071
0072 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
0073
0074 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
0075                                 struct dc_state *context,
0076                                 display_e2e_pipe_params_st *pipes,
0077                                 int pipe_cnt,
0078                                 int vlevel);
0079
0080 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params);
0081
0082 #endif