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0001 /*
0002  * Copyright 2019-2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "resource.h"
0027 #include "clk_mgr.h"
0028 #include "dcn31/dcn31_resource.h"
0029 #include "dcn315/dcn315_resource.h"
0030 #include "dcn316/dcn316_resource.h"
0031 
0032 #include "dml/dcn20/dcn20_fpu.h"
0033 #include "dcn31_fpu.h"
0034 
0035 /**
0036  * DOC: DCN31x FPU manipulation Overview
0037  *
0038  * The DCN architecture relies on FPU operations, which require special
0039  * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we
0040  * want to avoid spreading FPU access across multiple files. With this idea in
0041  * mind, this file aims to centralize all DCN3.1.x functions that require FPU
0042  * access in a single place. Code in this file follows the following code
0043  * pattern:
0044  *
0045  * 1. Functions that use FPU operations should be isolated in static functions.
0046  * 2. The FPU functions should have the noinline attribute to ensure anything
0047  *    that deals with FP register is contained within this call.
0048  * 3. All function that needs to be accessed outside this file requires a
0049  *    public interface that not uses any FPU reference.
0050  * 4. Developers **must not** use DC_FP_START/END in this file, but they need
0051  *    to ensure that the caller invokes it before access any function available
0052  *    in this file. For this reason, public functions in this file must invoke
0053  *    dc_assert_fp_enabled();
0054  */
0055 
0056 struct _vcs_dpi_ip_params_st dcn3_1_ip = {
0057     .gpuvm_enable = 1,
0058     .gpuvm_max_page_table_levels = 1,
0059     .hostvm_enable = 1,
0060     .hostvm_max_page_table_levels = 2,
0061     .rob_buffer_size_kbytes = 64,
0062     .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE,
0063     .config_return_buffer_size_in_kbytes = 1792,
0064     .compressed_buffer_segment_size_in_kbytes = 64,
0065     .meta_fifo_size_in_kentries = 32,
0066     .zero_size_buffer_entries = 512,
0067     .compbuf_reserved_space_64b = 256,
0068     .compbuf_reserved_space_zs = 64,
0069     .dpp_output_buffer_pixels = 2560,
0070     .opp_output_buffer_lines = 1,
0071     .pixel_chunk_size_kbytes = 8,
0072     .meta_chunk_size_kbytes = 2,
0073     .min_meta_chunk_size_bytes = 256,
0074     .writeback_chunk_size_kbytes = 8,
0075     .ptoi_supported = false,
0076     .num_dsc = 3,
0077     .maximum_dsc_bits_per_component = 10,
0078     .dsc422_native_support = false,
0079     .is_line_buffer_bpp_fixed = true,
0080     .line_buffer_fixed_bpp = 48,
0081     .line_buffer_size_bits = 789504,
0082     .max_line_buffer_lines = 12,
0083     .writeback_interface_buffer_size_kbytes = 90,
0084     .max_num_dpp = 4,
0085     .max_num_otg = 4,
0086     .max_num_hdmi_frl_outputs = 1,
0087     .max_num_wb = 1,
0088     .max_dchub_pscl_bw_pix_per_clk = 4,
0089     .max_pscl_lb_bw_pix_per_clk = 2,
0090     .max_lb_vscl_bw_pix_per_clk = 4,
0091     .max_vscl_hscl_bw_pix_per_clk = 4,
0092     .max_hscl_ratio = 6,
0093     .max_vscl_ratio = 6,
0094     .max_hscl_taps = 8,
0095     .max_vscl_taps = 8,
0096     .dpte_buffer_size_in_pte_reqs_luma = 64,
0097     .dpte_buffer_size_in_pte_reqs_chroma = 34,
0098     .dispclk_ramp_margin_percent = 1,
0099     .max_inter_dcn_tile_repeaters = 8,
0100     .cursor_buffer_size = 16,
0101     .cursor_chunk_size = 2,
0102     .writeback_line_buffer_buffer_size = 0,
0103     .writeback_min_hscl_ratio = 1,
0104     .writeback_min_vscl_ratio = 1,
0105     .writeback_max_hscl_ratio = 1,
0106     .writeback_max_vscl_ratio = 1,
0107     .writeback_max_hscl_taps = 1,
0108     .writeback_max_vscl_taps = 1,
0109     .dppclk_delay_subtotal = 46,
0110     .dppclk_delay_scl = 50,
0111     .dppclk_delay_scl_lb_only = 16,
0112     .dppclk_delay_cnvc_formatter = 27,
0113     .dppclk_delay_cnvc_cursor = 6,
0114     .dispclk_delay_subtotal = 119,
0115     .dynamic_metadata_vm_enabled = false,
0116     .odm_combine_4to1_supported = false,
0117     .dcc_supported = true,
0118 };
0119 
0120 static struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
0121         /*TODO: correct dispclk/dppclk voltage level determination*/
0122     .clock_limits = {
0123         {
0124             .state = 0,
0125             .dispclk_mhz = 1200.0,
0126             .dppclk_mhz = 1200.0,
0127             .phyclk_mhz = 600.0,
0128             .phyclk_d18_mhz = 667.0,
0129             .dscclk_mhz = 186.0,
0130             .dtbclk_mhz = 625.0,
0131         },
0132         {
0133             .state = 1,
0134             .dispclk_mhz = 1200.0,
0135             .dppclk_mhz = 1200.0,
0136             .phyclk_mhz = 810.0,
0137             .phyclk_d18_mhz = 667.0,
0138             .dscclk_mhz = 209.0,
0139             .dtbclk_mhz = 625.0,
0140         },
0141         {
0142             .state = 2,
0143             .dispclk_mhz = 1200.0,
0144             .dppclk_mhz = 1200.0,
0145             .phyclk_mhz = 810.0,
0146             .phyclk_d18_mhz = 667.0,
0147             .dscclk_mhz = 209.0,
0148             .dtbclk_mhz = 625.0,
0149         },
0150         {
0151             .state = 3,
0152             .dispclk_mhz = 1200.0,
0153             .dppclk_mhz = 1200.0,
0154             .phyclk_mhz = 810.0,
0155             .phyclk_d18_mhz = 667.0,
0156             .dscclk_mhz = 371.0,
0157             .dtbclk_mhz = 625.0,
0158         },
0159         {
0160             .state = 4,
0161             .dispclk_mhz = 1200.0,
0162             .dppclk_mhz = 1200.0,
0163             .phyclk_mhz = 810.0,
0164             .phyclk_d18_mhz = 667.0,
0165             .dscclk_mhz = 417.0,
0166             .dtbclk_mhz = 625.0,
0167         },
0168     },
0169     .num_states = 5,
0170     .sr_exit_time_us = 9.0,
0171     .sr_enter_plus_exit_time_us = 11.0,
0172     .sr_exit_z8_time_us = 442.0,
0173     .sr_enter_plus_exit_z8_time_us = 560.0,
0174     .writeback_latency_us = 12.0,
0175     .dram_channel_width_bytes = 4,
0176     .round_trip_ping_latency_dcfclk_cycles = 106,
0177     .urgent_latency_pixel_data_only_us = 4.0,
0178     .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
0179     .urgent_latency_vm_data_only_us = 4.0,
0180     .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
0181     .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
0182     .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
0183     .pct_ideal_sdp_bw_after_urgent = 80.0,
0184     .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
0185     .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
0186     .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
0187     .max_avg_sdp_bw_use_normal_percent = 60.0,
0188     .max_avg_dram_bw_use_normal_percent = 60.0,
0189     .fabric_datapath_to_dcn_data_return_bytes = 32,
0190     .return_bus_width_bytes = 64,
0191     .downspread_percent = 0.38,
0192     .dcn_downspread_percent = 0.5,
0193     .gpuvm_min_page_size_bytes = 4096,
0194     .hostvm_min_page_size_bytes = 4096,
0195     .do_urgent_latency_adjustment = false,
0196     .urgent_latency_adjustment_fabric_clock_component_us = 0,
0197     .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
0198 };
0199 
0200 struct _vcs_dpi_ip_params_st dcn3_15_ip = {
0201     .gpuvm_enable = 1,
0202     .gpuvm_max_page_table_levels = 1,
0203     .hostvm_enable = 1,
0204     .hostvm_max_page_table_levels = 2,
0205     .rob_buffer_size_kbytes = 64,
0206     .det_buffer_size_kbytes = DCN3_15_DEFAULT_DET_SIZE,
0207     .min_comp_buffer_size_kbytes = 64,
0208     .config_return_buffer_size_in_kbytes = 1024,
0209     .compressed_buffer_segment_size_in_kbytes = 64,
0210     .meta_fifo_size_in_kentries = 32,
0211     .zero_size_buffer_entries = 512,
0212     .compbuf_reserved_space_64b = 256,
0213     .compbuf_reserved_space_zs = 64,
0214     .dpp_output_buffer_pixels = 2560,
0215     .opp_output_buffer_lines = 1,
0216     .pixel_chunk_size_kbytes = 8,
0217     .meta_chunk_size_kbytes = 2,
0218     .min_meta_chunk_size_bytes = 256,
0219     .writeback_chunk_size_kbytes = 8,
0220     .ptoi_supported = false,
0221     .num_dsc = 3,
0222     .maximum_dsc_bits_per_component = 10,
0223     .dsc422_native_support = false,
0224     .is_line_buffer_bpp_fixed = true,
0225     .line_buffer_fixed_bpp = 49,
0226     .line_buffer_size_bits = 789504,
0227     .max_line_buffer_lines = 12,
0228     .writeback_interface_buffer_size_kbytes = 90,
0229     .max_num_dpp = 4,
0230     .max_num_otg = 4,
0231     .max_num_hdmi_frl_outputs = 1,
0232     .max_num_wb = 1,
0233     .max_dchub_pscl_bw_pix_per_clk = 4,
0234     .max_pscl_lb_bw_pix_per_clk = 2,
0235     .max_lb_vscl_bw_pix_per_clk = 4,
0236     .max_vscl_hscl_bw_pix_per_clk = 4,
0237     .max_hscl_ratio = 6,
0238     .max_vscl_ratio = 6,
0239     .max_hscl_taps = 8,
0240     .max_vscl_taps = 8,
0241     .dpte_buffer_size_in_pte_reqs_luma = 64,
0242     .dpte_buffer_size_in_pte_reqs_chroma = 34,
0243     .dispclk_ramp_margin_percent = 1,
0244     .max_inter_dcn_tile_repeaters = 9,
0245     .cursor_buffer_size = 16,
0246     .cursor_chunk_size = 2,
0247     .writeback_line_buffer_buffer_size = 0,
0248     .writeback_min_hscl_ratio = 1,
0249     .writeback_min_vscl_ratio = 1,
0250     .writeback_max_hscl_ratio = 1,
0251     .writeback_max_vscl_ratio = 1,
0252     .writeback_max_hscl_taps = 1,
0253     .writeback_max_vscl_taps = 1,
0254     .dppclk_delay_subtotal = 46,
0255     .dppclk_delay_scl = 50,
0256     .dppclk_delay_scl_lb_only = 16,
0257     .dppclk_delay_cnvc_formatter = 27,
0258     .dppclk_delay_cnvc_cursor = 6,
0259     .dispclk_delay_subtotal = 119,
0260     .dynamic_metadata_vm_enabled = false,
0261     .odm_combine_4to1_supported = false,
0262     .dcc_supported = true,
0263 };
0264 
0265 static struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = {
0266     .sr_exit_time_us = 9.0,
0267     .sr_enter_plus_exit_time_us = 11.0,
0268     .sr_exit_z8_time_us = 50.0,
0269     .sr_enter_plus_exit_z8_time_us = 50.0,
0270     .writeback_latency_us = 12.0,
0271     .dram_channel_width_bytes = 4,
0272     .round_trip_ping_latency_dcfclk_cycles = 106,
0273     .urgent_latency_pixel_data_only_us = 4.0,
0274     .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
0275     .urgent_latency_vm_data_only_us = 4.0,
0276     .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
0277     .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
0278     .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
0279     .pct_ideal_sdp_bw_after_urgent = 80.0,
0280     .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
0281     .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
0282     .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
0283     .max_avg_sdp_bw_use_normal_percent = 60.0,
0284     .max_avg_dram_bw_use_normal_percent = 60.0,
0285     .fabric_datapath_to_dcn_data_return_bytes = 32,
0286     .return_bus_width_bytes = 64,
0287     .downspread_percent = 0.38,
0288     .dcn_downspread_percent = 0.38,
0289     .gpuvm_min_page_size_bytes = 4096,
0290     .hostvm_min_page_size_bytes = 4096,
0291     .do_urgent_latency_adjustment = false,
0292     .urgent_latency_adjustment_fabric_clock_component_us = 0,
0293     .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
0294     .num_chans = 4,
0295 };
0296 
0297 struct _vcs_dpi_ip_params_st dcn3_16_ip = {
0298     .gpuvm_enable = 1,
0299     .gpuvm_max_page_table_levels = 1,
0300     .hostvm_enable = 1,
0301     .hostvm_max_page_table_levels = 2,
0302     .rob_buffer_size_kbytes = 64,
0303     .det_buffer_size_kbytes = DCN3_16_DEFAULT_DET_SIZE,
0304     .min_comp_buffer_size_kbytes = 64,
0305     .config_return_buffer_size_in_kbytes = 1024,
0306     .compressed_buffer_segment_size_in_kbytes = 64,
0307     .meta_fifo_size_in_kentries = 32,
0308     .zero_size_buffer_entries = 512,
0309     .compbuf_reserved_space_64b = 256,
0310     .compbuf_reserved_space_zs = 64,
0311     .dpp_output_buffer_pixels = 2560,
0312     .opp_output_buffer_lines = 1,
0313     .pixel_chunk_size_kbytes = 8,
0314     .meta_chunk_size_kbytes = 2,
0315     .min_meta_chunk_size_bytes = 256,
0316     .writeback_chunk_size_kbytes = 8,
0317     .ptoi_supported = false,
0318     .num_dsc = 3,
0319     .maximum_dsc_bits_per_component = 10,
0320     .dsc422_native_support = false,
0321     .is_line_buffer_bpp_fixed = true,
0322     .line_buffer_fixed_bpp = 48,
0323     .line_buffer_size_bits = 789504,
0324     .max_line_buffer_lines = 12,
0325     .writeback_interface_buffer_size_kbytes = 90,
0326     .max_num_dpp = 4,
0327     .max_num_otg = 4,
0328     .max_num_hdmi_frl_outputs = 1,
0329     .max_num_wb = 1,
0330     .max_dchub_pscl_bw_pix_per_clk = 4,
0331     .max_pscl_lb_bw_pix_per_clk = 2,
0332     .max_lb_vscl_bw_pix_per_clk = 4,
0333     .max_vscl_hscl_bw_pix_per_clk = 4,
0334     .max_hscl_ratio = 6,
0335     .max_vscl_ratio = 6,
0336     .max_hscl_taps = 8,
0337     .max_vscl_taps = 8,
0338     .dpte_buffer_size_in_pte_reqs_luma = 64,
0339     .dpte_buffer_size_in_pte_reqs_chroma = 34,
0340     .dispclk_ramp_margin_percent = 1,
0341     .max_inter_dcn_tile_repeaters = 8,
0342     .cursor_buffer_size = 16,
0343     .cursor_chunk_size = 2,
0344     .writeback_line_buffer_buffer_size = 0,
0345     .writeback_min_hscl_ratio = 1,
0346     .writeback_min_vscl_ratio = 1,
0347     .writeback_max_hscl_ratio = 1,
0348     .writeback_max_vscl_ratio = 1,
0349     .writeback_max_hscl_taps = 1,
0350     .writeback_max_vscl_taps = 1,
0351     .dppclk_delay_subtotal = 46,
0352     .dppclk_delay_scl = 50,
0353     .dppclk_delay_scl_lb_only = 16,
0354     .dppclk_delay_cnvc_formatter = 27,
0355     .dppclk_delay_cnvc_cursor = 6,
0356     .dispclk_delay_subtotal = 119,
0357     .dynamic_metadata_vm_enabled = false,
0358     .odm_combine_4to1_supported = false,
0359     .dcc_supported = true,
0360 };
0361 
0362 static struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = {
0363         /*TODO: correct dispclk/dppclk voltage level determination*/
0364     .clock_limits = {
0365         {
0366             .state = 0,
0367             .dispclk_mhz = 556.0,
0368             .dppclk_mhz = 556.0,
0369             .phyclk_mhz = 600.0,
0370             .phyclk_d18_mhz = 445.0,
0371             .dscclk_mhz = 186.0,
0372             .dtbclk_mhz = 625.0,
0373         },
0374         {
0375             .state = 1,
0376             .dispclk_mhz = 625.0,
0377             .dppclk_mhz = 625.0,
0378             .phyclk_mhz = 810.0,
0379             .phyclk_d18_mhz = 667.0,
0380             .dscclk_mhz = 209.0,
0381             .dtbclk_mhz = 625.0,
0382         },
0383         {
0384             .state = 2,
0385             .dispclk_mhz = 625.0,
0386             .dppclk_mhz = 625.0,
0387             .phyclk_mhz = 810.0,
0388             .phyclk_d18_mhz = 667.0,
0389             .dscclk_mhz = 209.0,
0390             .dtbclk_mhz = 625.0,
0391         },
0392         {
0393             .state = 3,
0394             .dispclk_mhz = 1112.0,
0395             .dppclk_mhz = 1112.0,
0396             .phyclk_mhz = 810.0,
0397             .phyclk_d18_mhz = 667.0,
0398             .dscclk_mhz = 371.0,
0399             .dtbclk_mhz = 625.0,
0400         },
0401         {
0402             .state = 4,
0403             .dispclk_mhz = 1250.0,
0404             .dppclk_mhz = 1250.0,
0405             .phyclk_mhz = 810.0,
0406             .phyclk_d18_mhz = 667.0,
0407             .dscclk_mhz = 417.0,
0408             .dtbclk_mhz = 625.0,
0409         },
0410     },
0411     .num_states = 5,
0412     .sr_exit_time_us = 9.0,
0413     .sr_enter_plus_exit_time_us = 11.0,
0414     .sr_exit_z8_time_us = 442.0,
0415     .sr_enter_plus_exit_z8_time_us = 560.0,
0416     .writeback_latency_us = 12.0,
0417     .dram_channel_width_bytes = 4,
0418     .round_trip_ping_latency_dcfclk_cycles = 106,
0419     .urgent_latency_pixel_data_only_us = 4.0,
0420     .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
0421     .urgent_latency_vm_data_only_us = 4.0,
0422     .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
0423     .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
0424     .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
0425     .pct_ideal_sdp_bw_after_urgent = 80.0,
0426     .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
0427     .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
0428     .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
0429     .max_avg_sdp_bw_use_normal_percent = 60.0,
0430     .max_avg_dram_bw_use_normal_percent = 60.0,
0431     .fabric_datapath_to_dcn_data_return_bytes = 32,
0432     .return_bus_width_bytes = 64,
0433     .downspread_percent = 0.38,
0434     .dcn_downspread_percent = 0.5,
0435     .gpuvm_min_page_size_bytes = 4096,
0436     .hostvm_min_page_size_bytes = 4096,
0437     .do_urgent_latency_adjustment = false,
0438     .urgent_latency_adjustment_fabric_clock_component_us = 0,
0439     .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
0440 };
0441 
0442 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
0443                   int pipe_cnt)
0444 {
0445     dc_assert_fp_enabled();
0446 
0447     pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
0448     pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
0449 }
0450 
0451 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
0452 {
0453     dc_assert_fp_enabled();
0454 
0455     if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
0456         context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
0457         context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
0458         context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
0459     }
0460 }
0461 
0462 void dcn31_calculate_wm_and_dlg_fp(
0463         struct dc *dc, struct dc_state *context,
0464         display_e2e_pipe_params_st *pipes,
0465         int pipe_cnt,
0466         int vlevel)
0467 {
0468     int i, pipe_idx;
0469     double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
0470 
0471     dc_assert_fp_enabled();
0472 
0473     if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
0474         dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
0475 
0476     /* We don't recalculate clocks for 0 pipe configs, which can block
0477      * S0i3 as high clocks will block low power states
0478      * Override any clocks that can block S0i3 to min here
0479      */
0480     if (pipe_cnt == 0) {
0481         context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0
0482         return;
0483     }
0484 
0485     pipes[0].clks_cfg.voltage = vlevel;
0486     pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
0487     pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
0488 
0489 #if 0 // TODO
0490     /* Set B:
0491      * TODO
0492      */
0493     if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
0494         if (vlevel == 0) {
0495             pipes[0].clks_cfg.voltage = 1;
0496             pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
0497         }
0498         context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
0499         context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
0500         context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
0501     }
0502     context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0503     context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0504     context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0505     context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0506     context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0507     context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0508     context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0509     context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0510     context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0511     context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0512 
0513     pipes[0].clks_cfg.voltage = vlevel;
0514     pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
0515 
0516     /* Set C:
0517      * TODO
0518      */
0519     if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
0520         context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us;
0521         context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
0522         context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
0523     }
0524     context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0525     context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0526     context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0527     context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0528     context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0529     context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0530     context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0531     context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0532     context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0533     context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0534 
0535     /* Set D:
0536      * TODO
0537      */
0538     if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
0539         context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
0540         context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
0541         context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
0542     }
0543     context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0544     context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0545     context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0546     context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0547     context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0548     context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0549     context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0550     context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0551     context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0552     context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0553 #endif
0554 
0555     /* Set A:
0556      * All clocks min required
0557      *
0558      * Set A calculated last so that following calculations are based on Set A
0559      */
0560     dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
0561     context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0562     context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0563     context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0564     context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0565     context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0566     context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0567     context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0568     context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0569     context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0570     context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
0571     /* TODO: remove: */
0572     context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
0573     context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
0574     context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
0575     /* end remove*/
0576 
0577     for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
0578         if (!context->res_ctx.pipe_ctx[i].stream)
0579             continue;
0580 
0581         pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
0582         pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
0583 
0584         if (dc->config.forced_clocks || dc->debug.max_disp_clk) {
0585             pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
0586             pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
0587         }
0588         if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
0589             pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
0590         if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
0591             pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
0592 
0593         pipe_idx++;
0594     }
0595 
0596     dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
0597 }
0598 
0599 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
0600 {
0601     struct clk_limit_table *clk_table = &bw_params->clk_table;
0602     unsigned int i, closest_clk_lvl;
0603     int j;
0604 
0605     dc_assert_fp_enabled();
0606 
0607     memcpy(&dcn3_1_soc._clock_tmp, &dcn3_1_soc.clock_limits,
0608            sizeof(dcn3_1_soc.clock_limits));
0609 
0610     // Default clock levels are used for diags, which may lead to overclocking.
0611     if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
0612         int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
0613 
0614         dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
0615         dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
0616         dcn3_1_soc.num_chans = bw_params->num_channels;
0617 
0618         ASSERT(clk_table->num_entries);
0619 
0620         /* Prepass to find max clocks independent of voltage level. */
0621         for (i = 0; i < clk_table->num_entries; ++i) {
0622             if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
0623                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
0624             if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
0625                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
0626         }
0627 
0628         for (i = 0; i < clk_table->num_entries; i++) {
0629             /* loop backwards*/
0630             for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) {
0631                 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
0632                     closest_clk_lvl = j;
0633                     break;
0634                 }
0635             }
0636 
0637             dcn3_1_soc._clock_tmp[i].state = i;
0638 
0639             /* Clocks dependent on voltage level. */
0640             dcn3_1_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
0641             dcn3_1_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
0642             dcn3_1_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
0643             dcn3_1_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
0644 
0645             /* Clocks independent of voltage level. */
0646             dcn3_1_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
0647                 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
0648 
0649             dcn3_1_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
0650                 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
0651 
0652             dcn3_1_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
0653             dcn3_1_soc._clock_tmp[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
0654             dcn3_1_soc._clock_tmp[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
0655             dcn3_1_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
0656             dcn3_1_soc._clock_tmp[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
0657         }
0658         if (clk_table->num_entries) {
0659             dcn3_1_soc.num_states = clk_table->num_entries;
0660         }
0661     }
0662 
0663     memcpy(&dcn3_1_soc.clock_limits, &dcn3_1_soc._clock_tmp,
0664            sizeof(dcn3_1_soc.clock_limits));
0665 
0666     dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
0667     dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
0668 
0669     if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
0670         dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);
0671     else
0672         dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA);
0673 }
0674 
0675 void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
0676 {
0677     struct clk_limit_table *clk_table = &bw_params->clk_table;
0678     int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0;
0679 
0680     dc_assert_fp_enabled();
0681 
0682     dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
0683     dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count;
0684 
0685     if (bw_params->num_channels > 0)
0686         dcn3_15_soc.num_chans = bw_params->num_channels;
0687     if (bw_params->dram_channel_width_bytes > 0)
0688         dcn3_15_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes;
0689 
0690     ASSERT(clk_table->num_entries);
0691 
0692     /* Setup soc to always use max dispclk/dppclk to avoid odm-to-lower-voltage */
0693     for (i = 0; i < clk_table->num_entries; ++i) {
0694         if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
0695             max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
0696         if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
0697             max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
0698     }
0699 
0700     for (i = 0; i < clk_table->num_entries; i++) {
0701         dcn3_15_soc.clock_limits[i].state = i;
0702 
0703         /* Clocks dependent on voltage level. */
0704         dcn3_15_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
0705         dcn3_15_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
0706         dcn3_15_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
0707         dcn3_15_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
0708 
0709         /* These aren't actually read from smu, but rather set in clk_mgr defaults */
0710         dcn3_15_soc.clock_limits[i].dtbclk_mhz = clk_table->entries[i].dtbclk_mhz;
0711         dcn3_15_soc.clock_limits[i].phyclk_d18_mhz = clk_table->entries[i].phyclk_d18_mhz;
0712         dcn3_15_soc.clock_limits[i].phyclk_mhz = clk_table->entries[i].phyclk_mhz;
0713 
0714         /* Clocks independent of voltage level. */
0715         dcn3_15_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
0716         dcn3_15_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
0717         dcn3_15_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3.0;
0718     }
0719     dcn3_15_soc.num_states = clk_table->num_entries;
0720 
0721 
0722     /* Set vco to max_dispclk * 2 to make sure the highest dispclk is always available for dml calcs,
0723      * no impact outside of dml validation
0724      */
0725     dcn3_15_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
0726 
0727     if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
0728         dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31);
0729     else
0730         dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31_FPGA);
0731 }
0732 
0733 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
0734 {
0735     struct clk_limit_table *clk_table = &bw_params->clk_table;
0736     unsigned int i, closest_clk_lvl;
0737     int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
0738     int j;
0739 
0740     dc_assert_fp_enabled();
0741 
0742     memcpy(&dcn3_16_soc._clock_tmp, &dcn3_16_soc.clock_limits,
0743            sizeof(dcn3_16_soc.clock_limits));
0744 
0745     // Default clock levels are used for diags, which may lead to overclocking.
0746     if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
0747 
0748         dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
0749         dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count;
0750         dcn3_16_soc.num_chans = bw_params->num_channels;
0751 
0752         ASSERT(clk_table->num_entries);
0753 
0754         /* Prepass to find max clocks independent of voltage level. */
0755         for (i = 0; i < clk_table->num_entries; ++i) {
0756             if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
0757                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
0758             if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
0759                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
0760         }
0761 
0762         for (i = 0; i < clk_table->num_entries; i++) {
0763             /* loop backwards*/
0764             for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) {
0765                 if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
0766                     closest_clk_lvl = j;
0767                     break;
0768                 }
0769             }
0770             // Ported from DCN315
0771             if (clk_table->num_entries == 1) {
0772                 /*smu gives one DPM level, let's take the highest one*/
0773                 closest_clk_lvl = dcn3_16_soc.num_states - 1;
0774             }
0775 
0776             dcn3_16_soc._clock_tmp[i].state = i;
0777 
0778             /* Clocks dependent on voltage level. */
0779             dcn3_16_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
0780             if (clk_table->num_entries == 1 &&
0781                 dcn3_16_soc._clock_tmp[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
0782                 /*SMU fix not released yet*/
0783                 dcn3_16_soc._clock_tmp[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
0784             }
0785             dcn3_16_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
0786             dcn3_16_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
0787             dcn3_16_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
0788 
0789             /* Clocks independent of voltage level. */
0790             dcn3_16_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
0791                 dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
0792 
0793             dcn3_16_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
0794                 dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
0795 
0796             dcn3_16_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
0797             dcn3_16_soc._clock_tmp[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
0798             dcn3_16_soc._clock_tmp[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
0799             dcn3_16_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
0800             dcn3_16_soc._clock_tmp[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
0801         }
0802         if (clk_table->num_entries) {
0803             dcn3_16_soc.num_states = clk_table->num_entries;
0804         }
0805     }
0806 
0807     memcpy(&dcn3_16_soc.clock_limits, &dcn3_16_soc._clock_tmp,
0808            sizeof(dcn3_16_soc.clock_limits));
0809 
0810     if (max_dispclk_mhz) {
0811         dcn3_16_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
0812         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
0813     }
0814 
0815     if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
0816         dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31);
0817     else
0818         dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31_FPGA);
0819 }
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