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0001 /*
0002  * Copyright 2019-2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 #include "resource.h"
0026 #include "clk_mgr.h"
0027 #include "dcn20/dcn20_resource.h"
0028 #include "dcn303/dcn303_resource.h"
0029 
0030 #include "dml/dcn20/dcn20_fpu.h"
0031 #include "dcn303_fpu.h"
0032 
0033 struct _vcs_dpi_ip_params_st dcn3_03_ip = {
0034         .use_min_dcfclk = 0,
0035         .clamp_min_dcfclk = 0,
0036         .odm_capable = 1,
0037         .gpuvm_enable = 1,
0038         .hostvm_enable = 0,
0039         .gpuvm_max_page_table_levels = 4,
0040         .hostvm_max_page_table_levels = 4,
0041         .hostvm_cached_page_table_levels = 0,
0042         .pte_group_size_bytes = 2048,
0043         .num_dsc = 2,
0044         .rob_buffer_size_kbytes = 184,
0045         .det_buffer_size_kbytes = 184,
0046         .dpte_buffer_size_in_pte_reqs_luma = 64,
0047         .dpte_buffer_size_in_pte_reqs_chroma = 34,
0048         .pde_proc_buffer_size_64k_reqs = 48,
0049         .dpp_output_buffer_pixels = 2560,
0050         .opp_output_buffer_lines = 1,
0051         .pixel_chunk_size_kbytes = 8,
0052         .pte_enable = 1,
0053         .max_page_table_levels = 2,
0054         .pte_chunk_size_kbytes = 2,  // ?
0055         .meta_chunk_size_kbytes = 2,
0056         .writeback_chunk_size_kbytes = 8,
0057         .line_buffer_size_bits = 789504,
0058         .is_line_buffer_bpp_fixed = 0,  // ?
0059         .line_buffer_fixed_bpp = 0,     // ?
0060         .dcc_supported = true,
0061         .writeback_interface_buffer_size_kbytes = 90,
0062         .writeback_line_buffer_buffer_size = 0,
0063         .max_line_buffer_lines = 12,
0064         .writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
0065         .writeback_chroma_buffer_size_kbytes = 8,
0066         .writeback_chroma_line_buffer_width_pixels = 4,
0067         .writeback_max_hscl_ratio = 1,
0068         .writeback_max_vscl_ratio = 1,
0069         .writeback_min_hscl_ratio = 1,
0070         .writeback_min_vscl_ratio = 1,
0071         .writeback_max_hscl_taps = 1,
0072         .writeback_max_vscl_taps = 1,
0073         .writeback_line_buffer_luma_buffer_size = 0,
0074         .writeback_line_buffer_chroma_buffer_size = 14643,
0075         .cursor_buffer_size = 8,
0076         .cursor_chunk_size = 2,
0077         .max_num_otg = 2,
0078         .max_num_dpp = 2,
0079         .max_num_wb = 1,
0080         .max_dchub_pscl_bw_pix_per_clk = 4,
0081         .max_pscl_lb_bw_pix_per_clk = 2,
0082         .max_lb_vscl_bw_pix_per_clk = 4,
0083         .max_vscl_hscl_bw_pix_per_clk = 4,
0084         .max_hscl_ratio = 6,
0085         .max_vscl_ratio = 6,
0086         .hscl_mults = 4,
0087         .vscl_mults = 4,
0088         .max_hscl_taps = 8,
0089         .max_vscl_taps = 8,
0090         .dispclk_ramp_margin_percent = 1,
0091         .underscan_factor = 1.11,
0092         .min_vblank_lines = 32,
0093         .dppclk_delay_subtotal = 46,
0094         .dynamic_metadata_vm_enabled = true,
0095         .dppclk_delay_scl_lb_only = 16,
0096         .dppclk_delay_scl = 50,
0097         .dppclk_delay_cnvc_formatter = 27,
0098         .dppclk_delay_cnvc_cursor = 6,
0099         .dispclk_delay_subtotal = 119,
0100         .dcfclk_cstate_latency = 5.2, // SRExitTime
0101         .max_inter_dcn_tile_repeaters = 8,
0102         .max_num_hdmi_frl_outputs = 1,
0103         .odm_combine_4to1_supported = false,
0104 
0105         .xfc_supported = false,
0106         .xfc_fill_bw_overhead_percent = 10.0,
0107         .xfc_fill_constant_bytes = 0,
0108         .gfx7_compat_tiling_supported = 0,
0109         .number_of_cursors = 1,
0110 };
0111 
0112 struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc = {
0113         .clock_limits = {
0114                 {
0115                         .state = 0,
0116                         .dispclk_mhz = 562.0,
0117                         .dppclk_mhz = 300.0,
0118                         .phyclk_mhz = 300.0,
0119                         .phyclk_d18_mhz = 667.0,
0120                         .dscclk_mhz = 405.6,
0121                 },
0122         },
0123 
0124         .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
0125         .num_states = 1,
0126         .sr_exit_time_us = 35.5,
0127         .sr_enter_plus_exit_time_us = 40,
0128         .urgent_latency_us = 4.0,
0129         .urgent_latency_pixel_data_only_us = 4.0,
0130         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
0131         .urgent_latency_vm_data_only_us = 4.0,
0132         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
0133         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
0134         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
0135         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
0136         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
0137         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
0138         .max_avg_sdp_bw_use_normal_percent = 60.0,
0139         .max_avg_dram_bw_use_normal_percent = 40.0,
0140         .writeback_latency_us = 12.0,
0141         .max_request_size_bytes = 256,
0142         .fabric_datapath_to_dcn_data_return_bytes = 64,
0143         .dcn_downspread_percent = 0.5,
0144         .downspread_percent = 0.38,
0145         .dram_page_open_time_ns = 50.0,
0146         .dram_rw_turnaround_time_ns = 17.5,
0147         .dram_return_buffer_per_channel_bytes = 8192,
0148         .round_trip_ping_latency_dcfclk_cycles = 156,
0149         .urgent_out_of_order_return_per_channel_bytes = 4096,
0150         .channel_interleave_bytes = 256,
0151         .num_banks = 8,
0152         .gpuvm_min_page_size_bytes = 4096,
0153         .hostvm_min_page_size_bytes = 4096,
0154         .dram_clock_change_latency_us = 404,
0155         .dummy_pstate_latency_us = 5,
0156         .writeback_dram_clock_change_latency_us = 23.0,
0157         .return_bus_width_bytes = 64,
0158         .dispclk_dppclk_vco_speed_mhz = 3650,
0159         .xfc_bus_transport_time_us = 20,      // ?
0160         .xfc_xbuf_latency_tolerance_us = 4,  // ?
0161         .use_urgent_burst_bw = 1,            // ?
0162         .do_urgent_latency_adjustment = true,
0163         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
0164         .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
0165 };
0166 
0167 static void dcn303_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
0168         unsigned int *optimal_dcfclk,
0169         unsigned int *optimal_fclk)
0170 {
0171     double bw_from_dram, bw_from_dram1, bw_from_dram2;
0172 
0173     bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans *
0174         dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_dram_bw_use_normal_percent / 100);
0175     bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans *
0176         dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100);
0177 
0178     bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
0179 
0180     if (optimal_fclk)
0181         *optimal_fclk = bw_from_dram /
0182         (dcn3_03_soc.fabric_datapath_to_dcn_data_return_bytes *
0183                 (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100));
0184 
0185     if (optimal_dcfclk)
0186         *optimal_dcfclk =  bw_from_dram /
0187         (dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100));
0188 }
0189 
0190 
0191 void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
0192 {
0193     unsigned int i, j;
0194     unsigned int num_states = 0;
0195 
0196     unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
0197     unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
0198     unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
0199     unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
0200 
0201     unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
0202     unsigned int num_dcfclk_sta_targets = 4;
0203     unsigned int num_uclk_states;
0204 
0205     dc_assert_fp_enabled();
0206 
0207     if (dc->ctx->dc_bios->vram_info.num_chans)
0208         dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
0209 
0210     if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
0211         dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
0212 
0213     dcn3_03_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
0214     dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
0215 
0216     if (bw_params->clk_table.entries[0].memclk_mhz) {
0217         int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
0218 
0219         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
0220             if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
0221                 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
0222             if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
0223                 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
0224             if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
0225                 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
0226             if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
0227                 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
0228         }
0229         if (!max_dcfclk_mhz)
0230             max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz;
0231         if (!max_dispclk_mhz)
0232             max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz;
0233         if (!max_dppclk_mhz)
0234             max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz;
0235         if (!max_phyclk_mhz)
0236             max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz;
0237 
0238         if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
0239             dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
0240             num_dcfclk_sta_targets++;
0241         } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
0242             for (i = 0; i < num_dcfclk_sta_targets; i++) {
0243                 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
0244                     dcfclk_sta_targets[i] = max_dcfclk_mhz;
0245                     break;
0246                 }
0247             }
0248             /* Update size of array since we "removed" duplicates */
0249             num_dcfclk_sta_targets = i + 1;
0250         }
0251 
0252         num_uclk_states = bw_params->clk_table.num_entries;
0253 
0254         /* Calculate optimal dcfclk for each uclk */
0255         for (i = 0; i < num_uclk_states; i++) {
0256             dcn303_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
0257                     &optimal_dcfclk_for_uclk[i], NULL);
0258             if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz)
0259                 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
0260         }
0261 
0262         /* Calculate optimal uclk for each dcfclk sta target */
0263         for (i = 0; i < num_dcfclk_sta_targets; i++) {
0264             for (j = 0; j < num_uclk_states; j++) {
0265                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
0266                     optimal_uclk_for_dcfclk_sta_targets[i] =
0267                             bw_params->clk_table.entries[j].memclk_mhz * 16;
0268                     break;
0269                 }
0270             }
0271         }
0272 
0273         i = 0;
0274         j = 0;
0275         /* create the final dcfclk and uclk table */
0276         while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
0277             if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
0278                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
0279                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
0280             } else {
0281                 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
0282                     dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
0283                     dram_speed_mts[num_states++] =
0284                             bw_params->clk_table.entries[j++].memclk_mhz * 16;
0285                 } else {
0286                     j = num_uclk_states;
0287                 }
0288             }
0289         }
0290 
0291         while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
0292             dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
0293             dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
0294         }
0295 
0296         while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
0297                 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
0298             dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
0299             dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
0300         }
0301 
0302         dcn3_03_soc.num_states = num_states;
0303         for (i = 0; i < dcn3_03_soc.num_states; i++) {
0304             dcn3_03_soc.clock_limits[i].state = i;
0305             dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
0306             dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
0307             dcn3_03_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
0308 
0309             /* Fill all states with max values of all other clocks */
0310             dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
0311             dcn3_03_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
0312             dcn3_03_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
0313             /* Populate from bw_params for DTBCLK, SOCCLK */
0314             if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
0315                 dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[i-1].dtbclk_mhz;
0316             else
0317                 dcn3_03_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
0318             if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
0319                 dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz;
0320             else
0321                 dcn3_03_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
0322             /* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */
0323             /* FCLK, PHYCLK_D18, DSCCLK */
0324             dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz;
0325             dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz;
0326         }
0327 
0328         if (dcn3_03_soc.num_chans <= 4) {
0329             for (i = 0; i < dcn3_03_soc.num_states; i++) {
0330                 if (dcn3_03_soc.clock_limits[i].dram_speed_mts > 1700)
0331                     break;
0332 
0333                 if (dcn3_03_soc.clock_limits[i].dram_speed_mts >= 1500) {
0334                     dcn3_03_soc.clock_limits[i].dcfclk_mhz = 100;
0335                     dcn3_03_soc.clock_limits[i].fabricclk_mhz = 100;
0336                 }
0337             }
0338         }
0339 
0340         /* re-init DML with updated bb */
0341         dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
0342         if (dc->current_state)
0343             dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
0344     }
0345 }
0346 
0347 void dcn303_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info)
0348 {
0349     dc_assert_fp_enabled();
0350 
0351     if (bb_info.dram_clock_change_latency_100ns > 0)
0352         dcn3_03_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
0353 
0354     if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
0355         dcn3_03_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
0356 
0357     if (bb_info.dram_sr_exit_latency_100ns > 0)
0358         dcn3_03_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
0359 }
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