Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "resource.h"
0027 #include "clk_mgr.h"
0028 #include "dcn20/dcn20_resource.h"
0029 #include "dcn302/dcn302_resource.h"
0030 
0031 #include "dml/dcn20/dcn20_fpu.h"
0032 #include "dcn302_fpu.h"
0033 
0034 struct _vcs_dpi_ip_params_st dcn3_02_ip = {
0035         .use_min_dcfclk = 0,
0036         .clamp_min_dcfclk = 0,
0037         .odm_capable = 1,
0038         .gpuvm_enable = 1,
0039         .hostvm_enable = 0,
0040         .gpuvm_max_page_table_levels = 4,
0041         .hostvm_max_page_table_levels = 4,
0042         .hostvm_cached_page_table_levels = 0,
0043         .pte_group_size_bytes = 2048,
0044         .num_dsc = 5,
0045         .rob_buffer_size_kbytes = 184,
0046         .det_buffer_size_kbytes = 184,
0047         .dpte_buffer_size_in_pte_reqs_luma = 64,
0048         .dpte_buffer_size_in_pte_reqs_chroma = 34,
0049         .pde_proc_buffer_size_64k_reqs = 48,
0050         .dpp_output_buffer_pixels = 2560,
0051         .opp_output_buffer_lines = 1,
0052         .pixel_chunk_size_kbytes = 8,
0053         .pte_enable = 1,
0054         .max_page_table_levels = 2,
0055         .pte_chunk_size_kbytes = 2,  // ?
0056         .meta_chunk_size_kbytes = 2,
0057         .writeback_chunk_size_kbytes = 8,
0058         .line_buffer_size_bits = 789504,
0059         .is_line_buffer_bpp_fixed = 0,  // ?
0060         .line_buffer_fixed_bpp = 0,     // ?
0061         .dcc_supported = true,
0062         .writeback_interface_buffer_size_kbytes = 90,
0063         .writeback_line_buffer_buffer_size = 0,
0064         .max_line_buffer_lines = 12,
0065         .writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
0066         .writeback_chroma_buffer_size_kbytes = 8,
0067         .writeback_chroma_line_buffer_width_pixels = 4,
0068         .writeback_max_hscl_ratio = 1,
0069         .writeback_max_vscl_ratio = 1,
0070         .writeback_min_hscl_ratio = 1,
0071         .writeback_min_vscl_ratio = 1,
0072         .writeback_max_hscl_taps = 1,
0073         .writeback_max_vscl_taps = 1,
0074         .writeback_line_buffer_luma_buffer_size = 0,
0075         .writeback_line_buffer_chroma_buffer_size = 14643,
0076         .cursor_buffer_size = 8,
0077         .cursor_chunk_size = 2,
0078         .max_num_otg = 5,
0079         .max_num_dpp = 5,
0080         .max_num_wb = 1,
0081         .max_dchub_pscl_bw_pix_per_clk = 4,
0082         .max_pscl_lb_bw_pix_per_clk = 2,
0083         .max_lb_vscl_bw_pix_per_clk = 4,
0084         .max_vscl_hscl_bw_pix_per_clk = 4,
0085         .max_hscl_ratio = 6,
0086         .max_vscl_ratio = 6,
0087         .hscl_mults = 4,
0088         .vscl_mults = 4,
0089         .max_hscl_taps = 8,
0090         .max_vscl_taps = 8,
0091         .dispclk_ramp_margin_percent = 1,
0092         .underscan_factor = 1.11,
0093         .min_vblank_lines = 32,
0094         .dppclk_delay_subtotal = 46,
0095         .dynamic_metadata_vm_enabled = true,
0096         .dppclk_delay_scl_lb_only = 16,
0097         .dppclk_delay_scl = 50,
0098         .dppclk_delay_cnvc_formatter = 27,
0099         .dppclk_delay_cnvc_cursor = 6,
0100         .dispclk_delay_subtotal = 119,
0101         .dcfclk_cstate_latency = 5.2, // SRExitTime
0102         .max_inter_dcn_tile_repeaters = 8,
0103         .max_num_hdmi_frl_outputs = 1,
0104         .odm_combine_4to1_supported = true,
0105 
0106         .xfc_supported = false,
0107         .xfc_fill_bw_overhead_percent = 10.0,
0108         .xfc_fill_constant_bytes = 0,
0109         .gfx7_compat_tiling_supported = 0,
0110         .number_of_cursors = 1,
0111 };
0112 
0113 struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = {
0114         .clock_limits = {
0115                 {
0116                         .state = 0,
0117                         .dispclk_mhz = 562.0,
0118                         .dppclk_mhz = 300.0,
0119                         .phyclk_mhz = 300.0,
0120                         .phyclk_d18_mhz = 667.0,
0121                         .dscclk_mhz = 405.6,
0122                 },
0123         },
0124 
0125         .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
0126         .num_states = 1,
0127         .sr_exit_time_us = 26.5,
0128         .sr_enter_plus_exit_time_us = 31,
0129         .urgent_latency_us = 4.0,
0130         .urgent_latency_pixel_data_only_us = 4.0,
0131         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
0132         .urgent_latency_vm_data_only_us = 4.0,
0133         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
0134         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
0135         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
0136         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
0137         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
0138         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
0139         .max_avg_sdp_bw_use_normal_percent = 60.0,
0140         .max_avg_dram_bw_use_normal_percent = 40.0,
0141         .writeback_latency_us = 12.0,
0142         .max_request_size_bytes = 256,
0143         .fabric_datapath_to_dcn_data_return_bytes = 64,
0144         .dcn_downspread_percent = 0.5,
0145         .downspread_percent = 0.38,
0146         .dram_page_open_time_ns = 50.0,
0147         .dram_rw_turnaround_time_ns = 17.5,
0148         .dram_return_buffer_per_channel_bytes = 8192,
0149         .round_trip_ping_latency_dcfclk_cycles = 156,
0150         .urgent_out_of_order_return_per_channel_bytes = 4096,
0151         .channel_interleave_bytes = 256,
0152         .num_banks = 8,
0153         .gpuvm_min_page_size_bytes = 4096,
0154         .hostvm_min_page_size_bytes = 4096,
0155         .dram_clock_change_latency_us = 404,
0156         .dummy_pstate_latency_us = 5,
0157         .writeback_dram_clock_change_latency_us = 23.0,
0158         .return_bus_width_bytes = 64,
0159         .dispclk_dppclk_vco_speed_mhz = 3650,
0160         .xfc_bus_transport_time_us = 20,      // ?
0161         .xfc_xbuf_latency_tolerance_us = 4,  // ?
0162         .use_urgent_burst_bw = 1,            // ?
0163         .do_urgent_latency_adjustment = true,
0164         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
0165         .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
0166 };
0167 
0168 static void dcn302_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
0169     unsigned int *optimal_dcfclk,
0170     unsigned int *optimal_fclk)
0171 {
0172 
0173             double bw_from_dram, bw_from_dram1, bw_from_dram2;
0174 
0175             bw_from_dram1 = uclk_mts * dcn3_02_soc.num_chans *
0176                 dcn3_02_soc.dram_channel_width_bytes *
0177                 (dcn3_02_soc.max_avg_dram_bw_use_normal_percent / 100);
0178             bw_from_dram2 = uclk_mts * dcn3_02_soc.num_chans *
0179                 dcn3_02_soc.dram_channel_width_bytes *
0180                 (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100);
0181 
0182             bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
0183 
0184             if (optimal_fclk)
0185                 *optimal_fclk = bw_from_dram /
0186                 (dcn3_02_soc.fabric_datapath_to_dcn_data_return_bytes *
0187                  (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100));
0188 
0189             if (optimal_dcfclk)
0190                 *optimal_dcfclk =  bw_from_dram /
0191                 (dcn3_02_soc.return_bus_width_bytes *
0192                  (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100));
0193 }
0194 
0195 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
0196 {
0197     unsigned int i, j;
0198     unsigned int num_states = 0;
0199 
0200     unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
0201     unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
0202     unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
0203     unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
0204 
0205     unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
0206     unsigned int num_dcfclk_sta_targets = 4;
0207     unsigned int num_uclk_states;
0208 
0209     dc_assert_fp_enabled();
0210 
0211     if (dc->ctx->dc_bios->vram_info.num_chans)
0212         dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
0213 
0214     if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
0215         dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
0216 
0217     dcn3_02_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
0218     dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
0219 
0220     if (bw_params->clk_table.entries[0].memclk_mhz) {
0221         int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
0222 
0223         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
0224             if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
0225                 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
0226             if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
0227                 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
0228             if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
0229                 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
0230             if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
0231                 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
0232         }
0233         if (!max_dcfclk_mhz)
0234             max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz;
0235         if (!max_dispclk_mhz)
0236             max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz;
0237         if (!max_dppclk_mhz)
0238             max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz;
0239         if (!max_phyclk_mhz)
0240             max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz;
0241 
0242         if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
0243             /* If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array */
0244             dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
0245             num_dcfclk_sta_targets++;
0246         } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
0247             /* If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates */
0248             for (i = 0; i < num_dcfclk_sta_targets; i++) {
0249                 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
0250                     dcfclk_sta_targets[i] = max_dcfclk_mhz;
0251                     break;
0252                 }
0253             }
0254             /* Update size of array since we "removed" duplicates */
0255             num_dcfclk_sta_targets = i + 1;
0256         }
0257 
0258         num_uclk_states = bw_params->clk_table.num_entries;
0259 
0260         /* Calculate optimal dcfclk for each uclk */
0261         for (i = 0; i < num_uclk_states; i++) {
0262             dcn302_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
0263                     &optimal_dcfclk_for_uclk[i], NULL);
0264             if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz)
0265                 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
0266         }
0267 
0268         /* Calculate optimal uclk for each dcfclk sta target */
0269         for (i = 0; i < num_dcfclk_sta_targets; i++) {
0270             for (j = 0; j < num_uclk_states; j++) {
0271                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
0272                     optimal_uclk_for_dcfclk_sta_targets[i] =
0273                             bw_params->clk_table.entries[j].memclk_mhz * 16;
0274                     break;
0275                 }
0276             }
0277         }
0278 
0279         i = 0;
0280         j = 0;
0281         /* create the final dcfclk and uclk table */
0282         while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
0283             if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
0284                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
0285                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
0286             } else {
0287                 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
0288                     dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
0289                     dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
0290                 } else {
0291                     j = num_uclk_states;
0292                 }
0293             }
0294         }
0295 
0296         while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
0297             dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
0298             dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
0299         }
0300 
0301         while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
0302                 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
0303             dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
0304             dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
0305         }
0306 
0307         dcn3_02_soc.num_states = num_states;
0308         for (i = 0; i < dcn3_02_soc.num_states; i++) {
0309             dcn3_02_soc.clock_limits[i].state = i;
0310             dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
0311             dcn3_02_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
0312             dcn3_02_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
0313 
0314             /* Fill all states with max values of all other clocks */
0315             dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
0316             dcn3_02_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
0317             dcn3_02_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
0318             /* Populate from bw_params for DTBCLK, SOCCLK */
0319             if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
0320                 dcn3_02_soc.clock_limits[i].dtbclk_mhz  = dcn3_02_soc.clock_limits[i-1].dtbclk_mhz;
0321             else
0322                 dcn3_02_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
0323             if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
0324                 dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz;
0325             else
0326                 dcn3_02_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
0327             /* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */
0328             /* FCLK, PHYCLK_D18, DSCCLK */
0329             dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz;
0330             dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz;
0331         }
0332         /* re-init DML with updated bb */
0333         dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
0334         if (dc->current_state)
0335             dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
0336     }
0337 }
0338 
0339 void dcn302_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info)
0340 {
0341 
0342             dc_assert_fp_enabled();
0343 
0344             if (bb_info.dram_clock_change_latency_100ns > 0)
0345                 dcn3_02_soc.dram_clock_change_latency_us =
0346                     bb_info.dram_clock_change_latency_100ns * 10;
0347 
0348             if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
0349                 dcn3_02_soc.sr_enter_plus_exit_time_us =
0350                     bb_info.dram_sr_enter_exit_latency_100ns * 10;
0351 
0352             if (bb_info.dram_sr_exit_latency_100ns > 0)
0353                 dcn3_02_soc.sr_exit_time_us =
0354                     bb_info.dram_sr_exit_latency_100ns * 10;
0355 }
0356 
0357
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!