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0001 /*
0002  * Copyright 2019-2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 #include "resource.h"
0026 #include "clk_mgr.h"
0027 #include "dcn20/dcn20_resource.h"
0028 #include "dcn301/dcn301_resource.h"
0029 #include "clk_mgr/dcn301/vg_clk_mgr.h"
0030 
0031 #include "dml/dcn20/dcn20_fpu.h"
0032 #include "dcn301_fpu.h"
0033 
0034 #define TO_DCN301_RES_POOL(pool)\
0035     container_of(pool, struct dcn301_resource_pool, base)
0036 
0037 /* Based on: //vidip/dc/dcn3/doc/architecture/DCN3x_Display_Mode.xlsm#83 */
0038 struct _vcs_dpi_ip_params_st dcn3_01_ip = {
0039     .odm_capable = 1,
0040     .gpuvm_enable = 1,
0041     .hostvm_enable = 1,
0042     .gpuvm_max_page_table_levels = 1,
0043     .hostvm_max_page_table_levels = 2,
0044     .hostvm_cached_page_table_levels = 0,
0045     .pte_group_size_bytes = 2048,
0046     .num_dsc = 3,
0047     .rob_buffer_size_kbytes = 184,
0048     .det_buffer_size_kbytes = 184,
0049     .dpte_buffer_size_in_pte_reqs_luma = 64,
0050     .dpte_buffer_size_in_pte_reqs_chroma = 32,
0051     .pde_proc_buffer_size_64k_reqs = 48,
0052     .dpp_output_buffer_pixels = 2560,
0053     .opp_output_buffer_lines = 1,
0054     .pixel_chunk_size_kbytes = 8,
0055     .meta_chunk_size_kbytes = 2,
0056     .writeback_chunk_size_kbytes = 8,
0057     .line_buffer_size_bits = 789504,
0058     .is_line_buffer_bpp_fixed = 0,  // ?
0059     .line_buffer_fixed_bpp = 48,     // ?
0060     .dcc_supported = true,
0061     .writeback_interface_buffer_size_kbytes = 90,
0062     .writeback_line_buffer_buffer_size = 656640,
0063     .max_line_buffer_lines = 12,
0064     .writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
0065     .writeback_chroma_buffer_size_kbytes = 8,
0066     .writeback_chroma_line_buffer_width_pixels = 4,
0067     .writeback_max_hscl_ratio = 1,
0068     .writeback_max_vscl_ratio = 1,
0069     .writeback_min_hscl_ratio = 1,
0070     .writeback_min_vscl_ratio = 1,
0071     .writeback_max_hscl_taps = 1,
0072     .writeback_max_vscl_taps = 1,
0073     .writeback_line_buffer_luma_buffer_size = 0,
0074     .writeback_line_buffer_chroma_buffer_size = 14643,
0075     .cursor_buffer_size = 8,
0076     .cursor_chunk_size = 2,
0077     .max_num_otg = 4,
0078     .max_num_dpp = 4,
0079     .max_num_wb = 1,
0080     .max_dchub_pscl_bw_pix_per_clk = 4,
0081     .max_pscl_lb_bw_pix_per_clk = 2,
0082     .max_lb_vscl_bw_pix_per_clk = 4,
0083     .max_vscl_hscl_bw_pix_per_clk = 4,
0084     .max_hscl_ratio = 6,
0085     .max_vscl_ratio = 6,
0086     .hscl_mults = 4,
0087     .vscl_mults = 4,
0088     .max_hscl_taps = 8,
0089     .max_vscl_taps = 8,
0090     .dispclk_ramp_margin_percent = 1,
0091     .underscan_factor = 1.11,
0092     .min_vblank_lines = 32,
0093     .dppclk_delay_subtotal = 46,
0094     .dynamic_metadata_vm_enabled = true,
0095     .dppclk_delay_scl_lb_only = 16,
0096     .dppclk_delay_scl = 50,
0097     .dppclk_delay_cnvc_formatter = 27,
0098     .dppclk_delay_cnvc_cursor = 6,
0099     .dispclk_delay_subtotal = 119,
0100     .dcfclk_cstate_latency = 5.2, // SRExitTime
0101     .max_inter_dcn_tile_repeaters = 8,
0102     .max_num_hdmi_frl_outputs = 0,
0103     .odm_combine_4to1_supported = true,
0104 
0105     .xfc_supported = false,
0106     .xfc_fill_bw_overhead_percent = 10.0,
0107     .xfc_fill_constant_bytes = 0,
0108     .gfx7_compat_tiling_supported = 0,
0109     .number_of_cursors = 1,
0110 };
0111 
0112 struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
0113     .clock_limits = {
0114         {
0115             .state = 0,
0116             .dram_speed_mts = 2400.0,
0117             .fabricclk_mhz = 600,
0118             .socclk_mhz = 278.0,
0119             .dcfclk_mhz = 400.0,
0120             .dscclk_mhz = 206.0,
0121             .dppclk_mhz = 1015.0,
0122             .dispclk_mhz = 1015.0,
0123             .phyclk_mhz = 600.0,
0124         },
0125 
0126         {
0127             .state = 1,
0128             .dram_speed_mts = 2400.0,
0129             .fabricclk_mhz = 688,
0130             .socclk_mhz = 278.0,
0131             .dcfclk_mhz = 400.0,
0132             .dscclk_mhz = 206.0,
0133             .dppclk_mhz = 1015.0,
0134             .dispclk_mhz = 1015.0,
0135             .phyclk_mhz = 600.0,
0136         },
0137 
0138         {
0139             .state = 2,
0140             .dram_speed_mts = 4267.0,
0141             .fabricclk_mhz = 1067,
0142             .socclk_mhz = 278.0,
0143             .dcfclk_mhz = 608.0,
0144             .dscclk_mhz = 296.0,
0145             .dppclk_mhz = 1015.0,
0146             .dispclk_mhz = 1015.0,
0147             .phyclk_mhz = 810.0,
0148         },
0149 
0150         {
0151             .state = 3,
0152             .dram_speed_mts = 4267.0,
0153             .fabricclk_mhz = 1067,
0154             .socclk_mhz = 715.0,
0155             .dcfclk_mhz = 676.0,
0156             .dscclk_mhz = 338.0,
0157             .dppclk_mhz = 1015.0,
0158             .dispclk_mhz = 1015.0,
0159             .phyclk_mhz = 810.0,
0160         },
0161 
0162         {
0163             .state = 4,
0164             .dram_speed_mts = 4267.0,
0165             .fabricclk_mhz = 1067,
0166             .socclk_mhz = 953.0,
0167             .dcfclk_mhz = 810.0,
0168             .dscclk_mhz = 338.0,
0169             .dppclk_mhz = 1015.0,
0170             .dispclk_mhz = 1015.0,
0171             .phyclk_mhz = 810.0,
0172         },
0173     },
0174 
0175     .sr_exit_time_us = 9.0,
0176     .sr_enter_plus_exit_time_us = 11.0,
0177     .urgent_latency_us = 4.0,
0178     .urgent_latency_pixel_data_only_us = 4.0,
0179     .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
0180     .urgent_latency_vm_data_only_us = 4.0,
0181     .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
0182     .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
0183     .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
0184     .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
0185     .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
0186     .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
0187     .max_avg_sdp_bw_use_normal_percent = 60.0,
0188     .max_avg_dram_bw_use_normal_percent = 60.0,
0189     .writeback_latency_us = 12.0,
0190     .max_request_size_bytes = 256,
0191     .dram_channel_width_bytes = 4,
0192     .fabric_datapath_to_dcn_data_return_bytes = 32,
0193     .dcn_downspread_percent = 0.5,
0194     .downspread_percent = 0.38,
0195     .dram_page_open_time_ns = 50.0,
0196     .dram_rw_turnaround_time_ns = 17.5,
0197     .dram_return_buffer_per_channel_bytes = 8192,
0198     .round_trip_ping_latency_dcfclk_cycles = 191,
0199     .urgent_out_of_order_return_per_channel_bytes = 4096,
0200     .channel_interleave_bytes = 256,
0201     .num_banks = 8,
0202     .num_chans = 4,
0203     .gpuvm_min_page_size_bytes = 4096,
0204     .hostvm_min_page_size_bytes = 4096,
0205     .dram_clock_change_latency_us = 23.84,
0206     .writeback_dram_clock_change_latency_us = 23.0,
0207     .return_bus_width_bytes = 64,
0208     .dispclk_dppclk_vco_speed_mhz = 3550,
0209     .xfc_bus_transport_time_us = 20,      // ?
0210     .xfc_xbuf_latency_tolerance_us = 4,  // ?
0211     .use_urgent_burst_bw = 1,            // ?
0212     .num_states = 5,
0213     .do_urgent_latency_adjustment = false,
0214     .urgent_latency_adjustment_fabric_clock_component_us = 0,
0215     .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
0216 };
0217 
0218 struct wm_table ddr4_wm_table = {
0219     .entries = {
0220         {
0221             .wm_inst = WM_A,
0222             .wm_type = WM_TYPE_PSTATE_CHG,
0223             .pstate_latency_us = 11.72,
0224             .sr_exit_time_us = 6.09,
0225             .sr_enter_plus_exit_time_us = 7.14,
0226             .valid = true,
0227         },
0228         {
0229             .wm_inst = WM_B,
0230             .wm_type = WM_TYPE_PSTATE_CHG,
0231             .pstate_latency_us = 11.72,
0232             .sr_exit_time_us = 10.12,
0233             .sr_enter_plus_exit_time_us = 11.48,
0234             .valid = true,
0235         },
0236         {
0237             .wm_inst = WM_C,
0238             .wm_type = WM_TYPE_PSTATE_CHG,
0239             .pstate_latency_us = 11.72,
0240             .sr_exit_time_us = 10.12,
0241             .sr_enter_plus_exit_time_us = 11.48,
0242             .valid = true,
0243         },
0244         {
0245             .wm_inst = WM_D,
0246             .wm_type = WM_TYPE_PSTATE_CHG,
0247             .pstate_latency_us = 11.72,
0248             .sr_exit_time_us = 10.12,
0249             .sr_enter_plus_exit_time_us = 11.48,
0250             .valid = true,
0251         },
0252     }
0253 };
0254 
0255 struct wm_table lpddr5_wm_table = {
0256     .entries = {
0257         {
0258             .wm_inst = WM_A,
0259             .wm_type = WM_TYPE_PSTATE_CHG,
0260             .pstate_latency_us = 11.65333,
0261             .sr_exit_time_us = 13.5,
0262             .sr_enter_plus_exit_time_us = 16.5,
0263             .valid = true,
0264         },
0265         {
0266             .wm_inst = WM_B,
0267             .wm_type = WM_TYPE_PSTATE_CHG,
0268             .pstate_latency_us = 11.65333,
0269             .sr_exit_time_us = 13.5,
0270             .sr_enter_plus_exit_time_us = 16.5,
0271             .valid = true,
0272         },
0273         {
0274             .wm_inst = WM_C,
0275             .wm_type = WM_TYPE_PSTATE_CHG,
0276             .pstate_latency_us = 11.65333,
0277             .sr_exit_time_us = 13.5,
0278             .sr_enter_plus_exit_time_us = 16.5,
0279             .valid = true,
0280         },
0281         {
0282             .wm_inst = WM_D,
0283             .wm_type = WM_TYPE_PSTATE_CHG,
0284             .pstate_latency_us = 11.65333,
0285             .sr_exit_time_us = 13.5,
0286             .sr_enter_plus_exit_time_us = 16.5,
0287             .valid = true,
0288         },
0289     }
0290 };
0291 
0292 static void calculate_wm_set_for_vlevel(int vlevel,
0293         struct wm_range_table_entry *table_entry,
0294         struct dcn_watermarks *wm_set,
0295         struct display_mode_lib *dml,
0296         display_e2e_pipe_params_st *pipes,
0297         int pipe_cnt)
0298 {
0299     double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
0300 
0301     ASSERT(vlevel < dml->soc.num_states);
0302     /* only pipe 0 is read for voltage and dcf/soc clocks */
0303     pipes[0].clks_cfg.voltage = vlevel;
0304     pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
0305     pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
0306 
0307     dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
0308     dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
0309     dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
0310 
0311     wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
0312     wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
0313     wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
0314     wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
0315     wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
0316     wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
0317     wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
0318     wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
0319     dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
0320 
0321 }
0322 
0323 void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
0324 {
0325     struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);
0326     struct clk_limit_table *clk_table = &bw_params->clk_table;
0327     unsigned int i, closest_clk_lvl;
0328     int j;
0329 
0330     dc_assert_fp_enabled();
0331 
0332     memcpy(&dcn3_01_soc._clock_tmp, &dcn3_01_soc.clock_limits,
0333            sizeof(dcn3_01_soc.clock_limits));
0334 
0335     /* Default clock levels are used for diags, which may lead to overclocking. */
0336     if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
0337         dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
0338         dcn3_01_ip.max_num_dpp = pool->base.pipe_count;
0339         dcn3_01_soc.num_chans = bw_params->num_channels;
0340 
0341         ASSERT(clk_table->num_entries);
0342         for (i = 0; i < clk_table->num_entries; i++) {
0343             /* loop backwards*/
0344             for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) {
0345                 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
0346                     closest_clk_lvl = j;
0347                     break;
0348                 }
0349             }
0350 
0351             dcn3_01_soc._clock_tmp[i].state = i;
0352             dcn3_01_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
0353             dcn3_01_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
0354             dcn3_01_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
0355             dcn3_01_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
0356 
0357             dcn3_01_soc._clock_tmp[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
0358             dcn3_01_soc._clock_tmp[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
0359             dcn3_01_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
0360             dcn3_01_soc._clock_tmp[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
0361             dcn3_01_soc._clock_tmp[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
0362             dcn3_01_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
0363             dcn3_01_soc._clock_tmp[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
0364         }
0365 
0366         if (clk_table->num_entries) {
0367             dcn3_01_soc.num_states = clk_table->num_entries;
0368             /* duplicate last level */
0369             dcn3_01_soc._clock_tmp[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];
0370             dcn3_01_soc._clock_tmp[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;
0371         }
0372     }
0373 
0374     memcpy(&dcn3_01_soc.clock_limits, &dcn3_01_soc._clock_tmp,
0375            sizeof(dcn3_01_soc.clock_limits));
0376 
0377     dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
0378     dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
0379 
0380     dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
0381 }
0382 
0383 void dcn301_fpu_set_wm_ranges(int i,
0384     struct pp_smu_wm_range_sets *ranges,
0385     struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
0386 {
0387     dc_assert_fp_enabled();
0388 
0389     ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
0390     ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
0391 }
0392 
0393 void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info)
0394 {
0395     dc_assert_fp_enabled();
0396 
0397     if (bb_info.dram_clock_change_latency_100ns > 0)
0398         dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
0399 
0400     if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
0401         dcn3_01_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
0402 
0403     if (bb_info.dram_sr_exit_latency_100ns > 0)
0404         dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
0405 }
0406 
0407 void dcn301_calculate_wm_and_dlg_fp(struct dc *dc,
0408         struct dc_state *context,
0409         display_e2e_pipe_params_st *pipes,
0410         int pipe_cnt,
0411         int vlevel_req)
0412 {
0413     int i, pipe_idx;
0414     int vlevel, vlevel_max;
0415     struct wm_range_table_entry *table_entry;
0416     struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
0417 
0418     ASSERT(bw_params);
0419     dc_assert_fp_enabled();
0420 
0421     vlevel_max = bw_params->clk_table.num_entries - 1;
0422 
0423     /* WM Set D */
0424     table_entry = &bw_params->wm_table.entries[WM_D];
0425     if (table_entry->wm_type == WM_TYPE_RETRAINING)
0426         vlevel = 0;
0427     else
0428         vlevel = vlevel_max;
0429     calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
0430                         &context->bw_ctx.dml, pipes, pipe_cnt);
0431     /* WM Set C */
0432     table_entry = &bw_params->wm_table.entries[WM_C];
0433     vlevel = min(max(vlevel_req, 2), vlevel_max);
0434     calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
0435                         &context->bw_ctx.dml, pipes, pipe_cnt);
0436     /* WM Set B */
0437     table_entry = &bw_params->wm_table.entries[WM_B];
0438     vlevel = min(max(vlevel_req, 1), vlevel_max);
0439     calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
0440                         &context->bw_ctx.dml, pipes, pipe_cnt);
0441 
0442     /* WM Set A */
0443     table_entry = &bw_params->wm_table.entries[WM_A];
0444     vlevel = min(vlevel_req, vlevel_max);
0445     calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
0446                         &context->bw_ctx.dml, pipes, pipe_cnt);
0447 
0448     for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
0449         if (!context->res_ctx.pipe_ctx[i].stream)
0450             continue;
0451 
0452         pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
0453         pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
0454 
0455         if (dc->config.forced_clocks) {
0456             pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
0457             pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
0458         }
0459         if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
0460             pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
0461         if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
0462             pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
0463         pipe_idx++;
0464     }
0465 
0466     dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
0467 }
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