dml/dcn30/dcn30_fpu.h

0001 /*
0002  * Copyright 2020-2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DCN30_FPU_H__
0027 #define __DCN30_FPU_H__
0028
0029 #include "core_types.h"
0030 #include "dcn20/dcn20_optc.h"
0031
0032 void optc3_fpu_set_vrr_m_const(struct timing_generator *optc,
0033         double vtotal_avg);
0034
0035 void dcn30_fpu_populate_dml_writeback_from_context(
0036         struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
0037
0038 void dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params,
0039     struct display_mode_lib *dml,
0040     display_e2e_pipe_params_st *pipes,
0041     int pipe_cnt,
0042     int cur_pipe);
0043
0044 void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
0045
0046 void dcn30_fpu_calculate_wm_and_dlg(
0047         struct dc *dc, struct dc_state *context,
0048         display_e2e_pipe_params_st *pipes,
0049         int pipe_cnt,
0050         int vlevel);
0051
0052 void dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc);
0053
0054 void dcn30_fpu_update_max_clk(struct dc_bounding_box_max_clk *dcn30_bb_max_clk);
0055
0056 void dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
0057         unsigned int *optimal_dcfclk,
0058         unsigned int *optimal_fclk);
0059
0060 void dcn30_fpu_update_bw_bounding_box(struct dc *dc,
0061     struct clk_bw_params *bw_params,
0062     struct dc_bounding_box_max_clk *dcn30_bb_max_clk,
0063     unsigned int *dcfclk_mhz,
0064     unsigned int *dram_speed_mts);
0065
0066 int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
0067                                 struct dc_state *context,
0068                                 display_e2e_pipe_params_st *pipes,
0069                                 int pipe_cnt,
0070                                 int vlevel);
0071
0072 void dcn3_fpu_build_wm_range_table(struct clk_mgr *base);
0073
0074 void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip);
0075
0076 #endif /* __DCN30_FPU_H__*/