dml/dcn20/dcn20_fpu.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright 2021 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: AMD
0024  *
0025  */
0026 #include "core_types.h"
0027
0028 #ifndef __DCN20_FPU_H__
0029 #define __DCN20_FPU_H__
0030
0031 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
0032                            struct resource_context *res_ctx,
0033                            display_e2e_pipe_params_st *pipes);
0034
0035 void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params,
0036                  struct dc_state *context,
0037                  display_e2e_pipe_params_st *pipes,
0038                  int pipe_cnt, int i);
0039 void dcn20_calculate_dlg_params(struct dc *dc,
0040                 struct dc_state *context,
0041                 display_e2e_pipe_params_st *pipes,
0042                 int pipe_cnt,
0043                 int vlevel);
0044 int dcn20_populate_dml_pipes_from_context(struct dc *dc,
0045                       struct dc_state *context,
0046                       display_e2e_pipe_params_st *pipes,
0047                       bool fast_validate);
0048 void dcn20_calculate_wm(struct dc *dc,
0049             struct dc_state *context,
0050             display_e2e_pipe_params_st *pipes,
0051             int *out_pipe_cnt,
0052             int *pipe_split_from,
0053             int vlevel,
0054             bool fast_validate);
0055 void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb,
0056               struct pp_smu_nv_clock_table max_clocks);
0057 void dcn20_update_bounding_box(struct dc *dc,
0058                    struct _vcs_dpi_soc_bounding_box_st *bb,
0059                    struct pp_smu_nv_clock_table *max_clocks,
0060                    unsigned int *uclk_states,
0061                    unsigned int num_states);
0062 void dcn20_patch_bounding_box(struct dc *dc,
0063                   struct _vcs_dpi_soc_bounding_box_st *bb);
0064 bool dcn20_validate_bandwidth_fp(struct dc *dc,
0065                  struct dc_state *context,
0066                  bool fast_validate);
0067 void dcn20_fpu_set_wm_ranges(int i,
0068                  struct pp_smu_wm_range_sets *ranges,
0069                  struct _vcs_dpi_soc_bounding_box_st *loaded_bb);
0070 void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,
0071                  int vlevel,
0072                  int max_mpc_comb,
0073                  int pipe_idx,
0074                  bool is_validating_bw);
0075
0076 int dcn21_populate_dml_pipes_from_context(struct dc *dc,
0077                       struct dc_state *context,
0078                       display_e2e_pipe_params_st *pipes,
0079                       bool fast_validate);
0080 bool dcn21_validate_bandwidth_fp(struct dc *dc,
0081                  struct dc_state *context,
0082                  bool fast_validate);
0083 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
0084
0085 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);
0086
0087 void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,
0088                         struct resource_context *res_ctx,
0089                         display_e2e_pipe_params_st *pipes);
0090
0091 #endif /* __DCN20_FPU_H__ */