dml/dcn10/dcn10_fpu.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright 2021 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: AMD
0024  *
0025  */
0026
0027 #include "dcn10/dcn10_resource.h"
0028
0029 #include "dcn10_fpu.h"
0030
0031 /**
0032  * DOC: DCN10 FPU manipulation Overview
0033  *
0034  * The DCN architecture relies on FPU operations, which require special
0035  * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we
0036  * want to avoid spreading FPU access across multiple files. With this idea in
0037  * mind, this file aims to centralize DCN10 functions that require FPU access
0038  * in a single place. Code in this file follows the following code pattern:
0039  *
0040  * 1. Functions that use FPU operations should be isolated in static functions.
0041  * 2. The FPU functions should have the noinline attribute to ensure anything
0042  *    that deals with FP register is contained within this call.
0043  * 3. All function that needs to be accessed outside this file requires a
0044  *    public interface that not uses any FPU reference.
0045  * 4. Developers **must not** use DC_FP_START/END in this file, but they need
0046  *    to ensure that the caller invokes it before access any function available
0047  *    in this file. For this reason, public functions in this file must invoke
0048  *    dc_assert_fp_enabled();
0049  *
0050  * Let's expand a little bit more the idea in the code pattern. To fully
0051  * isolate FPU operations in a single place, we must avoid situations where
0052  * compilers spill FP values to registers due to FP enable in a specific C
0053  * file. Note that even if we isolate all FPU functions in a single file and
0054  * call its interface from other files, the compiler might enable the use of
0055  * FPU before we call DC_FP_START. Nevertheless, it is the programmer's
0056  * responsibility to invoke DC_FP_START/END in the correct place. To highlight
0057  * situations where developers forgot to use the FP protection before calling
0058  * the DC FPU interface functions, we introduce a helper that checks if the
0059  * function is invoked under FP protection. If not, it will trigger a kernel
0060  * warning.
0061  */
0062
0063 struct _vcs_dpi_ip_params_st dcn1_0_ip = {
0064     .rob_buffer_size_kbytes = 64,
0065     .det_buffer_size_kbytes = 164,
0066     .dpte_buffer_size_in_pte_reqs_luma = 42,
0067     .dpp_output_buffer_pixels = 2560,
0068     .opp_output_buffer_lines = 1,
0069     .pixel_chunk_size_kbytes = 8,
0070     .pte_enable = 1,
0071     .pte_chunk_size_kbytes = 2,
0072     .meta_chunk_size_kbytes = 2,
0073     .writeback_chunk_size_kbytes = 2,
0074     .line_buffer_size_bits = 589824,
0075     .max_line_buffer_lines = 12,
0076     .IsLineBufferBppFixed = 0,
0077     .LineBufferFixedBpp = -1,
0078     .writeback_luma_buffer_size_kbytes = 12,
0079     .writeback_chroma_buffer_size_kbytes = 8,
0080     .max_num_dpp = 4,
0081     .max_num_wb = 2,
0082     .max_dchub_pscl_bw_pix_per_clk = 4,
0083     .max_pscl_lb_bw_pix_per_clk = 2,
0084     .max_lb_vscl_bw_pix_per_clk = 4,
0085     .max_vscl_hscl_bw_pix_per_clk = 4,
0086     .max_hscl_ratio = 4,
0087     .max_vscl_ratio = 4,
0088     .hscl_mults = 4,
0089     .vscl_mults = 4,
0090     .max_hscl_taps = 8,
0091     .max_vscl_taps = 8,
0092     .dispclk_ramp_margin_percent = 1,
0093     .underscan_factor = 1.10,
0094     .min_vblank_lines = 14,
0095     .dppclk_delay_subtotal = 90,
0096     .dispclk_delay_subtotal = 42,
0097     .dcfclk_cstate_latency = 10,
0098     .max_inter_dcn_tile_repeaters = 8,
0099     .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,
0100     .bug_forcing_LC_req_same_size_fixed = 0,
0101 };
0102
0103 struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {
0104     .sr_exit_time_us = 9.0,
0105     .sr_enter_plus_exit_time_us = 11.0,
0106     .urgent_latency_us = 4.0,
0107     .writeback_latency_us = 12.0,
0108     .ideal_dram_bw_after_urgent_percent = 80.0,
0109     .max_request_size_bytes = 256,
0110     .downspread_percent = 0.5,
0111     .dram_page_open_time_ns = 50.0,
0112     .dram_rw_turnaround_time_ns = 17.5,
0113     .dram_return_buffer_per_channel_bytes = 8192,
0114     .round_trip_ping_latency_dcfclk_cycles = 128,
0115     .urgent_out_of_order_return_per_channel_bytes = 256,
0116     .channel_interleave_bytes = 256,
0117     .num_banks = 8,
0118     .num_chans = 2,
0119     .vmm_page_size_bytes = 4096,
0120     .dram_clock_change_latency_us = 17.0,
0121     .writeback_dram_clock_change_latency_us = 23.0,
0122     .return_bus_width_bytes = 64,
0123 };