dml/calcs/dcn_calcs.c

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  * Copyright 2019 Raptor Engineering, LLC
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: AMD
0024  *
0025  */
0026
0027 #include "dm_services.h"
0028 #include "dc.h"
0029 #include "dcn_calcs.h"
0030 #include "dcn_calc_auto.h"
0031 #include "dal_asic_id.h"
0032 #include "resource.h"
0033 #include "dcn10/dcn10_resource.h"
0034 #include "dcn10/dcn10_hubbub.h"
0035 #include "dml/dml1_display_rq_dlg_calc.h"
0036
0037 #include "dcn_calc_math.h"
0038
0039 #define DC_LOGGER \
0040     dc->ctx->logger
0041
0042 #define WM_SET_COUNT 4
0043 #define WM_A 0
0044 #define WM_B 1
0045 #define WM_C 2
0046 #define WM_D 3
0047
0048 /*
0049  * NOTE:
0050  *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
0051  *
0052  * It doesn't adhere to Linux kernel style and sometimes will do things in odd
0053  * ways. Unless there is something clearly wrong with it the code should
0054  * remain as-is as it provides us with a guarantee from HW that it is correct.
0055  */
0056
0057 /* Defaults from spreadsheet rev#247.
0058  * RV2 delta: dram_clock_change_latency, max_num_dpp
0059  */
0060 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
0061         /* latencies */
0062         .sr_exit_time = 17, /*us*/
0063         .sr_enter_plus_exit_time = 19, /*us*/
0064         .urgent_latency = 4, /*us*/
0065         .dram_clock_change_latency = 17, /*us*/
0066         .write_back_latency = 12, /*us*/
0067         .percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
0068
0069         /* below default clocks derived from STA target base on
0070          * slow-slow corner + 10% margin with voltages aligned to FCLK.
0071          *
0072          * Use these value if fused value doesn't make sense as earlier
0073          * part don't have correct value fused */
0074         /* default DCF CLK DPM on RV*/
0075         .dcfclkv_max0p9 = 655,  /* MHz, = 3600/5.5 */
0076         .dcfclkv_nom0p8 = 626,  /* MHz, = 3600/5.75 */
0077         .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
0078         .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
0079
0080         /* default DISP CLK voltage state on RV */
0081         .max_dispclk_vmax0p9 = 1108,    /* MHz, = 3600/3.25 */
0082         .max_dispclk_vnom0p8 = 1029,    /* MHz, = 3600/3.5 */
0083         .max_dispclk_vmid0p72 = 960,    /* MHz, = 3600/3.75 */
0084         .max_dispclk_vmin0p65 = 626,    /* MHz, = 3600/5.75 */
0085
0086         /* default DPP CLK voltage state on RV */
0087         .max_dppclk_vmax0p9 = 720,  /* MHz, = 3600/5 */
0088         .max_dppclk_vnom0p8 = 686,  /* MHz, = 3600/5.25 */
0089         .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75 */
0090         .max_dppclk_vmin0p65 = 400, /* MHz, = 3600/9 */
0091
0092         /* default PHY CLK voltage state on RV */
0093         .phyclkv_max0p9 = 900, /*MHz*/
0094         .phyclkv_nom0p8 = 847, /*MHz*/
0095         .phyclkv_mid0p72 = 800, /*MHz*/
0096         .phyclkv_min0p65 = 600, /*MHz*/
0097
0098         /* BW depend on FCLK, MCLK, # of channels */
0099         /* dual channel BW */
0100         .fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
0101         .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/
0102         .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/
0103         .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
0104         /* single channel BW
0105         .fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
0106         .fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
0107         .fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
0108         .fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
0109         */
0110
0111         .number_of_channels = 2,
0112
0113         .socclk = 208, /*MHz*/
0114         .downspreading = 0.5f, /*%*/
0115         .round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
0116         .urgent_out_of_order_return_per_channel = 256, /*bytes*/
0117         .vmm_page_size = 4096, /*bytes*/
0118         .return_bus_width = 64, /*bytes*/
0119         .max_request_size = 256, /*bytes*/
0120
0121         /* Depends on user class (client vs embedded, workstation, etc) */
0122         .percent_disp_bw_limit = 0.3f /*%*/
0123 };
0124
0125 const struct dcn_ip_params dcn10_ip_defaults = {
0126         .rob_buffer_size_in_kbyte = 64,
0127         .det_buffer_size_in_kbyte = 164,
0128         .dpp_output_buffer_pixels = 2560,
0129         .opp_output_buffer_lines = 1,
0130         .pixel_chunk_size_in_kbyte = 8,
0131         .pte_enable = dcn_bw_yes,
0132         .pte_chunk_size = 2, /*kbytes*/
0133         .meta_chunk_size = 2, /*kbytes*/
0134         .writeback_chunk_size = 2, /*kbytes*/
0135         .odm_capability = dcn_bw_no,
0136         .dsc_capability = dcn_bw_no,
0137         .line_buffer_size = 589824, /*bit*/
0138         .max_line_buffer_lines = 12,
0139         .is_line_buffer_bpp_fixed = dcn_bw_no,
0140         .line_buffer_fixed_bpp = dcn_bw_na,
0141         .writeback_luma_buffer_size = 12, /*kbytes*/
0142         .writeback_chroma_buffer_size = 8, /*kbytes*/
0143         .max_num_dpp = 4,
0144         .max_num_writeback = 2,
0145         .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
0146         .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
0147         .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
0148         .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
0149         .max_hscl_ratio = 4,
0150         .max_vscl_ratio = 4,
0151         .max_hscl_taps = 8,
0152         .max_vscl_taps = 8,
0153         .pte_buffer_size_in_requests = 42,
0154         .dispclk_ramping_margin = 1, /*%*/
0155         .under_scan_factor = 1.11f,
0156         .max_inter_dcn_tile_repeaters = 8,
0157         .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no,
0158         .bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no,
0159         .dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/
0160 };
0161
0162 static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
0163 {
0164     switch (sw_mode) {
0165     case DC_SW_LINEAR:
0166         return dcn_bw_sw_linear;
0167     case DC_SW_4KB_S:
0168         return dcn_bw_sw_4_kb_s;
0169     case DC_SW_4KB_D:
0170         return dcn_bw_sw_4_kb_d;
0171     case DC_SW_64KB_S:
0172         return dcn_bw_sw_64_kb_s;
0173     case DC_SW_64KB_D:
0174         return dcn_bw_sw_64_kb_d;
0175     case DC_SW_VAR_S:
0176         return dcn_bw_sw_var_s;
0177     case DC_SW_VAR_D:
0178         return dcn_bw_sw_var_d;
0179     case DC_SW_64KB_S_T:
0180         return dcn_bw_sw_64_kb_s_t;
0181     case DC_SW_64KB_D_T:
0182         return dcn_bw_sw_64_kb_d_t;
0183     case DC_SW_4KB_S_X:
0184         return dcn_bw_sw_4_kb_s_x;
0185     case DC_SW_4KB_D_X:
0186         return dcn_bw_sw_4_kb_d_x;
0187     case DC_SW_64KB_S_X:
0188         return dcn_bw_sw_64_kb_s_x;
0189     case DC_SW_64KB_D_X:
0190         return dcn_bw_sw_64_kb_d_x;
0191     case DC_SW_VAR_S_X:
0192         return dcn_bw_sw_var_s_x;
0193     case DC_SW_VAR_D_X:
0194         return dcn_bw_sw_var_d_x;
0195     case DC_SW_256B_S:
0196     case DC_SW_256_D:
0197     case DC_SW_256_R:
0198     case DC_SW_4KB_R:
0199     case DC_SW_64KB_R:
0200     case DC_SW_VAR_R:
0201     case DC_SW_4KB_R_X:
0202     case DC_SW_64KB_R_X:
0203     case DC_SW_VAR_R_X:
0204     default:
0205         BREAK_TO_DEBUGGER(); /*not in formula*/
0206         return dcn_bw_sw_4_kb_s;
0207     }
0208 }
0209
0210 static int tl_lb_bpp_to_int(enum lb_pixel_depth depth)
0211 {
0212     switch (depth) {
0213     case LB_PIXEL_DEPTH_18BPP:
0214         return 18;
0215     case LB_PIXEL_DEPTH_24BPP:
0216         return 24;
0217     case LB_PIXEL_DEPTH_30BPP:
0218         return 30;
0219     case LB_PIXEL_DEPTH_36BPP:
0220         return 36;
0221     default:
0222         return 30;
0223     }
0224 }
0225
0226 static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format)
0227 {
0228     switch (format) {
0229     case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
0230     case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
0231         return dcn_bw_rgb_sub_16;
0232     case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
0233     case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
0234     case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
0235     case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
0236     case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
0237         return dcn_bw_rgb_sub_32;
0238     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
0239     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
0240     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
0241     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
0242         return dcn_bw_rgb_sub_64;
0243     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
0244     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
0245         return dcn_bw_yuv420_sub_8;
0246     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
0247     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
0248         return dcn_bw_yuv420_sub_10;
0249     default:
0250         return dcn_bw_rgb_sub_32;
0251     }
0252 }
0253
0254 enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode)
0255 {
0256     switch (sw_mode) {
0257     /* for 4/8/16 high tiles */
0258     case DC_SW_LINEAR:
0259         return dm_4k_tile;
0260     case DC_SW_4KB_S:
0261     case DC_SW_4KB_S_X:
0262         return dm_4k_tile;
0263     case DC_SW_64KB_S:
0264     case DC_SW_64KB_S_X:
0265     case DC_SW_64KB_S_T:
0266         return dm_64k_tile;
0267     case DC_SW_VAR_S:
0268     case DC_SW_VAR_S_X:
0269         return dm_256k_tile;
0270
0271     /* For 64bpp 2 high tiles */
0272     case DC_SW_4KB_D:
0273     case DC_SW_4KB_D_X:
0274         return dm_4k_tile;
0275     case DC_SW_64KB_D:
0276     case DC_SW_64KB_D_X:
0277     case DC_SW_64KB_D_T:
0278         return dm_64k_tile;
0279     case DC_SW_VAR_D:
0280     case DC_SW_VAR_D_X:
0281         return dm_256k_tile;
0282
0283     case DC_SW_4KB_R:
0284     case DC_SW_4KB_R_X:
0285         return dm_4k_tile;
0286     case DC_SW_64KB_R:
0287     case DC_SW_64KB_R_X:
0288         return dm_64k_tile;
0289     case DC_SW_VAR_R:
0290     case DC_SW_VAR_R_X:
0291         return dm_256k_tile;
0292
0293     /* Unsupported swizzle modes for dcn */
0294     case DC_SW_256B_S:
0295     default:
0296         ASSERT(0); /* Not supported */
0297         return 0;
0298     }
0299 }
0300
0301 static void pipe_ctx_to_e2e_pipe_params (
0302         const struct pipe_ctx *pipe,
0303         struct _vcs_dpi_display_pipe_params_st *input)
0304 {
0305     input->src.is_hsplit = false;
0306
0307     /* stereo can never be split */
0308     if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
0309         pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
0310         /* reset the split group if it was already considered split. */
0311         input->src.hsplit_grp = pipe->pipe_idx;
0312     } else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) {
0313         input->src.is_hsplit = true;
0314     } else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) {
0315         input->src.is_hsplit = true;
0316     }
0317
0318     if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
0319         /*
0320          * this method requires us to always re-calculate watermark when dcc change
0321          * between flip.
0322          */
0323         input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;
0324     } else {
0325         /*
0326          * allow us to disable dcc on the fly without re-calculating WM
0327          *
0328          * extra overhead for DCC is quite small.  for 1080p WM without
0329          * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
0330          */
0331         unsigned int bpe;
0332
0333         input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
0334             dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
0335     }
0336     input->src.dcc_rate            = 1;
0337     input->src.meta_pitch          = pipe->plane_state->dcc.meta_pitch;
0338     input->src.source_scan         = dm_horz;
0339     input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
0340
0341     input->src.viewport_width      = pipe->plane_res.scl_data.viewport.width;
0342     input->src.viewport_height     = pipe->plane_res.scl_data.viewport.height;
0343     input->src.data_pitch          = pipe->plane_res.scl_data.viewport.width;
0344     input->src.data_pitch_c        = pipe->plane_res.scl_data.viewport.width;
0345     input->src.cur0_src_width      = 128; /* TODO: Cursor calcs, not curently stored */
0346     input->src.cur0_bpp            = 32;
0347
0348     input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
0349
0350     switch (pipe->plane_state->rotation) {
0351     case ROTATION_ANGLE_0:
0352     case ROTATION_ANGLE_180:
0353         input->src.source_scan = dm_horz;
0354         break;
0355     case ROTATION_ANGLE_90:
0356     case ROTATION_ANGLE_270:
0357         input->src.source_scan = dm_vert;
0358         break;
0359     default:
0360         ASSERT(0); /* Not supported */
0361         break;
0362     }
0363
0364     /* TODO: Fix pixel format mappings */
0365     switch (pipe->plane_state->format) {
0366     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
0367     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
0368         input->src.source_format = dm_420_8;
0369         input->src.viewport_width_c    = input->src.viewport_width / 2;
0370         input->src.viewport_height_c   = input->src.viewport_height / 2;
0371         break;
0372     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
0373     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
0374         input->src.source_format = dm_420_10;
0375         input->src.viewport_width_c    = input->src.viewport_width / 2;
0376         input->src.viewport_height_c   = input->src.viewport_height / 2;
0377         break;
0378     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
0379     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
0380     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
0381     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
0382         input->src.source_format = dm_444_64;
0383         input->src.viewport_width_c    = input->src.viewport_width;
0384         input->src.viewport_height_c   = input->src.viewport_height;
0385         break;
0386     case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
0387         input->src.source_format = dm_rgbe_alpha;
0388         input->src.viewport_width_c    = input->src.viewport_width;
0389         input->src.viewport_height_c   = input->src.viewport_height;
0390         break;
0391     default:
0392         input->src.source_format = dm_444_32;
0393         input->src.viewport_width_c    = input->src.viewport_width;
0394         input->src.viewport_height_c   = input->src.viewport_height;
0395         break;
0396     }
0397
0398     input->scale_taps.htaps                = pipe->plane_res.scl_data.taps.h_taps;
0399     input->scale_ratio_depth.hscl_ratio    = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
0400     input->scale_ratio_depth.vscl_ratio    = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
0401     input->scale_ratio_depth.vinit =  pipe->plane_res.scl_data.inits.v.value/4294967296.0;
0402     if (input->scale_ratio_depth.vinit < 1.0)
0403             input->scale_ratio_depth.vinit = 1;
0404     input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
0405     input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
0406     input->scale_taps.htaps_c              = pipe->plane_res.scl_data.taps.h_taps_c;
0407     input->scale_ratio_depth.hscl_ratio_c  = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;
0408     input->scale_ratio_depth.vscl_ratio_c  = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;
0409     input->scale_ratio_depth.vinit_c       = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;
0410     if (input->scale_ratio_depth.vinit_c < 1.0)
0411             input->scale_ratio_depth.vinit_c = 1;
0412     switch (pipe->plane_res.scl_data.lb_params.depth) {
0413     case LB_PIXEL_DEPTH_30BPP:
0414         input->scale_ratio_depth.lb_depth = 30; break;
0415     case LB_PIXEL_DEPTH_36BPP:
0416         input->scale_ratio_depth.lb_depth = 36; break;
0417     default:
0418         input->scale_ratio_depth.lb_depth = 24; break;
0419     }
0420
0421
0422     input->dest.vactive        = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
0423             + pipe->stream->timing.v_border_bottom;
0424
0425     input->dest.recout_width   = pipe->plane_res.scl_data.recout.width;
0426     input->dest.recout_height  = pipe->plane_res.scl_data.recout.height;
0427
0428     input->dest.full_recout_width   = pipe->plane_res.scl_data.recout.width;
0429     input->dest.full_recout_height  = pipe->plane_res.scl_data.recout.height;
0430
0431     input->dest.htotal         = pipe->stream->timing.h_total;
0432     input->dest.hblank_start   = input->dest.htotal - pipe->stream->timing.h_front_porch;
0433     input->dest.hblank_end     = input->dest.hblank_start
0434             - pipe->stream->timing.h_addressable
0435             - pipe->stream->timing.h_border_left
0436             - pipe->stream->timing.h_border_right;
0437
0438     input->dest.vtotal         = pipe->stream->timing.v_total;
0439     input->dest.vblank_start   = input->dest.vtotal - pipe->stream->timing.v_front_porch;
0440     input->dest.vblank_end     = input->dest.vblank_start
0441             - pipe->stream->timing.v_addressable
0442             - pipe->stream->timing.v_border_bottom
0443             - pipe->stream->timing.v_border_top;
0444     input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;
0445     input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
0446     input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
0447     input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
0448     input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
0449
0450 }
0451
0452 static void dcn_bw_calc_rq_dlg_ttu(
0453         const struct dc *dc,
0454         const struct dcn_bw_internal_vars *v,
0455         struct pipe_ctx *pipe,
0456         int in_idx)
0457 {
0458     struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
0459     struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
0460     struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
0461     struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
0462     struct _vcs_dpi_display_rq_params_st *rq_param = &pipe->dml_rq_param;
0463     struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param = &pipe->dml_dlg_sys_param;
0464     struct _vcs_dpi_display_e2e_pipe_params_st *input = &pipe->dml_input;
0465     float total_active_bw = 0;
0466     float total_prefetch_bw = 0;
0467     int total_flip_bytes = 0;
0468     int i;
0469
0470     memset(dlg_regs, 0, sizeof(*dlg_regs));
0471     memset(ttu_regs, 0, sizeof(*ttu_regs));
0472     memset(rq_regs, 0, sizeof(*rq_regs));
0473     memset(rq_param, 0, sizeof(*rq_param));
0474     memset(dlg_sys_param, 0, sizeof(*dlg_sys_param));
0475     memset(input, 0, sizeof(*input));
0476
0477     for (i = 0; i < number_of_planes; i++) {
0478         total_active_bw += v->read_bandwidth[i];
0479         total_prefetch_bw += v->prefetch_bandwidth[i];
0480         total_flip_bytes += v->total_immediate_flip_bytes[i];
0481     }
0482     dlg_sys_param->total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
0483     if (dlg_sys_param->total_flip_bw < 0.0)
0484         dlg_sys_param->total_flip_bw = 0;
0485
0486     dlg_sys_param->t_mclk_wm_us = v->dram_clock_change_watermark;
0487     dlg_sys_param->t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
0488     dlg_sys_param->t_urg_wm_us = v->urgent_watermark;
0489     dlg_sys_param->t_extra_us = v->urgent_extra_latency;
0490     dlg_sys_param->deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
0491     dlg_sys_param->total_flip_bytes = total_flip_bytes;
0492
0493     pipe_ctx_to_e2e_pipe_params(pipe, &input->pipe);
0494     input->clks_cfg.dcfclk_mhz = v->dcfclk;
0495     input->clks_cfg.dispclk_mhz = v->dispclk;
0496     input->clks_cfg.dppclk_mhz = v->dppclk;
0497     input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
0498     input->clks_cfg.socclk_mhz = v->socclk;
0499     input->clks_cfg.voltage = v->voltage_level;
0500 //  dc->dml.logger = pool->base.logger;
0501     input->dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
0502     input->dout.output_type  = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
0503     //input[in_idx].dout.output_standard;
0504
0505     /*todo: soc->sr_enter_plus_exit_time??*/
0506
0507     dml1_rq_dlg_get_rq_params(dml, rq_param, &input->pipe.src);
0508     dml1_extract_rq_regs(dml, rq_regs, rq_param);
0509     dml1_rq_dlg_get_dlg_params(
0510             dml,
0511             dlg_regs,
0512             ttu_regs,
0513             &rq_param->dlg,
0514             dlg_sys_param,
0515             input,
0516             true,
0517             true,
0518             v->pte_enable == dcn_bw_yes,
0519             pipe->plane_state->flip_immediate);
0520 }
0521
0522 static void split_stream_across_pipes(
0523         struct resource_context *res_ctx,
0524         const struct resource_pool *pool,
0525         struct pipe_ctx *primary_pipe,
0526         struct pipe_ctx *secondary_pipe)
0527 {
0528     int pipe_idx = secondary_pipe->pipe_idx;
0529
0530     if (!primary_pipe->plane_state)
0531         return;
0532
0533     *secondary_pipe = *primary_pipe;
0534
0535     secondary_pipe->pipe_idx = pipe_idx;
0536     secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
0537     secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
0538     secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
0539     secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
0540     secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
0541     secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
0542     if (primary_pipe->bottom_pipe) {
0543         ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
0544         secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
0545         secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
0546     }
0547     primary_pipe->bottom_pipe = secondary_pipe;
0548     secondary_pipe->top_pipe = primary_pipe;
0549
0550     resource_build_scaling_params(primary_pipe);
0551     resource_build_scaling_params(secondary_pipe);
0552 }
0553
0554 #if 0
0555 static void calc_wm_sets_and_perf_params(
0556         struct dc_state *context,
0557         struct dcn_bw_internal_vars *v)
0558 {
0559     /* Calculate set A last to keep internal var state consistent for required config */
0560     if (v->voltage_level < 2) {
0561         v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
0562         v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
0563         v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
0564         dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
0565
0566         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
0567             v->stutter_exit_watermark * 1000;
0568         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
0569                 v->stutter_enter_plus_exit_watermark * 1000;
0570         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
0571                 v->dram_clock_change_watermark * 1000;
0572         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
0573         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
0574
0575         v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
0576         v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
0577         v->dcfclk = v->dcfclkv_nom0p8;
0578         dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
0579
0580         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
0581             v->stutter_exit_watermark * 1000;
0582         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
0583                 v->stutter_enter_plus_exit_watermark * 1000;
0584         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
0585                 v->dram_clock_change_watermark * 1000;
0586         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
0587         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
0588     }
0589
0590     if (v->voltage_level < 3) {
0591         v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
0592         v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
0593         v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
0594         v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
0595         v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
0596         v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
0597         v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
0598         v->dcfclk = v->dcfclkv_max0p9;
0599         dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
0600
0601         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
0602             v->stutter_exit_watermark * 1000;
0603         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
0604                 v->stutter_enter_plus_exit_watermark * 1000;
0605         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
0606                 v->dram_clock_change_watermark * 1000;
0607         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
0608         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
0609     }
0610
0611     v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
0612     v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
0613     v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
0614     v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
0615     v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
0616     v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
0617     v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
0618     v->dcfclk = v->dcfclk_per_state[v->voltage_level];
0619     dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
0620
0621     context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
0622         v->stutter_exit_watermark * 1000;
0623     context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
0624             v->stutter_enter_plus_exit_watermark * 1000;
0625     context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
0626             v->dram_clock_change_watermark * 1000;
0627     context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
0628     context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
0629     if (v->voltage_level >= 2) {
0630         context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
0631         context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
0632     }
0633     if (v->voltage_level >= 3)
0634         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
0635 }
0636 #endif
0637
0638 static bool dcn_bw_apply_registry_override(struct dc *dc)
0639 {
0640     bool updated = false;
0641
0642     if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
0643             && dc->debug.sr_exit_time_ns) {
0644         updated = true;
0645         dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;
0646     }
0647
0648     if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)
0649                 != dc->debug.sr_enter_plus_exit_time_ns
0650             && dc->debug.sr_enter_plus_exit_time_ns) {
0651         updated = true;
0652         dc->dcn_soc->sr_enter_plus_exit_time =
0653                 dc->debug.sr_enter_plus_exit_time_ns / 1000.0;
0654     }
0655
0656     if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns
0657             && dc->debug.urgent_latency_ns) {
0658         updated = true;
0659         dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;
0660     }
0661
0662     if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)
0663                 != dc->debug.percent_of_ideal_drambw
0664             && dc->debug.percent_of_ideal_drambw) {
0665         updated = true;
0666         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =
0667                 dc->debug.percent_of_ideal_drambw;
0668     }
0669
0670     if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)
0671                 != dc->debug.dram_clock_change_latency_ns
0672             && dc->debug.dram_clock_change_latency_ns) {
0673         updated = true;
0674         dc->dcn_soc->dram_clock_change_latency =
0675                 dc->debug.dram_clock_change_latency_ns / 1000.0;
0676     }
0677
0678     return updated;
0679 }
0680
0681 static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
0682 {
0683     /*
0684      * disable optional pipe split by lower dispclk bounding box
0685      * at DPM0
0686      */
0687     v->max_dispclk[0] = v->max_dppclk_vmin0p65;
0688 }
0689
0690 static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
0691         unsigned int pixel_rate_100hz)
0692 {
0693     float pixel_rate_mhz = pixel_rate_100hz / 10000;
0694
0695     /*
0696      * force enabling pipe split by lower dpp clock for DPM0 to just
0697      * below the specify pixel_rate, so bw calc would split pipe.
0698      */
0699     if (pixel_rate_mhz < v->max_dppclk[0])
0700         v->max_dppclk[0] = pixel_rate_mhz;
0701 }
0702
0703 static void hack_bounding_box(struct dcn_bw_internal_vars *v,
0704         struct dc_debug_options *dbg,
0705         struct dc_state *context)
0706 {
0707     int i;
0708
0709     for (i = 0; i < MAX_PIPES; i++) {
0710         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
0711
0712         /**
0713          * Workaround for avoiding pipe-split in cases where we'd split
0714          * planes that are too small, resulting in splits that aren't
0715          * valid for the scaler.
0716          */
0717         if (pipe->plane_state &&
0718             (pipe->plane_state->dst_rect.width <= 16 ||
0719              pipe->plane_state->dst_rect.height <= 16 ||
0720              pipe->plane_state->src_rect.width <= 16 ||
0721              pipe->plane_state->src_rect.height <= 16)) {
0722             hack_disable_optional_pipe_split(v);
0723             return;
0724         }
0725     }
0726
0727     if (dbg->pipe_split_policy == MPC_SPLIT_AVOID)
0728         hack_disable_optional_pipe_split(v);
0729
0730     if (dbg->pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP &&
0731         context->stream_count >= 2)
0732         hack_disable_optional_pipe_split(v);
0733
0734     if (context->stream_count == 1 &&
0735             dbg->force_single_disp_pipe_split)
0736         hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
0737 }
0738
0739 static unsigned int get_highest_allowed_voltage_level(uint32_t chip_family,
0740                               uint32_t hw_internal_rev,
0741                               uint32_t pci_revision_id)
0742 {
0743     /* for low power RV2 variants, the highest voltage level we want is 0 */
0744     if ((chip_family == FAMILY_RV) &&
0745          ASICREV_IS_RAVEN2(hw_internal_rev))
0746         switch (pci_revision_id) {
0747         case PRID_DALI_DE:
0748         case PRID_DALI_DF:
0749         case PRID_DALI_E3:
0750         case PRID_DALI_E4:
0751         case PRID_POLLOCK_94:
0752         case PRID_POLLOCK_95:
0753         case PRID_POLLOCK_E9:
0754         case PRID_POLLOCK_EA:
0755         case PRID_POLLOCK_EB:
0756             return 0;
0757         default:
0758             break;
0759         }
0760
0761     /* we are ok with all levels */
0762     return 4;
0763 }
0764
0765 bool dcn_validate_bandwidth(
0766         struct dc *dc,
0767         struct dc_state *context,
0768         bool fast_validate)
0769 {
0770     /*
0771      * we want a breakdown of the various stages of validation, which the
0772      * perf_trace macro doesn't support
0773      */
0774     BW_VAL_TRACE_SETUP();
0775
0776     const struct resource_pool *pool = dc->res_pool;
0777     struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
0778     int i, input_idx, k;
0779     int vesa_sync_start, asic_blank_end, asic_blank_start;
0780     bool bw_limit_pass;
0781     float bw_limit;
0782
0783     PERFORMANCE_TRACE_START();
0784
0785     BW_VAL_TRACE_COUNT();
0786
0787     if (dcn_bw_apply_registry_override(dc))
0788         dcn_bw_sync_calcs_and_dml(dc);
0789
0790     memset(v, 0, sizeof(*v));
0791
0792     v->sr_exit_time = dc->dcn_soc->sr_exit_time;
0793     v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
0794     v->urgent_latency = dc->dcn_soc->urgent_latency;
0795     v->write_back_latency = dc->dcn_soc->write_back_latency;
0796     v->percent_of_ideal_drambw_received_after_urg_latency =
0797             dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
0798
0799     v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;
0800     v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;
0801     v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;
0802     v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;
0803
0804     v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;
0805     v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;
0806     v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;
0807     v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;
0808
0809     v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;
0810     v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;
0811     v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;
0812     v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;
0813
0814     v->socclk = dc->dcn_soc->socclk;
0815
0816     v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
0817     v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
0818     v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
0819     v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
0820
0821     v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;
0822     v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;
0823     v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;
0824     v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;
0825
0826     v->downspreading = dc->dcn_soc->downspreading;
0827     v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;
0828     v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;
0829     v->number_of_channels = dc->dcn_soc->number_of_channels;
0830     v->vmm_page_size = dc->dcn_soc->vmm_page_size;
0831     v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;
0832     v->return_bus_width = dc->dcn_soc->return_bus_width;
0833
0834     v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;
0835     v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;
0836     v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
0837     v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
0838     v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;
0839     v->pte_enable = dc->dcn_ip->pte_enable;
0840     v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;
0841     v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;
0842     v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;
0843     v->odm_capability = dc->dcn_ip->odm_capability;
0844     v->dsc_capability = dc->dcn_ip->dsc_capability;
0845     v->line_buffer_size = dc->dcn_ip->line_buffer_size;
0846     v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;
0847     v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;
0848     v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
0849     v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;
0850     v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;
0851     v->max_num_dpp = dc->dcn_ip->max_num_dpp;
0852     v->max_num_writeback = dc->dcn_ip->max_num_writeback;
0853     v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;
0854     v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;
0855     v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;
0856     v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;
0857     v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
0858     v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
0859     v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;
0860     v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;
0861     v->under_scan_factor = dc->dcn_ip->under_scan_factor;
0862     v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;
0863     v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;
0864     v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
0865     v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
0866             dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
0867     v->bug_forcing_luma_and_chroma_request_to_same_size_fixed =
0868             dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;
0869
0870     v->voltage[5] = dcn_bw_no_support;
0871     v->voltage[4] = dcn_bw_v_max0p9;
0872     v->voltage[3] = dcn_bw_v_max0p9;
0873     v->voltage[2] = dcn_bw_v_nom0p8;
0874     v->voltage[1] = dcn_bw_v_mid0p72;
0875     v->voltage[0] = dcn_bw_v_min0p65;
0876     v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9;
0877     v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9;
0878     v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9;
0879     v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
0880     v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
0881     v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
0882     v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
0883     v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
0884     v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
0885     v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
0886     v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
0887     v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
0888     v->max_dispclk[5] = v->max_dispclk_vmax0p9;
0889     v->max_dispclk[4] = v->max_dispclk_vmax0p9;
0890     v->max_dispclk[3] = v->max_dispclk_vmax0p9;
0891     v->max_dispclk[2] = v->max_dispclk_vnom0p8;
0892     v->max_dispclk[1] = v->max_dispclk_vmid0p72;
0893     v->max_dispclk[0] = v->max_dispclk_vmin0p65;
0894     v->max_dppclk[5] = v->max_dppclk_vmax0p9;
0895     v->max_dppclk[4] = v->max_dppclk_vmax0p9;
0896     v->max_dppclk[3] = v->max_dppclk_vmax0p9;
0897     v->max_dppclk[2] = v->max_dppclk_vnom0p8;
0898     v->max_dppclk[1] = v->max_dppclk_vmid0p72;
0899     v->max_dppclk[0] = v->max_dppclk_vmin0p65;
0900     v->phyclk_per_state[5] = v->phyclkv_max0p9;
0901     v->phyclk_per_state[4] = v->phyclkv_max0p9;
0902     v->phyclk_per_state[3] = v->phyclkv_max0p9;
0903     v->phyclk_per_state[2] = v->phyclkv_nom0p8;
0904     v->phyclk_per_state[1] = v->phyclkv_mid0p72;
0905     v->phyclk_per_state[0] = v->phyclkv_min0p65;
0906     v->synchronized_vblank = dcn_bw_no;
0907     v->ta_pscalculation = dcn_bw_override;
0908     v->allow_different_hratio_vratio = dcn_bw_yes;
0909
0910     for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
0911         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
0912
0913         if (!pipe->stream)
0914             continue;
0915         /* skip all but first of split pipes */
0916         if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
0917             continue;
0918
0919         v->underscan_output[input_idx] = false; /* taken care of in recout already*/
0920         v->interlace_output[input_idx] = false;
0921
0922         v->htotal[input_idx] = pipe->stream->timing.h_total;
0923         v->vtotal[input_idx] = pipe->stream->timing.v_total;
0924         v->vactive[input_idx] = pipe->stream->timing.v_addressable +
0925                 pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;
0926         v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
0927                 - v->vactive[input_idx]
0928                 - pipe->stream->timing.v_front_porch;
0929         v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
0930         if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
0931             v->pixel_clock[input_idx] *= 2;
0932         if (!pipe->plane_state) {
0933             v->dcc_enable[input_idx] = dcn_bw_yes;
0934             v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
0935             v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
0936             v->lb_bit_per_pixel[input_idx] = 30;
0937             v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
0938             v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
0939             /*
0940              * for cases where we have no plane, we want to validate up to 1080p
0941              * source size because here we are only interested in if the output
0942              * timing is supported or not. if we cannot support native resolution
0943              * of the high res display, we still want to support lower res up scale
0944              * to native
0945              */
0946             if (v->viewport_width[input_idx] > 1920)
0947                 v->viewport_width[input_idx] = 1920;
0948             if (v->viewport_height[input_idx] > 1080)
0949                 v->viewport_height[input_idx] = 1080;
0950             v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx];
0951             v->scaler_recout_height[input_idx] = v->viewport_height[input_idx];
0952             v->override_hta_ps[input_idx] = 1;
0953             v->override_vta_ps[input_idx] = 1;
0954             v->override_hta_pschroma[input_idx] = 1;
0955             v->override_vta_pschroma[input_idx] = 1;
0956             v->source_scan[input_idx] = dcn_bw_hor;
0957
0958         } else {
0959             v->viewport_height[input_idx] =  pipe->plane_res.scl_data.viewport.height;
0960             v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;
0961             v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;
0962             v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;
0963             if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
0964                 if (pipe->plane_state->rotation % 2 == 0) {
0965                     int viewport_end = pipe->plane_res.scl_data.viewport.width
0966                             + pipe->plane_res.scl_data.viewport.x;
0967                     int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width
0968                             + pipe->bottom_pipe->plane_res.scl_data.viewport.x;
0969
0970                     if (viewport_end > viewport_b_end)
0971                         v->viewport_width[input_idx] = viewport_end
0972                             - pipe->bottom_pipe->plane_res.scl_data.viewport.x;
0973                     else
0974                         v->viewport_width[input_idx] = viewport_b_end
0975                                     - pipe->plane_res.scl_data.viewport.x;
0976                 } else  {
0977                     int viewport_end = pipe->plane_res.scl_data.viewport.height
0978                         + pipe->plane_res.scl_data.viewport.y;
0979                     int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height
0980                         + pipe->bottom_pipe->plane_res.scl_data.viewport.y;
0981
0982                     if (viewport_end > viewport_b_end)
0983                         v->viewport_height[input_idx] = viewport_end
0984                             - pipe->bottom_pipe->plane_res.scl_data.viewport.y;
0985                     else
0986                         v->viewport_height[input_idx] = viewport_b_end
0987                                     - pipe->plane_res.scl_data.viewport.y;
0988                 }
0989                 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width
0990                         + pipe->bottom_pipe->plane_res.scl_data.recout.width;
0991             }
0992
0993             if (pipe->plane_state->rotation % 2 == 0) {
0994                 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
0995                     || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
0996                 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
0997                     || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
0998             } else {
0999                 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
1000                     || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
1001                 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
1002                     || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
1003             }
1004
1005             if (dc->debug.optimized_watermark) {
1006                 /*
1007                  * this method requires us to always re-calculate watermark when dcc change
1008                  * between flip.
1009                  */
1010                 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
1011             } else {
1012                 /*
1013                  * allow us to disable dcc on the fly without re-calculating WM
1014                  *
1015                  * extra overhead for DCC is quite small.  for 1080p WM without
1016                  * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
1017                  */
1018                 unsigned int bpe;
1019
1020                 v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(
1021                         pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
1022             }
1023
1024             v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
1025                     pipe->plane_state->format);
1026             v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
1027                     pipe->plane_state->tiling_info.gfx9.swizzle);
1028             v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);
1029             v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
1030             v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
1031             v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
1032             v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
1033             /*
1034              * Spreadsheet doesn't handle taps_c is one properly,
1035              * need to force Chroma to always be scaled to pass
1036              * bandwidth validation.
1037              */
1038             if (v->override_hta_pschroma[input_idx] == 1)
1039                 v->override_hta_pschroma[input_idx] = 2;
1040             if (v->override_vta_pschroma[input_idx] == 1)
1041                 v->override_vta_pschroma[input_idx] = 2;
1042             v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
1043         }
1044         if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
1045             v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
1046         v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
1047         v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
1048                 PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
1049         v->output[input_idx] = pipe->stream->signal ==
1050                 SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
1051         v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
1052         if (v->output[input_idx] == dcn_bw_hdmi) {
1053             switch (pipe->stream->timing.display_color_depth) {
1054             case COLOR_DEPTH_101010:
1055                 v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc;
1056                 break;
1057             case COLOR_DEPTH_121212:
1058                 v->output_deep_color[input_idx]  = dcn_bw_encoder_12bpc;
1059                 break;
1060             case COLOR_DEPTH_161616:
1061                 v->output_deep_color[input_idx]  = dcn_bw_encoder_16bpc;
1062                 break;
1063             default:
1064                 break;
1065             }
1066         }
1067
1068         input_idx++;
1069     }
1070     v->number_of_active_planes = input_idx;
1071
1072     scaler_settings_calculation(v);
1073
1074     hack_bounding_box(v, &dc->debug, context);
1075
1076     mode_support_and_system_configuration(v);
1077
1078     /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */
1079     if (v->voltage_level != 0
1080             && context->stream_count == 1
1081             && dc->debug.force_single_disp_pipe_split) {
1082         v->max_dppclk[0] = v->max_dppclk_vmin0p65;
1083         mode_support_and_system_configuration(v);
1084     }
1085
1086     if (v->voltage_level == 0 &&
1087             (dc->debug.sr_exit_time_dpm0_ns
1088                 || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
1089
1090         if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)
1091             v->sr_enter_plus_exit_time =
1092                 dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
1093         if (dc->debug.sr_exit_time_dpm0_ns)
1094             v->sr_exit_time =  dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
1095         context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
1096         context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time;
1097         mode_support_and_system_configuration(v);
1098     }
1099
1100     display_pipe_configuration(v);
1101
1102     for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1103         if (v->source_scan[k] == dcn_bw_hor)
1104             v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
1105         else
1106             v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
1107     }
1108     for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1109         if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
1110             v->byte_per_pixel_dety[k] = 8.0;
1111             v->byte_per_pixel_detc[k] = 0.0;
1112         } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
1113             v->byte_per_pixel_dety[k] = 4.0;
1114             v->byte_per_pixel_detc[k] = 0.0;
1115         } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
1116             v->byte_per_pixel_dety[k] = 2.0;
1117             v->byte_per_pixel_detc[k] = 0.0;
1118         } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
1119             v->byte_per_pixel_dety[k] = 1.0;
1120             v->byte_per_pixel_detc[k] = 2.0;
1121         } else {
1122             v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
1123             v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
1124         }
1125     }
1126
1127     v->total_data_read_bandwidth = 0.0;
1128     for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1129         v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *
1130                 dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
1131         v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *
1132                 dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
1133         v->total_data_read_bandwidth = v->total_data_read_bandwidth +
1134                 v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
1135     }
1136
1137     BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1138
1139     if (v->voltage_level != number_of_states_plus_one && !fast_validate) {
1140         float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
1141
1142         if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
1143             bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
1144         else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
1145             bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72;
1146         else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8)
1147             bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8;
1148         else
1149             bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
1150
1151         if (bw_consumed < v->fabric_and_dram_bandwidth)
1152             if (dc->debug.voltage_align_fclk)
1153                 bw_consumed = v->fabric_and_dram_bandwidth;
1154
1155         display_pipe_configuration(v);
1156         /*calc_wm_sets_and_perf_params(context, v);*/
1157         /* Only 1 set is used by dcn since no noticeable
1158          * performance improvement was measured and due to hw bug DEGVIDCN10-254
1159          */
1160         dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
1161
1162         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
1163             v->stutter_exit_watermark * 1000;
1164         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
1165                 v->stutter_enter_plus_exit_watermark * 1000;
1166         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
1167                 v->dram_clock_change_watermark * 1000;
1168         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
1169         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
1170         context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
1171         context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
1172         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1173
1174         context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /
1175                 (ddr4_dram_factor_single_Channel * v->number_of_channels));
1176         if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65)
1177             context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
1178
1179         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
1180         context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
1181
1182         context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
1183         if (dc->debug.max_disp_clk == true)
1184             context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
1185
1186         if (context->bw_ctx.bw.dcn.clk.dispclk_khz <
1187                 dc->debug.min_disp_clk_khz) {
1188             context->bw_ctx.bw.dcn.clk.dispclk_khz =
1189                     dc->debug.min_disp_clk_khz;
1190         }
1191
1192         context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /
1193                 v->dispclk_dppclk_ratio;
1194         context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
1195         switch (v->voltage_level) {
1196         case 0:
1197             context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1198                     (int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);
1199             break;
1200         case 1:
1201             context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1202                     (int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);
1203             break;
1204         case 2:
1205             context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1206                     (int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);
1207             break;
1208         default:
1209             context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1210                     (int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);
1211             break;
1212         }
1213
1214         BW_VAL_TRACE_END_WATERMARKS();
1215
1216         for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
1217             struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1218
1219             /* skip inactive pipe */
1220             if (!pipe->stream)
1221                 continue;
1222             /* skip all but first of split pipes */
1223             if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1224                 continue;
1225
1226             pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1227             pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1228             pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1229             pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1230
1231             pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1232             pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1233             vesa_sync_start = pipe->stream->timing.v_addressable +
1234                         pipe->stream->timing.v_border_bottom +
1235                         pipe->stream->timing.v_front_porch;
1236
1237             asic_blank_end = (pipe->stream->timing.v_total -
1238                         vesa_sync_start -
1239                         pipe->stream->timing.v_border_top)
1240             * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1241
1242             asic_blank_start = asic_blank_end +
1243                         (pipe->stream->timing.v_border_top +
1244                         pipe->stream->timing.v_addressable +
1245                         pipe->stream->timing.v_border_bottom)
1246             * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1247
1248             pipe->pipe_dlg_param.vblank_start = asic_blank_start;
1249             pipe->pipe_dlg_param.vblank_end = asic_blank_end;
1250
1251             if (pipe->plane_state) {
1252                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1253
1254                 pipe->plane_state->update_flags.bits.full_update = 1;
1255
1256                 if (v->dpp_per_plane[input_idx] == 2 ||
1257                     ((pipe->stream->view_format ==
1258                       VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1259                       pipe->stream->view_format ==
1260                       VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1261                     (pipe->stream->timing.timing_3d_format ==
1262                      TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1263                      pipe->stream->timing.timing_3d_format ==
1264                      TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
1265                     if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1266                         /* update previously split pipe */
1267                         hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1268                         hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1269                         hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1270                         hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1271
1272                         hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1273                         hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1274                         hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
1275                         hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
1276                     } else {
1277                         /* pipe not split previously needs split */
1278                         hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool, pipe);
1279                         ASSERT(hsplit_pipe);
1280                         split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe);
1281                     }
1282
1283                     dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
1284                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1285                     /* merge previously split pipe */
1286                     pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1287                     if (hsplit_pipe->bottom_pipe)
1288                         hsplit_pipe->bottom_pipe->top_pipe = pipe;
1289                     hsplit_pipe->plane_state = NULL;
1290                     hsplit_pipe->stream = NULL;
1291                     hsplit_pipe->top_pipe = NULL;
1292                     hsplit_pipe->bottom_pipe = NULL;
1293                     /* Clear plane_res and stream_res */
1294                     memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1295                     memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1296                     resource_build_scaling_params(pipe);
1297                 }
1298                 /* for now important to do this after pipe split for building e2e params */
1299                 dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);
1300             }
1301
1302             input_idx++;
1303         }
1304     } else if (v->voltage_level == number_of_states_plus_one) {
1305         BW_VAL_TRACE_SKIP(fail);
1306     } else if (fast_validate) {
1307         BW_VAL_TRACE_SKIP(fast);
1308     }
1309
1310     if (v->voltage_level == 0) {
1311         context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
1312                 dc->dcn_soc->sr_enter_plus_exit_time;
1313         context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1314     }
1315
1316     /*
1317      * BW limit is set to prevent display from impacting other system functions
1318      */
1319
1320     bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
1321     bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
1322
1323     PERFORMANCE_TRACE_END();
1324     BW_VAL_TRACE_FINISH();
1325
1326     if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(
1327                             dc->ctx->asic_id.chip_family,
1328                             dc->ctx->asic_id.hw_internal_rev,
1329                             dc->ctx->asic_id.pci_revision_id))
1330         return true;
1331     else
1332         return false;
1333 }
1334
1335 static unsigned int dcn_find_normalized_clock_vdd_Level(
1336     const struct dc *dc,
1337     enum dm_pp_clock_type clocks_type,
1338     int clocks_in_khz)
1339 {
1340     int vdd_level = dcn_bw_v_min0p65;
1341
1342     if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
1343         return vdd_level;
1344
1345     switch (clocks_type) {
1346     case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
1347         if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
1348             vdd_level = dcn_bw_v_max0p91;
1349             BREAK_TO_DEBUGGER();
1350         } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
1351             vdd_level = dcn_bw_v_max0p9;
1352         } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
1353             vdd_level = dcn_bw_v_nom0p8;
1354         } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {
1355             vdd_level = dcn_bw_v_mid0p72;
1356         } else
1357             vdd_level = dcn_bw_v_min0p65;
1358         break;
1359     case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
1360         if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
1361             vdd_level = dcn_bw_v_max0p91;
1362             BREAK_TO_DEBUGGER();
1363         } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
1364             vdd_level = dcn_bw_v_max0p9;
1365         } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
1366             vdd_level = dcn_bw_v_nom0p8;
1367         } else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {
1368             vdd_level = dcn_bw_v_mid0p72;
1369         } else
1370             vdd_level = dcn_bw_v_min0p65;
1371         break;
1372
1373     case DM_PP_CLOCK_TYPE_DPPCLK:
1374         if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
1375             vdd_level = dcn_bw_v_max0p91;
1376             BREAK_TO_DEBUGGER();
1377         } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
1378             vdd_level = dcn_bw_v_max0p9;
1379         } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {
1380             vdd_level = dcn_bw_v_nom0p8;
1381         } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {
1382             vdd_level = dcn_bw_v_mid0p72;
1383         } else
1384             vdd_level = dcn_bw_v_min0p65;
1385         break;
1386
1387     case DM_PP_CLOCK_TYPE_MEMORY_CLK:
1388         {
1389             unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
1390
1391             if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
1392                 vdd_level = dcn_bw_v_max0p91;
1393                 BREAK_TO_DEBUGGER();
1394             } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
1395                 vdd_level = dcn_bw_v_max0p9;
1396             } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
1397                 vdd_level = dcn_bw_v_nom0p8;
1398             } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
1399                 vdd_level = dcn_bw_v_mid0p72;
1400             } else
1401                 vdd_level = dcn_bw_v_min0p65;
1402         }
1403         break;
1404
1405     case DM_PP_CLOCK_TYPE_DCFCLK:
1406         if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
1407             vdd_level = dcn_bw_v_max0p91;
1408             BREAK_TO_DEBUGGER();
1409         } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
1410             vdd_level = dcn_bw_v_max0p9;
1411         } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {
1412             vdd_level = dcn_bw_v_nom0p8;
1413         } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {
1414             vdd_level = dcn_bw_v_mid0p72;
1415         } else
1416             vdd_level = dcn_bw_v_min0p65;
1417         break;
1418
1419     default:
1420          break;
1421     }
1422     return vdd_level;
1423 }
1424
1425 unsigned int dcn_find_dcfclk_suits_all(
1426     const struct dc *dc,
1427     struct dc_clocks *clocks)
1428 {
1429     unsigned vdd_level, vdd_level_temp;
1430     unsigned dcf_clk;
1431
1432     /*find a common supported voltage level*/
1433     vdd_level = dcn_find_normalized_clock_vdd_Level(
1434         dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);
1435     vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1436         dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);
1437
1438     vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1439     vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1440         dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
1441     vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1442
1443     vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1444         dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);
1445     vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1446     vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1447         dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);
1448
1449     /*find that level conresponding dcfclk*/
1450     vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1451     if (vdd_level == dcn_bw_v_max0p91) {
1452         BREAK_TO_DEBUGGER();
1453         dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
1454     } else if (vdd_level == dcn_bw_v_max0p9)
1455         dcf_clk =  dc->dcn_soc->dcfclkv_max0p9*1000;
1456     else if (vdd_level == dcn_bw_v_nom0p8)
1457         dcf_clk =  dc->dcn_soc->dcfclkv_nom0p8*1000;
1458     else if (vdd_level == dcn_bw_v_mid0p72)
1459         dcf_clk =  dc->dcn_soc->dcfclkv_mid0p72*1000;
1460     else
1461         dcf_clk =  dc->dcn_soc->dcfclkv_min0p65*1000;
1462
1463     DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk);
1464     return dcf_clk;
1465 }
1466
1467 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1468 {
1469     int i;
1470
1471     if (clks->num_levels == 0)
1472         return false;
1473
1474     for (i = 0; i < clks->num_levels; i++)
1475         /* Ensure that the result is sane */
1476         if (clks->data[i].clocks_in_khz == 0)
1477             return false;
1478
1479     return true;
1480 }
1481
1482 void dcn_bw_update_from_pplib(struct dc *dc)
1483 {
1484     struct dc_context *ctx = dc->ctx;
1485     struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1486     bool res;
1487     unsigned vmin0p65_idx, vmid0p72_idx, vnom0p8_idx, vmax0p9_idx;
1488
1489     /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
1490     res = dm_pp_get_clock_levels_by_type_with_voltage(
1491             ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1492
1493     if (res)
1494         res = verify_clock_values(&fclks);
1495
1496     if (res) {
1497         ASSERT(fclks.num_levels);
1498
1499         vmin0p65_idx = 0;
1500         vmid0p72_idx = fclks.num_levels -
1501             (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1));
1502         vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1);
1503         vmax0p9_idx = fclks.num_levels - 1;
1504
1505         dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 =
1506             32 * (fclks.data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0;
1507         dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 =
1508             dc->dcn_soc->number_of_channels *
1509             (fclks.data[vmid0p72_idx].clocks_in_khz / 1000.0)
1510             * ddr4_dram_factor_single_Channel / 1000.0;
1511         dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 =
1512             dc->dcn_soc->number_of_channels *
1513             (fclks.data[vnom0p8_idx].clocks_in_khz / 1000.0)
1514             * ddr4_dram_factor_single_Channel / 1000.0;
1515         dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 =
1516             dc->dcn_soc->number_of_channels *
1517             (fclks.data[vmax0p9_idx].clocks_in_khz / 1000.0)
1518             * ddr4_dram_factor_single_Channel / 1000.0;
1519     } else
1520         BREAK_TO_DEBUGGER();
1521
1522     res = dm_pp_get_clock_levels_by_type_with_voltage(
1523             ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1524
1525     if (res)
1526         res = verify_clock_values(&dcfclks);
1527
1528     if (res && dcfclks.num_levels >= 3) {
1529         dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0;
1530         dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0;
1531         dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0;
1532         dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0;
1533     } else
1534         BREAK_TO_DEBUGGER();
1535 }
1536
1537 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
1538 {
1539     struct pp_smu_funcs_rv *pp = NULL;
1540     struct pp_smu_wm_range_sets ranges = {0};
1541     int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1542     const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
1543
1544     if (dc->res_pool->pp_smu)
1545         pp = &dc->res_pool->pp_smu->rv_funcs;
1546     if (!pp || !pp->set_wm_ranges)
1547         return;
1548
1549     min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
1550     min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
1551     socclk_khz = dc->dcn_soc->socclk * 1000;
1552
1553     /* Now notify PPLib/SMU about which Watermarks sets they should select
1554      * depending on DPM state they are in. And update BW MGR GFX Engine and
1555      * Memory clock member variables for Watermarks calculations for each
1556      * Watermark Set. Only one watermark set for dcn1 due to hw bug DEGVIDCN10-254.
1557      */
1558     /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
1559      * care what the value is, hence min to overdrive level
1560      */
1561     ranges.num_reader_wm_sets = WM_SET_COUNT;
1562     ranges.num_writer_wm_sets = WM_SET_COUNT;
1563     ranges.reader_wm_sets[0].wm_inst = WM_A;
1564     ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000;
1565     ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1566     ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000;
1567     ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1568     ranges.writer_wm_sets[0].wm_inst = WM_A;
1569     ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000;
1570     ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1571     ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000;
1572     ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1573
1574     if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
1575         ranges.reader_wm_sets[0].wm_inst = WM_A;
1576         ranges.reader_wm_sets[0].min_drain_clk_mhz = 300;
1577         ranges.reader_wm_sets[0].max_drain_clk_mhz = 5000;
1578         ranges.reader_wm_sets[0].min_fill_clk_mhz = 800;
1579         ranges.reader_wm_sets[0].max_fill_clk_mhz = 5000;
1580         ranges.writer_wm_sets[0].wm_inst = WM_A;
1581         ranges.writer_wm_sets[0].min_fill_clk_mhz = 200;
1582         ranges.writer_wm_sets[0].max_fill_clk_mhz = 5000;
1583         ranges.writer_wm_sets[0].min_drain_clk_mhz = 800;
1584         ranges.writer_wm_sets[0].max_drain_clk_mhz = 5000;
1585     }
1586
1587     ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0];
1588     ranges.reader_wm_sets[1].wm_inst = WM_B;
1589
1590     ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0];
1591     ranges.reader_wm_sets[2].wm_inst = WM_C;
1592
1593     ranges.reader_wm_sets[3] = ranges.writer_wm_sets[0];
1594     ranges.reader_wm_sets[3].wm_inst = WM_D;
1595
1596     /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1597     pp->set_wm_ranges(&pp->pp_smu, &ranges);
1598 }
1599
1600 void dcn_bw_sync_calcs_and_dml(struct dc *dc)
1601 {
1602     DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
1603             "sr_enter_plus_exit_time: %f ns\n"
1604             "urgent_latency: %f ns\n"
1605             "write_back_latency: %f ns\n"
1606             "percent_of_ideal_drambw_received_after_urg_latency: %f %%\n"
1607             "max_request_size: %d bytes\n"
1608             "dcfclkv_max0p9: %f kHz\n"
1609             "dcfclkv_nom0p8: %f kHz\n"
1610             "dcfclkv_mid0p72: %f kHz\n"
1611             "dcfclkv_min0p65: %f kHz\n"
1612             "max_dispclk_vmax0p9: %f kHz\n"
1613             "max_dispclk_vnom0p8: %f kHz\n"
1614             "max_dispclk_vmid0p72: %f kHz\n"
1615             "max_dispclk_vmin0p65: %f kHz\n"
1616             "max_dppclk_vmax0p9: %f kHz\n"
1617             "max_dppclk_vnom0p8: %f kHz\n"
1618             "max_dppclk_vmid0p72: %f kHz\n"
1619             "max_dppclk_vmin0p65: %f kHz\n"
1620             "socclk: %f kHz\n"
1621             "fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n"
1622             "fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n"
1623             "fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n"
1624             "fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n"
1625             "phyclkv_max0p9: %f kHz\n"
1626             "phyclkv_nom0p8: %f kHz\n"
1627             "phyclkv_mid0p72: %f kHz\n"
1628             "phyclkv_min0p65: %f kHz\n"
1629             "downspreading: %f %%\n"
1630             "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
1631             "urgent_out_of_order_return_per_channel: %d Bytes\n"
1632             "number_of_channels: %d\n"
1633             "vmm_page_size: %d Bytes\n"
1634             "dram_clock_change_latency: %f ns\n"
1635             "return_bus_width: %d Bytes\n",
1636             dc->dcn_soc->sr_exit_time * 1000,
1637             dc->dcn_soc->sr_enter_plus_exit_time * 1000,
1638             dc->dcn_soc->urgent_latency * 1000,
1639             dc->dcn_soc->write_back_latency * 1000,
1640             dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,
1641             dc->dcn_soc->max_request_size,
1642             dc->dcn_soc->dcfclkv_max0p9 * 1000,
1643             dc->dcn_soc->dcfclkv_nom0p8 * 1000,
1644             dc->dcn_soc->dcfclkv_mid0p72 * 1000,
1645             dc->dcn_soc->dcfclkv_min0p65 * 1000,
1646             dc->dcn_soc->max_dispclk_vmax0p9 * 1000,
1647             dc->dcn_soc->max_dispclk_vnom0p8 * 1000,
1648             dc->dcn_soc->max_dispclk_vmid0p72 * 1000,
1649             dc->dcn_soc->max_dispclk_vmin0p65 * 1000,
1650             dc->dcn_soc->max_dppclk_vmax0p9 * 1000,
1651             dc->dcn_soc->max_dppclk_vnom0p8 * 1000,
1652             dc->dcn_soc->max_dppclk_vmid0p72 * 1000,
1653             dc->dcn_soc->max_dppclk_vmin0p65 * 1000,
1654             dc->dcn_soc->socclk * 1000,
1655             dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,
1656             dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,
1657             dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,
1658             dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,
1659             dc->dcn_soc->phyclkv_max0p9 * 1000,
1660             dc->dcn_soc->phyclkv_nom0p8 * 1000,
1661             dc->dcn_soc->phyclkv_mid0p72 * 1000,
1662             dc->dcn_soc->phyclkv_min0p65 * 1000,
1663             dc->dcn_soc->downspreading * 100,
1664             dc->dcn_soc->round_trip_ping_latency_cycles,
1665             dc->dcn_soc->urgent_out_of_order_return_per_channel,
1666             dc->dcn_soc->number_of_channels,
1667             dc->dcn_soc->vmm_page_size,
1668             dc->dcn_soc->dram_clock_change_latency * 1000,
1669             dc->dcn_soc->return_bus_width);
1670     DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n"
1671             "det_buffer_size_in_kbyte: %f\n"
1672             "dpp_output_buffer_pixels: %f\n"
1673             "opp_output_buffer_lines: %f\n"
1674             "pixel_chunk_size_in_kbyte: %f\n"
1675             "pte_enable: %d\n"
1676             "pte_chunk_size: %d kbytes\n"
1677             "meta_chunk_size: %d kbytes\n"
1678             "writeback_chunk_size: %d kbytes\n"
1679             "odm_capability: %d\n"
1680             "dsc_capability: %d\n"
1681             "line_buffer_size: %d bits\n"
1682             "max_line_buffer_lines: %d\n"
1683             "is_line_buffer_bpp_fixed: %d\n"
1684             "line_buffer_fixed_bpp: %d\n"
1685             "writeback_luma_buffer_size: %d kbytes\n"
1686             "writeback_chroma_buffer_size: %d kbytes\n"
1687             "max_num_dpp: %d\n"
1688             "max_num_writeback: %d\n"
1689             "max_dchub_topscl_throughput: %d pixels/dppclk\n"
1690             "max_pscl_tolb_throughput: %d pixels/dppclk\n"
1691             "max_lb_tovscl_throughput: %d pixels/dppclk\n"
1692             "max_vscl_tohscl_throughput: %d pixels/dppclk\n"
1693             "max_hscl_ratio: %f\n"
1694             "max_vscl_ratio: %f\n"
1695             "max_hscl_taps: %d\n"
1696             "max_vscl_taps: %d\n"
1697             "pte_buffer_size_in_requests: %d\n"
1698             "dispclk_ramping_margin: %f %%\n"
1699             "under_scan_factor: %f %%\n"
1700             "max_inter_dcn_tile_repeaters: %d\n"
1701             "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
1702             "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
1703             "dcfclk_cstate_latency: %d\n",
1704             dc->dcn_ip->rob_buffer_size_in_kbyte,
1705             dc->dcn_ip->det_buffer_size_in_kbyte,
1706             dc->dcn_ip->dpp_output_buffer_pixels,
1707             dc->dcn_ip->opp_output_buffer_lines,
1708             dc->dcn_ip->pixel_chunk_size_in_kbyte,
1709             dc->dcn_ip->pte_enable,
1710             dc->dcn_ip->pte_chunk_size,
1711             dc->dcn_ip->meta_chunk_size,
1712             dc->dcn_ip->writeback_chunk_size,
1713             dc->dcn_ip->odm_capability,
1714             dc->dcn_ip->dsc_capability,
1715             dc->dcn_ip->line_buffer_size,
1716             dc->dcn_ip->max_line_buffer_lines,
1717             dc->dcn_ip->is_line_buffer_bpp_fixed,
1718             dc->dcn_ip->line_buffer_fixed_bpp,
1719             dc->dcn_ip->writeback_luma_buffer_size,
1720             dc->dcn_ip->writeback_chroma_buffer_size,
1721             dc->dcn_ip->max_num_dpp,
1722             dc->dcn_ip->max_num_writeback,
1723             dc->dcn_ip->max_dchub_topscl_throughput,
1724             dc->dcn_ip->max_pscl_tolb_throughput,
1725             dc->dcn_ip->max_lb_tovscl_throughput,
1726             dc->dcn_ip->max_vscl_tohscl_throughput,
1727             dc->dcn_ip->max_hscl_ratio,
1728             dc->dcn_ip->max_vscl_ratio,
1729             dc->dcn_ip->max_hscl_taps,
1730             dc->dcn_ip->max_vscl_taps,
1731             dc->dcn_ip->pte_buffer_size_in_requests,
1732             dc->dcn_ip->dispclk_ramping_margin,
1733             dc->dcn_ip->under_scan_factor * 100,
1734             dc->dcn_ip->max_inter_dcn_tile_repeaters,
1735             dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
1736             dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,
1737             dc->dcn_ip->dcfclk_cstate_latency);
1738
1739     dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1740     dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;
1741     dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;
1742     dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;
1743     dc->dml.soc.ideal_dram_bw_after_urgent_percent =
1744             dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
1745     dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;
1746     dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;
1747     dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =
1748             dc->dcn_soc->round_trip_ping_latency_cycles;
1749     dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =
1750             dc->dcn_soc->urgent_out_of_order_return_per_channel;
1751     dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;
1752     dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;
1753     dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;
1754     dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;
1755
1756     dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte;
1757     dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte;
1758     dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
1759     dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
1760     dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte;
1761     dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;
1762     dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size;
1763     dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;
1764     dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;
1765     dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;
1766     dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
1767     dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;
1768     dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;
1769     dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;
1770     dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;
1771     dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;
1772     dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;
1773     dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;
1774     dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;
1775     dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;
1776     dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;
1777     dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
1778     dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
1779     dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;
1780     dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;
1781     /*pte_buffer_size_in_requests missing in dml*/
1782     dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;
1783     dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;
1784     dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
1785     dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
1786         dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
1787     dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
1788         dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
1789     dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
1790 }