display/dc/dm_services.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 /**
0027  * This file defines external dependencies of Display Core.
0028  */
0029
0030 #ifndef __DM_SERVICES_H__
0031
0032 #define __DM_SERVICES_H__
0033
0034 /* TODO: remove when DC is complete. */
0035 #include "dm_services_types.h"
0036 #include "logger_interface.h"
0037 #include "link_service_types.h"
0038
0039 #undef DEPRECATED
0040
0041 struct dmub_srv;
0042 struct dc_dmub_srv;
0043
0044 irq_handler_idx dm_register_interrupt(
0045     struct dc_context *ctx,
0046     struct dc_interrupt_params *int_params,
0047     interrupt_handler ih,
0048     void *handler_args);
0049
0050 /*
0051  *
0052  * GPU registers access
0053  *
0054  */
0055 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
0056               const char *func_name);
0057
0058 /* enable for debugging new code, this adds 50k to the driver size. */
0059 /* #define DM_CHECK_ADDR_0 */
0060
0061 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
0062                uint32_t value, const char *func_name);
0063
0064 #define dm_read_reg(ctx, address)   \
0065     dm_read_reg_func(ctx, address, __func__)
0066
0067 #define dm_write_reg(ctx, address, value)   \
0068     dm_write_reg_func(ctx, address, value, __func__)
0069
0070 static inline uint32_t dm_read_index_reg(
0071     const struct dc_context *ctx,
0072     enum cgs_ind_reg addr_space,
0073     uint32_t index)
0074 {
0075     return cgs_read_ind_register(ctx->cgs_device, addr_space, index);
0076 }
0077
0078 static inline void dm_write_index_reg(
0079     const struct dc_context *ctx,
0080     enum cgs_ind_reg addr_space,
0081     uint32_t index,
0082     uint32_t value)
0083 {
0084     cgs_write_ind_register(ctx->cgs_device, addr_space, index, value);
0085 }
0086
0087 static inline uint32_t get_reg_field_value_ex(
0088     uint32_t reg_value,
0089     uint32_t mask,
0090     uint8_t shift)
0091 {
0092     return (mask & reg_value) >> shift;
0093 }
0094
0095 #define get_reg_field_value(reg_value, reg_name, reg_field)\
0096     get_reg_field_value_ex(\
0097         (reg_value),\
0098         reg_name ## __ ## reg_field ## _MASK,\
0099         reg_name ## __ ## reg_field ## __SHIFT)
0100
0101 static inline uint32_t set_reg_field_value_ex(
0102     uint32_t reg_value,
0103     uint32_t value,
0104     uint32_t mask,
0105     uint8_t shift)
0106 {
0107     ASSERT(mask != 0);
0108     return (reg_value & ~mask) | (mask & (value << shift));
0109 }
0110
0111 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\
0112     (reg_value) = set_reg_field_value_ex(\
0113         (reg_value),\
0114         (value),\
0115         reg_name ## __ ## reg_field ## _MASK,\
0116         reg_name ## __ ## reg_field ## __SHIFT)
0117
0118 uint32_t generic_reg_set_ex(const struct dc_context *ctx,
0119         uint32_t addr, uint32_t reg_val, int n,
0120         uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
0121
0122 uint32_t generic_reg_update_ex(const struct dc_context *ctx,
0123         uint32_t addr, int n,
0124         uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
0125
0126 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);
0127 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);
0128
0129 void reg_sequence_start_gather(const struct dc_context *ctx);
0130 void reg_sequence_start_execute(const struct dc_context *ctx);
0131 void reg_sequence_wait_done(const struct dc_context *ctx);
0132
0133 #define FD(reg_field)   reg_field ## __SHIFT, \
0134                         reg_field ## _MASK
0135
0136 /*
0137  * return number of poll before condition is met
0138  * return 0 if condition is not meet after specified time out tries
0139  */
0140 void generic_reg_wait(const struct dc_context *ctx,
0141     uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,
0142     unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
0143     const char *func_name, int line);
0144
0145 unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...);
0146
0147 /* These macros need to be used with soc15 registers in order to retrieve
0148  * the actual offset.
0149  */
0150 #define dm_write_reg_soc15(ctx, reg, inst_offset, value)    \
0151         dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__)
0152
0153 #define dm_read_reg_soc15(ctx, reg, inst_offset)    \
0154         dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__)
0155
0156 #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\
0157         generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] +  mm##reg_name + inst_offset, \
0158         n, __VA_ARGS__)
0159
0160 #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\
0161         generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \
0162         n, __VA_ARGS__)
0163
0164 #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\
0165     get_reg_field_value_ex(\
0166         (reg_value),\
0167         block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
0168         block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
0169
0170 #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\
0171     (reg_value) = set_reg_field_value_ex(\
0172         (reg_value),\
0173         (value),\
0174         block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
0175         block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
0176
0177 /**************************************
0178  * Power Play (PP) interfaces
0179  **************************************/
0180
0181 /* Gets valid clocks levels from pplib
0182  *
0183  * input: clk_type - display clk / sclk / mem clk
0184  *
0185  * output: array of valid clock levels for given type in ascending order,
0186  * with invalid levels filtered out
0187  *
0188  */
0189 bool dm_pp_get_clock_levels_by_type(
0190     const struct dc_context *ctx,
0191     enum dm_pp_clock_type clk_type,
0192     struct dm_pp_clock_levels *clk_level_info);
0193
0194 bool dm_pp_get_clock_levels_by_type_with_latency(
0195     const struct dc_context *ctx,
0196     enum dm_pp_clock_type clk_type,
0197     struct dm_pp_clock_levels_with_latency *clk_level_info);
0198
0199 bool dm_pp_get_clock_levels_by_type_with_voltage(
0200     const struct dc_context *ctx,
0201     enum dm_pp_clock_type clk_type,
0202     struct dm_pp_clock_levels_with_voltage *clk_level_info);
0203
0204 bool dm_pp_notify_wm_clock_changes(
0205     const struct dc_context *ctx,
0206     struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
0207
0208 void dm_pp_get_funcs(struct dc_context *ctx,
0209         struct pp_smu_funcs *funcs);
0210
0211 /* DAL calls this function to notify PP about completion of Mode Set.
0212  * For PP it means that current DCE clocks are those which were returned
0213  * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
0214  *
0215  * If the clocks are higher than before, then PP does nothing.
0216  *
0217  * If the clocks are lower than before, then PP reduces the voltage.
0218  *
0219  * \returns true - call is successful
0220  *      false - call failed
0221  */
0222 bool dm_pp_apply_display_requirements(
0223     const struct dc_context *ctx,
0224     const struct dm_pp_display_configuration *pp_display_cfg);
0225
0226 bool dm_pp_apply_power_level_change_request(
0227     const struct dc_context *ctx,
0228     struct dm_pp_power_level_change_request *level_change_req);
0229
0230 bool dm_pp_apply_clock_for_voltage_request(
0231     const struct dc_context *ctx,
0232     struct dm_pp_clock_for_voltage_req *clock_for_voltage_req);
0233
0234 bool dm_pp_get_static_clocks(
0235     const struct dc_context *ctx,
0236     struct dm_pp_static_clock_info *static_clk_info);
0237
0238 /****** end of PP interfaces ******/
0239
0240 struct persistent_data_flag {
0241     bool save_per_link;
0242     bool save_per_edid;
0243 };
0244
0245 bool dm_query_extended_brightness_caps
0246     (struct dc_context *ctx, enum dm_acpi_display_type display,
0247             struct dm_acpi_atif_backlight_caps *pCaps);
0248
0249 bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
0250
0251 /*
0252  *
0253  * print-out services
0254  *
0255  */
0256 #define dm_log_to_buffer(buffer, size, fmt, args)\
0257     vsnprintf(buffer, size, fmt, args)
0258
0259 static inline unsigned long long dm_get_timestamp(struct dc_context *ctx)
0260 {
0261     return ktime_get_raw_ns();
0262 }
0263
0264 unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
0265         unsigned long long current_time_stamp,
0266         unsigned long long last_time_stamp);
0267
0268 /*
0269  * performance tracing
0270  */
0271 void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc_context *ctx);
0272
0273 #define PERF_TRACE()    dm_perf_trace_timestamp(__func__, __LINE__, CTX)
0274 #define PERF_TRACE_CTX(__CTX)   dm_perf_trace_timestamp(__func__, __LINE__, __CTX)
0275
0276 /*
0277  * Debug and verification hooks
0278  */
0279
0280 void dm_dtn_log_begin(struct dc_context *ctx,
0281     struct dc_log_buffer_ctx *log_ctx);
0282 void dm_dtn_log_append_v(struct dc_context *ctx,
0283     struct dc_log_buffer_ctx *log_ctx,
0284     const char *msg, ...);
0285 void dm_dtn_log_end(struct dc_context *ctx,
0286     struct dc_log_buffer_ctx *log_ctx);
0287
0288 #endif /* __DM_SERVICES_H__ */