dc/dcn321/dcn321_dio_link_encoder.c

0001 /*
0002  * Copyright 2022 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026
0027 #include "reg_helper.h"
0028
0029 #include "core_types.h"
0030 #include "link_encoder.h"
0031 #include "dcn321_dio_link_encoder.h"
0032 #include "dcn31/dcn31_dio_link_encoder.h"
0033 #include "stream_encoder.h"
0034 #include "i2caux_interface.h"
0035 #include "dc_bios_types.h"
0036
0037 #include "gpio_service_interface.h"
0038
0039 #ifndef MIN
0040 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
0041 #endif
0042
0043 #define CTX \
0044     enc10->base.ctx
0045 #define DC_LOGGER \
0046     enc10->base.ctx->logger
0047
0048 #define REG(reg)\
0049     (enc10->link_regs->reg)
0050
0051 #undef FN
0052 #define FN(reg_name, field_name) \
0053     enc10->link_shift->field_name, enc10->link_mask->field_name
0054
0055 #define AUX_REG(reg)\
0056     (enc10->aux_regs->reg)
0057
0058 #define AUX_REG_READ(reg_name) \
0059         dm_read_reg(CTX, AUX_REG(reg_name))
0060
0061 #define AUX_REG_WRITE(reg_name, val) \
0062             dm_write_reg(CTX, AUX_REG(reg_name), val)
0063
0064 static const struct link_encoder_funcs dcn321_link_enc_funcs = {
0065     .read_state = link_enc2_read_state,
0066     .validate_output_with_stream =
0067             dcn30_link_encoder_validate_output_with_stream,
0068     .hw_init = enc32_hw_init,
0069     .setup = dcn10_link_encoder_setup,
0070     .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
0071     .enable_dp_output = dcn32_link_encoder_enable_dp_output,
0072     .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
0073     .disable_output = dcn10_link_encoder_disable_output,
0074     .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
0075     .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
0076     .update_mst_stream_allocation_table =
0077         dcn10_link_encoder_update_mst_stream_allocation_table,
0078     .psr_program_dp_dphy_fast_training =
0079             dcn10_psr_program_dp_dphy_fast_training,
0080     .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
0081     .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
0082     .enable_hpd = dcn10_link_encoder_enable_hpd,
0083     .disable_hpd = dcn10_link_encoder_disable_hpd,
0084     .is_dig_enabled = dcn10_is_dig_enabled,
0085     .destroy = dcn10_link_encoder_destroy,
0086     .fec_set_enable = enc2_fec_set_enable,
0087     .fec_set_ready = enc2_fec_set_ready,
0088     .fec_is_active = enc2_fec_is_active,
0089     .get_dig_frontend = dcn10_get_dig_frontend,
0090     .get_dig_mode = dcn10_get_dig_mode,
0091     .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
0092     .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
0093     .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
0094     .set_dig_output_mode = enc32_set_dig_output_mode,
0095 };
0096
0097 void dcn321_link_encoder_construct(
0098     struct dcn20_link_encoder *enc20,
0099     const struct encoder_init_data *init_data,
0100     const struct encoder_feature_support *enc_features,
0101     const struct dcn10_link_enc_registers *link_regs,
0102     const struct dcn10_link_enc_aux_registers *aux_regs,
0103     const struct dcn10_link_enc_hpd_registers *hpd_regs,
0104     const struct dcn10_link_enc_shift *link_shift,
0105     const struct dcn10_link_enc_mask *link_mask)
0106 {
0107     struct bp_connector_speed_cap_info bp_cap_info = {0};
0108     const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
0109     enum bp_result result = BP_RESULT_OK;
0110     struct dcn10_link_encoder *enc10 = &enc20->enc10;
0111
0112     enc10->base.funcs = &dcn321_link_enc_funcs;
0113     enc10->base.ctx = init_data->ctx;
0114     enc10->base.id = init_data->encoder;
0115
0116     enc10->base.hpd_source = init_data->hpd_source;
0117     enc10->base.connector = init_data->connector;
0118
0119     if (enc10->base.connector.id == CONNECTOR_ID_USBC)
0120         enc10->base.features.flags.bits.DP_IS_USB_C = 1;
0121
0122     enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0123
0124     enc10->base.features = *enc_features;
0125
0126     enc10->base.transmitter = init_data->transmitter;
0127
0128     /* set the flag to indicate whether driver poll the I2C data pin
0129      * while doing the DP sink detect
0130      */
0131
0132 /*  if (dal_adapter_service_is_feature_supported(as,
0133         FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
0134         enc10->base.features.flags.bits.
0135             DP_SINK_DETECT_POLL_DATA_PIN = true;*/
0136
0137     enc10->base.output_signals =
0138         SIGNAL_TYPE_DVI_SINGLE_LINK |
0139         SIGNAL_TYPE_DVI_DUAL_LINK |
0140         SIGNAL_TYPE_LVDS |
0141         SIGNAL_TYPE_DISPLAY_PORT |
0142         SIGNAL_TYPE_DISPLAY_PORT_MST |
0143         SIGNAL_TYPE_EDP |
0144         SIGNAL_TYPE_HDMI_TYPE_A;
0145
0146     enc10->link_regs = link_regs;
0147     enc10->aux_regs = aux_regs;
0148     enc10->hpd_regs = hpd_regs;
0149     enc10->link_shift = link_shift;
0150     enc10->link_mask = link_mask;
0151
0152     switch (enc10->base.transmitter) {
0153     case TRANSMITTER_UNIPHY_A:
0154         enc10->base.preferred_engine = ENGINE_ID_DIGA;
0155     break;
0156     case TRANSMITTER_UNIPHY_B:
0157         enc10->base.preferred_engine = ENGINE_ID_DIGB;
0158     break;
0159     case TRANSMITTER_UNIPHY_C:
0160         enc10->base.preferred_engine = ENGINE_ID_DIGC;
0161     break;
0162     case TRANSMITTER_UNIPHY_D:
0163         enc10->base.preferred_engine = ENGINE_ID_DIGD;
0164     break;
0165     case TRANSMITTER_UNIPHY_E:
0166         enc10->base.preferred_engine = ENGINE_ID_DIGE;
0167     break;
0168     default:
0169         ASSERT_CRITICAL(false);
0170         enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0171     }
0172
0173     /* default to one to mirror Windows behavior */
0174     enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
0175
0176     if (bp_funcs->get_connector_speed_cap_info)
0177         result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
0178                         enc10->base.connector, &bp_cap_info);
0179
0180     /* Override features with DCE-specific values */
0181     if (result == BP_RESULT_OK) {
0182         enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
0183                 bp_cap_info.DP_HBR2_EN;
0184         enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
0185                 bp_cap_info.DP_HBR3_EN;
0186         enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
0187         enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
0188         enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
0189         enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
0190         enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
0191     } else {
0192         DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
0193                 __func__,
0194                 result);
0195     }
0196     if (enc10->base.ctx->dc->debug.hdmi20_disable) {
0197         enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
0198     }
0199 }