dc/dcn32/dcn32_optc.c

0001 /*
0002  * Copyright 2022 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dcn32_optc.h"
0027
0028 #include "dcn30/dcn30_optc.h"
0029 #include "dcn31/dcn31_optc.h"
0030 #include "reg_helper.h"
0031 #include "dc.h"
0032 #include "dcn_calc_math.h"
0033 #include "dc_dmub_srv.h"
0034
0035 #define REG(reg)\
0036     optc1->tg_regs->reg
0037
0038 #define CTX \
0039     optc1->base.ctx
0040
0041 #undef FN
0042 #define FN(reg_name, field_name) \
0043     optc1->tg_shift->field_name, optc1->tg_mask->field_name
0044
0045 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
0046         struct dc_crtc_timing *timing)
0047 {
0048     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0049     uint32_t memory_mask = 0;
0050     int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
0051     int mpcc_hactive = h_active / opp_cnt;
0052     /* Each memory instance is 2048x(32x2) bits to support half line of 4096 */
0053     int odm_mem_count = (h_active + 2047) / 2048;
0054
0055     /*
0056      * display <= 4k : 2 memories + 2 pipes
0057      * 4k < display <= 8k : 4 memories + 2 pipes
0058      * 8k < display <= 12k : 6 memories + 4 pipes
0059      */
0060     if (opp_cnt == 4) {
0061         if (odm_mem_count <= 2)
0062             memory_mask = 0x3;
0063         else if (odm_mem_count <= 4)
0064             memory_mask = 0xf;
0065         else
0066             memory_mask = 0x3f;
0067     } else {
0068         if (odm_mem_count <= 2)
0069             memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
0070         else if (odm_mem_count <= 4)
0071             memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
0072         else
0073             memory_mask = 0x77;
0074     }
0075
0076     REG_SET(OPTC_MEMORY_CONFIG, 0,
0077         OPTC_MEM_SEL, memory_mask);
0078
0079     if (opp_cnt == 2) {
0080         REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
0081                 OPTC_NUM_OF_INPUT_SEGMENT, 1,
0082                 OPTC_SEG0_SRC_SEL, opp_id[0],
0083                 OPTC_SEG1_SRC_SEL, opp_id[1]);
0084     } else if (opp_cnt == 4) {
0085         REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
0086                 OPTC_NUM_OF_INPUT_SEGMENT, 3,
0087                 OPTC_SEG0_SRC_SEL, opp_id[0],
0088                 OPTC_SEG1_SRC_SEL, opp_id[1],
0089                 OPTC_SEG2_SRC_SEL, opp_id[2],
0090                 OPTC_SEG3_SRC_SEL, opp_id[3]);
0091     }
0092
0093     REG_UPDATE(OPTC_WIDTH_CONTROL,
0094             OPTC_SEGMENT_WIDTH, mpcc_hactive);
0095
0096     REG_UPDATE(OTG_H_TIMING_CNTL,
0097             OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
0098     optc1->opp_count = opp_cnt;
0099 }
0100
0101 static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
0102 {
0103     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0104
0105     REG_UPDATE(OTG_H_TIMING_CNTL,
0106             OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
0107 }
0108 /**
0109  * Enable CRTC
0110  * Enable CRTC - call ASIC Control Object to enable Timing generator.
0111  */
0112 static bool optc32_enable_crtc(struct timing_generator *optc)
0113 {
0114     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0115
0116     /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
0117     REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
0118             OPTC_SEG0_SRC_SEL, optc->inst);
0119
0120     /* VTG enable first is for HW workaround */
0121     REG_UPDATE(CONTROL,
0122             VTG0_ENABLE, 1);
0123
0124     REG_SEQ_START();
0125
0126     /* Enable CRTC */
0127     REG_UPDATE_2(OTG_CONTROL,
0128             OTG_DISABLE_POINT_CNTL, 2,
0129             OTG_MASTER_EN, 1);
0130
0131     REG_SEQ_SUBMIT();
0132     REG_SEQ_WAIT_DONE();
0133
0134     return true;
0135 }
0136
0137 /* disable_crtc */
0138 static bool optc32_disable_crtc(struct timing_generator *optc)
0139 {
0140     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0141
0142     /* disable otg request until end of the first line
0143      * in the vertical blank region
0144      */
0145     REG_UPDATE(OTG_CONTROL,
0146             OTG_MASTER_EN, 0);
0147
0148     REG_UPDATE(CONTROL,
0149             VTG0_ENABLE, 0);
0150
0151     /* CRTC disabled, so disable  clock. */
0152     REG_WAIT(OTG_CLOCK_CONTROL,
0153             OTG_BUSY, 0,
0154             1, 100000);
0155
0156     return true;
0157 }
0158
0159 void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
0160 {
0161     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0162
0163     /* Disable immediately. */
0164     REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
0165
0166     /* CRTC disabled, so disable  clock. */
0167     REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
0168 }
0169
0170 static void optc32_set_odm_bypass(struct timing_generator *optc,
0171         const struct dc_crtc_timing *dc_crtc_timing)
0172 {
0173     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0174     enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
0175
0176     REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
0177             OPTC_NUM_OF_INPUT_SEGMENT, 0,
0178             OPTC_SEG0_SRC_SEL, optc->inst,
0179             OPTC_SEG1_SRC_SEL, 0xf,
0180             OPTC_SEG2_SRC_SEL, 0xf,
0181             OPTC_SEG3_SRC_SEL, 0xf
0182             );
0183
0184     h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
0185     REG_UPDATE(OTG_H_TIMING_CNTL,
0186             OTG_H_TIMING_DIV_MODE, h_div);
0187
0188     REG_SET(OPTC_MEMORY_CONFIG, 0,
0189             OPTC_MEM_SEL, 0);
0190     optc1->opp_count = 1;
0191 }
0192
0193 void optc32_setup_manual_trigger(struct timing_generator *optc)
0194 {
0195     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0196     struct dc *dc = optc->ctx->dc;
0197
0198     if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
0199         dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
0200     else {
0201         /*
0202          * MIN_MASK_EN is gone and MASK is now always enabled.
0203          *
0204          * To get it to it work with manual trigger we need to make sure
0205          * we program the correct bit.
0206          */
0207         REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
0208                 OTG_V_TOTAL_MIN_SEL, 1,
0209                 OTG_V_TOTAL_MAX_SEL, 1,
0210                 OTG_FORCE_LOCK_ON_EVENT, 0,
0211                 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
0212
0213         // Setup manual flow control for EOF via TRIG_A
0214         optc->funcs->setup_manual_trigger(optc);
0215     }
0216 }
0217
0218 void optc32_set_drr(
0219     struct timing_generator *optc,
0220     const struct drr_params *params)
0221 {
0222     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0223
0224     if (params != NULL &&
0225         params->vertical_total_max > 0 &&
0226         params->vertical_total_min > 0) {
0227
0228         if (params->vertical_total_mid != 0) {
0229
0230             REG_SET(OTG_V_TOTAL_MID, 0,
0231                 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
0232
0233             REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
0234                     OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
0235                     OTG_VTOTAL_MID_FRAME_NUM,
0236                     (uint8_t)params->vertical_total_mid_frame_num);
0237
0238         }
0239
0240         optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
0241         optc32_setup_manual_trigger(optc);
0242     } else {
0243         REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
0244                 OTG_SET_V_TOTAL_MIN_MASK, 0,
0245                 OTG_V_TOTAL_MIN_SEL, 0,
0246                 OTG_V_TOTAL_MAX_SEL, 0,
0247                 OTG_FORCE_LOCK_ON_EVENT, 0);
0248
0249         optc->funcs->set_vtotal_min_max(optc, 0, 0);
0250     }
0251 }
0252
0253 static struct timing_generator_funcs dcn32_tg_funcs = {
0254         .validate_timing = optc1_validate_timing,
0255         .program_timing = optc1_program_timing,
0256         .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
0257         .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
0258         .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
0259         .program_global_sync = optc1_program_global_sync,
0260         .enable_crtc = optc32_enable_crtc,
0261         .disable_crtc = optc32_disable_crtc,
0262         .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable,
0263         /* used by enable_timing_synchronization. Not need for FPGA */
0264         .is_counter_moving = optc1_is_counter_moving,
0265         .get_position = optc1_get_position,
0266         .get_frame_count = optc1_get_vblank_counter,
0267         .get_scanoutpos = optc1_get_crtc_scanoutpos,
0268         .get_otg_active_size = optc1_get_otg_active_size,
0269         .set_early_control = optc1_set_early_control,
0270         /* used by enable_timing_synchronization. Not need for FPGA */
0271         .wait_for_state = optc1_wait_for_state,
0272         .set_blank_color = optc3_program_blank_color,
0273         .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
0274         .triplebuffer_lock = optc3_triplebuffer_lock,
0275         .triplebuffer_unlock = optc2_triplebuffer_unlock,
0276         .enable_reset_trigger = optc1_enable_reset_trigger,
0277         .enable_crtc_reset = optc1_enable_crtc_reset,
0278         .disable_reset_trigger = optc1_disable_reset_trigger,
0279         .lock = optc3_lock,
0280         .unlock = optc1_unlock,
0281         .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
0282         .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
0283         .enable_optc_clock = optc1_enable_optc_clock,
0284         .set_drr = optc32_set_drr,
0285         .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
0286         .set_vtotal_min_max = optc3_set_vtotal_min_max,
0287         .set_static_screen_control = optc1_set_static_screen_control,
0288         .program_stereo = optc1_program_stereo,
0289         .is_stereo_left_eye = optc1_is_stereo_left_eye,
0290         .tg_init = optc3_tg_init,
0291         .is_tg_enabled = optc1_is_tg_enabled,
0292         .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
0293         .clear_optc_underflow = optc1_clear_optc_underflow,
0294         .setup_global_swap_lock = NULL,
0295         .get_crc = optc1_get_crc,
0296         .configure_crc = optc1_configure_crc,
0297         .set_dsc_config = optc3_set_dsc_config,
0298         .get_dsc_status = optc2_get_dsc_status,
0299         .set_dwb_source = NULL,
0300         .set_odm_bypass = optc32_set_odm_bypass,
0301         .set_odm_combine = optc32_set_odm_combine,
0302         .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
0303         .get_optc_source = optc2_get_optc_source,
0304         .set_out_mux = optc3_set_out_mux,
0305         .set_drr_trigger_window = optc3_set_drr_trigger_window,
0306         .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
0307         .set_gsl = optc2_set_gsl,
0308         .set_gsl_source_select = optc2_set_gsl_source_select,
0309         .set_vtg_params = optc1_set_vtg_params,
0310         .program_manual_trigger = optc2_program_manual_trigger,
0311         .setup_manual_trigger = optc2_setup_manual_trigger,
0312         .get_hw_timing = optc1_get_hw_timing,
0313 };
0314
0315 void dcn32_timing_generator_init(struct optc *optc1)
0316 {
0317     optc1->base.funcs = &dcn32_tg_funcs;
0318
0319     optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
0320     optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
0321
0322     optc1->min_h_blank = 32;
0323     optc1->min_v_blank = 3;
0324     optc1->min_v_blank_interlace = 5;
0325     optc1->min_h_sync_width = 4;
0326     optc1->min_v_sync_width = 1;
0327 }
0328