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0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "reg_helper.h"
0027 #include "dcn30/dcn30_mpc.h"
0028 #include "dcn30/dcn30_cm_common.h"
0029 #include "dcn32_mpc.h"
0030 #include "basics/conversion.h"
0031 #include "dcn10/dcn10_cm_common.h"
0032 #include "dc.h"
0033 
0034 #define REG(reg)\
0035     mpc30->mpc_regs->reg
0036 
0037 #define CTX \
0038     mpc30->base.ctx
0039 
0040 #undef FN
0041 #define FN(reg_name, field_name) \
0042     mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
0043 
0044 
0045 static void mpc32_mpc_init(struct mpc *mpc)
0046 {
0047     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0048     int mpcc_id;
0049 
0050     mpc1_mpc_init(mpc);
0051 
0052     if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
0053         if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) {
0054             for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) {
0055                 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3);
0056                 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3);
0057                 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3);
0058             }
0059         }
0060         if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) {
0061             for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++)
0062                 REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);
0063         }
0064     }
0065 }
0066 
0067 static void mpc32_power_on_blnd_lut(
0068     struct mpc *mpc,
0069     uint32_t mpcc_id,
0070     bool power_on)
0071 {
0072     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0073 
0074     if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {
0075         if (power_on) {
0076             REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
0077             REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
0078         } else {
0079             ASSERT(false);
0080             /* TODO: change to mpc
0081              *  dpp_base->ctx->dc->optimized_required = true;
0082              *  dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
0083              */
0084         }
0085     } else {
0086         REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
0087                 MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);
0088     }
0089 }
0090 
0091 static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)
0092 {
0093     enum dc_lut_mode mode;
0094     uint32_t mode_current = 0;
0095     uint32_t in_use = 0;
0096 
0097     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0098 
0099     REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
0100             MPCC_MCM_1DLUT_MODE_CURRENT, &mode_current);
0101     REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
0102             MPCC_MCM_1DLUT_SELECT_CURRENT, &in_use);
0103 
0104     switch (mode_current) {
0105     case 0:
0106     case 1:
0107         mode = LUT_BYPASS;
0108         break;
0109 
0110     case 2:
0111         if (in_use == 0)
0112             mode = LUT_RAM_A;
0113         else
0114             mode = LUT_RAM_B;
0115         break;
0116     default:
0117         mode = LUT_BYPASS;
0118         break;
0119     }
0120     return mode;
0121 }
0122 
0123 static void mpc32_configure_post1dlut(
0124         struct mpc *mpc,
0125         uint32_t mpcc_id,
0126         bool is_ram_a)
0127 {
0128     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0129 
0130     //TODO: this
0131     REG_UPDATE_2(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id],
0132             MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 7,
0133             MPCC_MCM_1DLUT_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
0134 
0135     REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
0136 }
0137 
0138 static void mpc32_post1dlut_get_reg_field(
0139         struct dcn30_mpc *mpc,
0140         struct dcn3_xfer_func_reg *reg)
0141 {
0142     reg->shifts.exp_region0_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
0143     reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
0144     reg->shifts.exp_region0_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
0145     reg->masks.exp_region0_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
0146     reg->shifts.exp_region1_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
0147     reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
0148     reg->shifts.exp_region1_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
0149     reg->masks.exp_region1_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
0150 
0151     reg->shifts.field_region_end = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
0152     reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
0153     reg->shifts.field_region_end_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
0154     reg->masks.field_region_end_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
0155     reg->shifts.field_region_end_base = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
0156     reg->masks.field_region_end_base = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
0157     reg->shifts.field_region_linear_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
0158     reg->masks.field_region_linear_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
0159     reg->shifts.exp_region_start = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
0160     reg->masks.exp_region_start = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
0161     reg->shifts.exp_resion_start_segment = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
0162     reg->masks.exp_resion_start_segment = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
0163 }
0164 
0165 /*program blnd lut RAM A*/
0166 static void mpc32_program_post1dluta_settings(
0167         struct mpc *mpc,
0168         uint32_t mpcc_id,
0169         const struct pwl_params *params)
0170 {
0171     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0172     struct dcn3_xfer_func_reg gam_regs;
0173 
0174     mpc32_post1dlut_get_reg_field(mpc30, &gam_regs);
0175 
0176     gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_B[mpcc_id]);
0177     gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_G[mpcc_id]);
0178     gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_R[mpcc_id]);
0179     gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[mpcc_id]);
0180     gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[mpcc_id]);
0181     gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[mpcc_id]);
0182     gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[mpcc_id]);
0183     gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[mpcc_id]);
0184     gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G[mpcc_id]);
0185     gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G[mpcc_id]);
0186     gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R[mpcc_id]);
0187     gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R[mpcc_id]);
0188     gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMA_REGION_0_1[mpcc_id]);
0189     gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMA_REGION_32_33[mpcc_id]);
0190 
0191     cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);
0192 }
0193 
0194 /*program blnd lut RAM B*/
0195 static void mpc32_program_post1dlutb_settings(
0196         struct mpc *mpc,
0197         uint32_t mpcc_id,
0198         const struct pwl_params *params)
0199 {
0200     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0201     struct dcn3_xfer_func_reg gam_regs;
0202 
0203     mpc32_post1dlut_get_reg_field(mpc30, &gam_regs);
0204 
0205     gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_B[mpcc_id]);
0206     gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_G[mpcc_id]);
0207     gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_R[mpcc_id]);
0208     gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B[mpcc_id]);
0209     gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G[mpcc_id]);
0210     gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R[mpcc_id]);
0211     gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B[mpcc_id]);
0212     gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B[mpcc_id]);
0213     gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G[mpcc_id]);
0214     gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G[mpcc_id]);
0215     gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R[mpcc_id]);
0216     gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R[mpcc_id]);
0217     gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMB_REGION_0_1[mpcc_id]);
0218     gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMB_REGION_32_33[mpcc_id]);
0219 
0220     cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);
0221 }
0222 
0223 static void mpc32_program_post1dlut_pwl(
0224         struct mpc *mpc,
0225         uint32_t mpcc_id,
0226         const struct pwl_result_data *rgb,
0227         uint32_t num)
0228 {
0229     uint32_t i;
0230     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0231     uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
0232     uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
0233     uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
0234 
0235     if (is_rgb_equal(rgb, num)) {
0236         for (i = 0 ; i < num; i++)
0237             REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
0238         REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
0239     } else {
0240         REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 4);
0241         for (i = 0 ; i < num; i++)
0242             REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
0243         REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
0244 
0245         REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 2);
0246         for (i = 0 ; i < num; i++)
0247             REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].green_reg);
0248         REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_green);
0249 
0250         REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 1);
0251         for (i = 0 ; i < num; i++)
0252             REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].blue_reg);
0253         REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_blue);
0254     }
0255 }
0256 
0257 static bool mpc32_program_post1dlut(
0258         struct mpc *mpc,
0259         const struct pwl_params *params,
0260         uint32_t mpcc_id)
0261 {
0262     enum dc_lut_mode current_mode;
0263     enum dc_lut_mode next_mode;
0264     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0265 
0266     if (params == NULL) {
0267         REG_SET(MPCC_MCM_1DLUT_CONTROL[mpcc_id], 0, MPCC_MCM_1DLUT_MODE, 0);
0268         if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm)
0269             mpc32_power_on_blnd_lut(mpc, mpcc_id, false);
0270         return false;
0271     }
0272 
0273     current_mode = mpc32_get_post1dlut_current(mpc, mpcc_id);
0274     if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
0275         next_mode = LUT_RAM_A;
0276     else
0277         next_mode = LUT_RAM_B;
0278 
0279     mpc32_power_on_blnd_lut(mpc, mpcc_id, true);
0280     mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);
0281 
0282     if (next_mode == LUT_RAM_A)
0283         mpc32_program_post1dluta_settings(mpc, mpcc_id, params);
0284     else
0285         mpc32_program_post1dlutb_settings(mpc, mpcc_id, params);
0286 
0287     mpc32_program_post1dlut_pwl(
0288             mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);
0289 
0290     REG_UPDATE_2(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
0291             MPCC_MCM_1DLUT_MODE, 2,
0292             MPCC_MCM_1DLUT_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
0293 
0294     return true;
0295 }
0296 
0297 static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id)
0298 {
0299     enum dc_lut_mode mode;
0300     uint32_t state_mode;
0301     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0302 
0303     REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode);
0304 
0305     switch (state_mode) {
0306     case 0:
0307         mode = LUT_BYPASS;
0308         break;
0309     case 1:
0310         mode = LUT_RAM_A;
0311         break;
0312     case 2:
0313         mode = LUT_RAM_B;
0314         break;
0315     default:
0316         mode = LUT_BYPASS;
0317         break;
0318     }
0319 
0320     return mode;
0321 }
0322 
0323 
0324 static void mpc32_configure_shaper_lut(
0325         struct mpc *mpc,
0326         bool is_ram_a,
0327         uint32_t mpcc_id)
0328 {
0329     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0330 
0331     REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
0332             MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7);
0333     REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
0334             MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
0335     REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0);
0336 }
0337 
0338 
0339 static void mpc32_program_shaper_luta_settings(
0340         struct mpc *mpc,
0341         const struct pwl_params *params,
0342         uint32_t mpcc_id)
0343 {
0344     const struct gamma_curve *curve;
0345     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0346 
0347     REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0,
0348         MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
0349         MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
0350     REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0,
0351             MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
0352             MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
0353     REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0,
0354             MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
0355             MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
0356 
0357     REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0,
0358             MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
0359             MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
0360     REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0,
0361             MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
0362             MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
0363     REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0,
0364             MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
0365             MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
0366 
0367     curve = params->arr_curve_points;
0368     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0,
0369         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0370         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0371         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0372         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0373 
0374     curve += 2;
0375     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0,
0376         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0377         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0378         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0379         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0380 
0381     curve += 2;
0382     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0,
0383         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0384         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0385         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0386         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0387 
0388     curve += 2;
0389     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0,
0390         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0391         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0392         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0393         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0394 
0395     curve += 2;
0396     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0,
0397         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0398         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0399         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0400         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0401 
0402     curve += 2;
0403     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0,
0404         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0405         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0406         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0407         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0408 
0409     curve += 2;
0410     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0,
0411         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0412         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0413         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0414         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0415 
0416     curve += 2;
0417     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0,
0418         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0419         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0420         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0421         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0422 
0423 
0424     curve += 2;
0425     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0,
0426         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0427         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0428         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0429         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0430 
0431     curve += 2;
0432     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0,
0433         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0434         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0435         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0436         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0437 
0438     curve += 2;
0439     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0,
0440         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0441         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0442         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0443         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0444 
0445     curve += 2;
0446     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0,
0447         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0448         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0449         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0450         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0451 
0452     curve += 2;
0453     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0,
0454         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0455         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0456         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0457         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0458 
0459     curve += 2;
0460     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0,
0461             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0462             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0463             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0464             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0465 
0466     curve += 2;
0467     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0,
0468         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0469         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0470         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0471         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0472 
0473     curve += 2;
0474     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0,
0475         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0476         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0477         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0478         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0479 
0480     curve += 2;
0481     REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0,
0482         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0483         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0484         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0485         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0486 }
0487 
0488 
0489 static void mpc32_program_shaper_lutb_settings(
0490         struct mpc *mpc,
0491         const struct pwl_params *params,
0492         uint32_t mpcc_id)
0493 {
0494     const struct gamma_curve *curve;
0495     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0496 
0497     REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0,
0498         MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
0499         MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
0500     REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0,
0501             MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
0502             MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
0503     REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0,
0504             MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
0505             MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
0506 
0507     REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0,
0508             MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
0509             MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
0510     REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0,
0511             MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
0512             MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
0513     REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0,
0514             MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
0515             MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
0516 
0517     curve = params->arr_curve_points;
0518     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0,
0519         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0520         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0521         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0522         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0523 
0524     curve += 2;
0525     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0,
0526             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0527             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0528             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0529             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0530 
0531 
0532     curve += 2;
0533     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0,
0534             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0535             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0536             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0537             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0538 
0539     curve += 2;
0540     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0,
0541             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0542             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0543             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0544             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0545 
0546     curve += 2;
0547     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0,
0548         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0549         MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0550         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0551         MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0552 
0553     curve += 2;
0554     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0,
0555             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0556             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0557             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0558             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0559 
0560     curve += 2;
0561     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0,
0562             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0563             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0564             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0565             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0566 
0567     curve += 2;
0568     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0,
0569             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0570             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0571             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0572             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0573 
0574 
0575     curve += 2;
0576     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0,
0577             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0578             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0579             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0580             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0581 
0582     curve += 2;
0583     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0,
0584             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0585             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0586             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0587             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0588 
0589     curve += 2;
0590     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0,
0591             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0592             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0593             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0594             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0595 
0596     curve += 2;
0597     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0,
0598             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0599             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0600             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0601             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0602 
0603     curve += 2;
0604     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0,
0605             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0606             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0607             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0608             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0609 
0610     curve += 2;
0611     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0,
0612             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0613             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0614             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0615             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0616 
0617     curve += 2;
0618     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0,
0619             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0620             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0621             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0622             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0623 
0624     curve += 2;
0625     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0,
0626             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0627             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0628             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0629             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0630 
0631     curve += 2;
0632     REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0,
0633             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0634             MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0635             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0636             MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0637 }
0638 
0639 
0640 static void mpc32_program_shaper_lut(
0641         struct mpc *mpc,
0642         const struct pwl_result_data *rgb,
0643         uint32_t num,
0644         uint32_t mpcc_id)
0645 {
0646     uint32_t i, red, green, blue;
0647     uint32_t  red_delta, green_delta, blue_delta;
0648     uint32_t  red_value, green_value, blue_value;
0649 
0650     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0651 
0652     for (i = 0 ; i < num; i++) {
0653 
0654         red   = rgb[i].red_reg;
0655         green = rgb[i].green_reg;
0656         blue  = rgb[i].blue_reg;
0657 
0658         red_delta   = rgb[i].delta_red_reg;
0659         green_delta = rgb[i].delta_green_reg;
0660         blue_delta  = rgb[i].delta_blue_reg;
0661 
0662         red_value   = ((red_delta   & 0x3ff) << 14) | (red   & 0x3fff);
0663         green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
0664         blue_value  = ((blue_delta  & 0x3ff) << 14) | (blue  & 0x3fff);
0665 
0666         REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, red_value);
0667         REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, green_value);
0668         REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, blue_value);
0669     }
0670 
0671 }
0672 
0673 
0674 static void mpc32_power_on_shaper_3dlut(
0675         struct mpc *mpc,
0676         uint32_t mpcc_id,
0677         bool power_on)
0678 {
0679     uint32_t power_status_shaper = 2;
0680     uint32_t power_status_3dlut  = 2;
0681     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0682     int max_retries = 10;
0683 
0684     REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
0685     MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0);
0686     /* wait for memory to fully power up */
0687     if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
0688         REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
0689         REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
0690     }
0691 
0692     /*read status is not mandatory, it is just for debugging*/
0693     REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper);
0694     REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
0695 
0696     if (power_status_shaper != 0 && power_on == true)
0697         BREAK_TO_DEBUGGER();
0698 
0699     if (power_status_3dlut != 0 && power_on == true)
0700         BREAK_TO_DEBUGGER();
0701 }
0702 
0703 
0704 bool mpc32_program_shaper(
0705         struct mpc *mpc,
0706         const struct pwl_params *params,
0707         uint32_t mpcc_id)
0708 {
0709     enum dc_lut_mode current_mode;
0710     enum dc_lut_mode next_mode;
0711 
0712     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0713 
0714     if (params == NULL) {
0715         REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, 0);
0716         return false;
0717     }
0718 
0719     if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
0720         mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
0721 
0722     current_mode = mpc32_get_shaper_current(mpc, mpcc_id);
0723 
0724     if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
0725         next_mode = LUT_RAM_B;
0726     else
0727         next_mode = LUT_RAM_A;
0728 
0729     mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A ? true:false, mpcc_id);
0730 
0731     if (next_mode == LUT_RAM_A)
0732         mpc32_program_shaper_luta_settings(mpc, params, mpcc_id);
0733     else
0734         mpc32_program_shaper_lutb_settings(mpc, params, mpcc_id);
0735 
0736     mpc32_program_shaper_lut(
0737             mpc, params->rgb_resulted, params->hw_points_num, mpcc_id);
0738 
0739     REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
0740     mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
0741 
0742     return true;
0743 }
0744 
0745 
0746 static enum dc_lut_mode get3dlut_config(
0747             struct mpc *mpc,
0748             bool *is_17x17x17,
0749             bool *is_12bits_color_channel,
0750             int mpcc_id)
0751 {
0752     uint32_t i_mode, i_enable_10bits, lut_size;
0753     enum dc_lut_mode mode;
0754     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0755 
0756     REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id],
0757             MPCC_MCM_3DLUT_MODE_CURRENT,  &i_mode);
0758 
0759     REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
0760             MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits);
0761 
0762     switch (i_mode) {
0763     case 0:
0764         mode = LUT_BYPASS;
0765         break;
0766     case 1:
0767         mode = LUT_RAM_A;
0768         break;
0769     case 2:
0770         mode = LUT_RAM_B;
0771         break;
0772     default:
0773         mode = LUT_BYPASS;
0774         break;
0775     }
0776     if (i_enable_10bits > 0)
0777         *is_12bits_color_channel = false;
0778     else
0779         *is_12bits_color_channel = true;
0780 
0781     REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size);
0782 
0783     if (lut_size == 0)
0784         *is_17x17x17 = true;
0785     else
0786         *is_17x17x17 = false;
0787 
0788     return mode;
0789 }
0790 
0791 
0792 static void mpc32_select_3dlut_ram(
0793         struct mpc *mpc,
0794         enum dc_lut_mode mode,
0795         bool is_color_channel_12bits,
0796         uint32_t mpcc_id)
0797 {
0798     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0799 
0800     REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
0801         MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
0802         MPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1);
0803 }
0804 
0805 
0806 static void mpc32_select_3dlut_ram_mask(
0807         struct mpc *mpc,
0808         uint32_t ram_selection_mask,
0809         uint32_t mpcc_id)
0810 {
0811     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0812 
0813     REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK,
0814             ram_selection_mask);
0815     REG_SET(MPCC_MCM_3DLUT_INDEX[mpcc_id], 0, MPCC_MCM_3DLUT_INDEX, 0);
0816 }
0817 
0818 
0819 static void mpc32_set3dlut_ram12(
0820         struct mpc *mpc,
0821         const struct dc_rgb *lut,
0822         uint32_t entries,
0823         uint32_t mpcc_id)
0824 {
0825     uint32_t i, red, green, blue, red1, green1, blue1;
0826     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0827 
0828     for (i = 0 ; i < entries; i += 2) {
0829         red   = lut[i].red<<4;
0830         green = lut[i].green<<4;
0831         blue  = lut[i].blue<<4;
0832         red1   = lut[i+1].red<<4;
0833         green1 = lut[i+1].green<<4;
0834         blue1  = lut[i+1].blue<<4;
0835 
0836         REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
0837                 MPCC_MCM_3DLUT_DATA0, red,
0838                 MPCC_MCM_3DLUT_DATA1, red1);
0839 
0840         REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
0841                 MPCC_MCM_3DLUT_DATA0, green,
0842                 MPCC_MCM_3DLUT_DATA1, green1);
0843 
0844         REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
0845                 MPCC_MCM_3DLUT_DATA0, blue,
0846                 MPCC_MCM_3DLUT_DATA1, blue1);
0847     }
0848 }
0849 
0850 
0851 static void mpc32_set3dlut_ram10(
0852         struct mpc *mpc,
0853         const struct dc_rgb *lut,
0854         uint32_t entries,
0855         uint32_t mpcc_id)
0856 {
0857     uint32_t i, red, green, blue, value;
0858     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0859 
0860     for (i = 0; i < entries; i++) {
0861         red   = lut[i].red;
0862         green = lut[i].green;
0863         blue  = lut[i].blue;
0864         //should we shift red 22bit and green 12?
0865         value = (red<<20) | (green<<10) | blue;
0866 
0867         REG_SET(MPCC_MCM_3DLUT_DATA_30BIT[mpcc_id], 0, MPCC_MCM_3DLUT_DATA_30BIT, value);
0868     }
0869 
0870 }
0871 
0872 
0873 static void mpc32_set_3dlut_mode(
0874         struct mpc *mpc,
0875         enum dc_lut_mode mode,
0876         bool is_color_channel_12bits,
0877         bool is_lut_size17x17x17,
0878         uint32_t mpcc_id)
0879 {
0880     uint32_t lut_mode;
0881     struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
0882 
0883     // set default 3DLUT to pre-blend
0884     // TODO: implement movable CM location
0885     REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id], MPCC_MOVABLE_CM_LOCATION_CNTL, 0);
0886 
0887     if (mode == LUT_BYPASS)
0888         lut_mode = 0;
0889     else if (mode == LUT_RAM_A)
0890         lut_mode = 1;
0891     else
0892         lut_mode = 2;
0893 
0894     REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id],
0895             MPCC_MCM_3DLUT_MODE, lut_mode,
0896             MPCC_MCM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
0897 }
0898 
0899 
0900 bool mpc32_program_3dlut(
0901         struct mpc *mpc,
0902         const struct tetrahedral_params *params,
0903         int mpcc_id)
0904 {
0905     enum dc_lut_mode mode;
0906     bool is_17x17x17;
0907     bool is_12bits_color_channel;
0908     const struct dc_rgb *lut0;
0909     const struct dc_rgb *lut1;
0910     const struct dc_rgb *lut2;
0911     const struct dc_rgb *lut3;
0912     int lut_size0;
0913     int lut_size;
0914 
0915     if (params == NULL) {
0916         mpc32_set_3dlut_mode(mpc, LUT_BYPASS, false, false, mpcc_id);
0917         return false;
0918     }
0919     mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
0920 
0921     mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id);
0922 
0923     if (mode == LUT_BYPASS || mode == LUT_RAM_B)
0924         mode = LUT_RAM_A;
0925     else
0926         mode = LUT_RAM_B;
0927 
0928     is_17x17x17 = !params->use_tetrahedral_9;
0929     is_12bits_color_channel = params->use_12bits;
0930     if (is_17x17x17) {
0931         lut0 = params->tetrahedral_17.lut0;
0932         lut1 = params->tetrahedral_17.lut1;
0933         lut2 = params->tetrahedral_17.lut2;
0934         lut3 = params->tetrahedral_17.lut3;
0935         lut_size0 = sizeof(params->tetrahedral_17.lut0)/
0936                     sizeof(params->tetrahedral_17.lut0[0]);
0937         lut_size  = sizeof(params->tetrahedral_17.lut1)/
0938                     sizeof(params->tetrahedral_17.lut1[0]);
0939     } else {
0940         lut0 = params->tetrahedral_9.lut0;
0941         lut1 = params->tetrahedral_9.lut1;
0942         lut2 = params->tetrahedral_9.lut2;
0943         lut3 = params->tetrahedral_9.lut3;
0944         lut_size0 = sizeof(params->tetrahedral_9.lut0)/
0945                 sizeof(params->tetrahedral_9.lut0[0]);
0946         lut_size  = sizeof(params->tetrahedral_9.lut1)/
0947                 sizeof(params->tetrahedral_9.lut1[0]);
0948         }
0949 
0950     mpc32_select_3dlut_ram(mpc, mode,
0951                 is_12bits_color_channel, mpcc_id);
0952     mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);
0953     if (is_12bits_color_channel)
0954         mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);
0955     else
0956         mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);
0957 
0958     mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);
0959     if (is_12bits_color_channel)
0960         mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);
0961     else
0962         mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);
0963 
0964     mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);
0965     if (is_12bits_color_channel)
0966         mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);
0967     else
0968         mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);
0969 
0970     mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);
0971     if (is_12bits_color_channel)
0972         mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);
0973     else
0974         mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);
0975 
0976     mpc32_set_3dlut_mode(mpc, mode, is_12bits_color_channel,
0977                     is_17x17x17, mpcc_id);
0978 
0979     if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
0980         mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
0981 
0982     return true;
0983 }
0984 
0985 const struct mpc_funcs dcn32_mpc_funcs = {
0986     .read_mpcc_state = mpc1_read_mpcc_state,
0987     .insert_plane = mpc1_insert_plane,
0988     .remove_mpcc = mpc1_remove_mpcc,
0989     .mpc_init = mpc32_mpc_init,
0990     .mpc_init_single_inst = mpc1_mpc_init_single_inst,
0991     .update_blending = mpc2_update_blending,
0992     .cursor_lock = mpc1_cursor_lock,
0993     .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
0994     .wait_for_idle = mpc2_assert_idle_mpcc,
0995     .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
0996     .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
0997     .set_denorm =  mpc3_set_denorm,
0998     .set_denorm_clamp = mpc3_set_denorm_clamp,
0999     .set_output_csc = mpc3_set_output_csc,
1000     .set_ocsc_default = mpc3_set_ocsc_default,
1001     .set_output_gamma = mpc3_set_output_gamma,
1002     .insert_plane_to_secondary = NULL,
1003     .remove_mpcc_from_secondary =  NULL,
1004     .set_dwb_mux = mpc3_set_dwb_mux,
1005     .disable_dwb_mux = mpc3_disable_dwb_mux,
1006     .is_dwb_idle = mpc3_is_dwb_idle,
1007     .set_out_rate_control = mpc3_set_out_rate_control,
1008     .set_gamut_remap = mpc3_set_gamut_remap,
1009     .program_shaper = mpc32_program_shaper,
1010     .program_3dlut = mpc32_program_3dlut,
1011     .program_1dlut = mpc32_program_post1dlut,
1012     .acquire_rmu = NULL,
1013     .release_rmu = NULL,
1014     .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,
1015     .get_mpc_out_mux = mpc1_get_mpc_out_mux,
1016     .set_bg_color = mpc1_set_bg_color,
1017 };
1018 
1019 
1020 void dcn32_mpc_construct(struct dcn30_mpc *mpc30,
1021     struct dc_context *ctx,
1022     const struct dcn30_mpc_registers *mpc_regs,
1023     const struct dcn30_mpc_shift *mpc_shift,
1024     const struct dcn30_mpc_mask *mpc_mask,
1025     int num_mpcc,
1026     int num_rmu)
1027 {
1028     int i;
1029 
1030     mpc30->base.ctx = ctx;
1031 
1032     mpc30->base.funcs = &dcn32_mpc_funcs;
1033 
1034     mpc30->mpc_regs = mpc_regs;
1035     mpc30->mpc_shift = mpc_shift;
1036     mpc30->mpc_mask = mpc_mask;
1037 
1038     mpc30->mpcc_in_use_mask = 0;
1039     mpc30->num_mpcc = num_mpcc;
1040     mpc30->num_rmu = num_rmu;
1041 
1042     for (i = 0; i < MAX_MPCC; i++)
1043         mpc3_init_mpcc(&mpc30->base.mpcc_array[i], i);
1044 }
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