dc/dcn32/dcn32_mmhubbub.c

0001 /*
0002  * Copyright 2022 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026
0027 #include "reg_helper.h"
0028 #include "resource.h"
0029 #include "mcif_wb.h"
0030 #include "dcn32_mmhubbub.h"
0031
0032
0033 #define REG(reg)\
0034     mcif_wb30->mcif_wb_regs->reg
0035
0036 #define CTX \
0037     mcif_wb30->base.ctx
0038
0039 #undef FN
0040 #define FN(reg_name, field_name) \
0041     mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name
0042
0043 #define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8
0044 #define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40
0045
0046 /* wbif programming guide:
0047  * 1. set up wbif parameter:
0048  *    unsigned long long   luma_address[4];       //4 frame buffer
0049  *    unsigned long long   chroma_address[4];
0050  *    unsigned int     luma_pitch;
0051  *    unsigned int     chroma_pitch;
0052  *    unsigned int         warmup_pitch=0x10;     //256B align, the page size is 4KB when it is 0x10
0053  *    unsigned int     slice_lines;           //slice size
0054  *    unsigned int         time_per_pixel;        // time per pixel, in ns
0055  *    unsigned int         arbitration_slice;     // 0: 2048 bytes 1: 4096 bytes 2: 8192 Bytes
0056  *    unsigned int         max_scaled_time;       // used for QOS generation
0057  *    unsigned int         swlock=0x0;
0058  *    unsigned int         cli_watermark[4];      //4 group urgent watermark
0059  *    unsigned int         pstate_watermark[4];   //4 group pstate watermark
0060  *    unsigned int         sw_int_en;             // Software interrupt enable, frame end and overflow
0061  *    unsigned int         sw_slice_int_en;       // slice end interrupt enable
0062  *    unsigned int         sw_overrun_int_en;     // overrun error interrupt enable
0063  *    unsigned int         vce_int_en;            // VCE interrupt enable, frame end and overflow
0064  *    unsigned int         vce_slice_int_en;      // VCE slice end interrupt enable, frame end and overflow
0065  *
0066  * 2. configure wbif register
0067  *    a. call mmhubbub_config_wbif()
0068  *
0069  * 3. Enable wbif
0070  *    call set_wbif_bufmgr_enable();
0071  *
0072  * 4. wbif_dump_status(), option, for debug purpose
0073  *    the bufmgr status can show the progress of write back, can be used for debug purpose
0074  */
0075
0076 static void mmhubbub32_warmup_mcif(struct mcif_wb *mcif_wb,
0077         struct mcif_warmup_params *params)
0078 {
0079     struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb);
0080     union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5};
0081
0082     /* Set base address and region size for warmup */
0083     REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.high_part);
0084     REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_LOW, 0, MMHUBBUB_WARMUP_BASE_ADDR_LOW, start_address_shift.low_part);
0085     REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5);
0086 //  REG_SET(MMHUBBUB_WARMUP_P_VMID, 0, MMHUBBUB_WARMUP_P_VMID, params->p_vmid);
0087
0088     /* Set address increment and enable warmup */
0089     REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true,
0090             MMHUBBUB_WARMUP_SW_INT_EN, true,
0091             MMHUBBUB_WARMUP_INC_ADDR, params->address_increment >> 5);
0092
0093     /* Wait for an interrupt to signal warmup is completed */
0094     REG_WAIT(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, 1, 20, 100);
0095
0096     /* Acknowledge interrupt */
0097     REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1);
0098
0099     /* Disable warmup */
0100     REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false);
0101 }
0102
0103 void mmhubbub32_config_mcif_buf(struct mcif_wb *mcif_wb,
0104         struct mcif_buf_params *params,
0105         unsigned int dest_height)
0106 {
0107     struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb);
0108
0109     /* buffer address for packing mode or Luma in planar mode */
0110     REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));
0111     REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));
0112
0113     /* buffer address for Chroma in planar mode (unused in packing mode) */
0114     REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));
0115     REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));
0116
0117     /* buffer address for packing mode or Luma in planar mode */
0118     REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));
0119     REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));
0120
0121     /* buffer address for Chroma in planar mode (unused in packing mode) */
0122     REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1]));
0123     REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1]));
0124
0125     /* buffer address for packing mode or Luma in planar mode */
0126     REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2]));
0127     REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2]));
0128
0129     /* buffer address for Chroma in planar mode (unused in packing mode) */
0130     REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2]));
0131     REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2]));
0132
0133     /* buffer address for packing mode or Luma in planar mode */
0134     REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3]));
0135     REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3]));
0136
0137     /* buffer address for Chroma in planar mode (unused in packing mode) */
0138     REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3]));
0139     REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3]));
0140
0141     /* setup luma & chroma size
0142      * should be enough to contain a whole frame Luma data,
0143      * the programmed value is frame buffer size [27:8], 256-byte aligned
0144      */
0145     REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, (params->luma_pitch>>8) * dest_height);
0146     REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, (params->chroma_pitch>>8) * dest_height);
0147
0148     /* enable address fence */
0149     REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1);
0150
0151     /* setup pitch, the programmed value is [15:8], 256B align */
0152     REG_UPDATE_2(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, params->luma_pitch >> 8,
0153             MCIF_WB_BUF_CHROMA_PITCH, params->chroma_pitch >> 8);
0154 }
0155
0156 static void mmhubbub32_config_mcif_arb(struct mcif_wb *mcif_wb,
0157         struct mcif_arb_params *params)
0158 {
0159     struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb);
0160
0161     /* Programmed by the video driver based on the CRTC timing (for DWB) */
0162     REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, params->time_per_pixel);
0163
0164     /* Programming dwb watermark */
0165     /* Watermark to generate urgent in MCIF_WB_CLI, value is determined by MCIF_WB_CLI_WATERMARK_MASK. */
0166     /* Program in ns. A formula will be provided in the pseudo code to calculate the value. */
0167     REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x0);
0168     /* urgent_watermarkA */
0169     REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[0]);
0170     REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x1);
0171     /* urgent_watermarkB */
0172     REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[1]);
0173     REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x2);
0174     /* urgent_watermarkC */
0175     REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[2]);
0176     REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x3);
0177     /* urgent_watermarkD */
0178     REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[3]);
0179
0180     /* Programming nb pstate watermark */
0181     /* nbp_state_change_watermarkA */
0182     REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0);
0183     REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
0184             NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[0]);
0185     /* nbp_state_change_watermarkB */
0186     REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1);
0187     REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
0188             NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[1]);
0189     /* nbp_state_change_watermarkC */
0190     REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2);
0191     REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
0192             NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[2]);
0193     /* nbp_state_change_watermarkD */
0194     REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);
0195     REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
0196             NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[3]);
0197
0198     /* dram_speed_change_duration - register removed */
0199     //REG_UPDATE(MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI,
0200     //      MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, params->dram_speed_change_duration);
0201
0202     /* max_scaled_time */
0203     REG_UPDATE(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, params->max_scaled_time);
0204
0205     /* slice_lines */
0206     REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1);
0207
0208     /* Set arbitration unit for Luma/Chroma */
0209     /* arb_unit=2 should be chosen for more efficiency */
0210     /* Arbitration size, 0: 2048 bytes 1: 4096 bytes 2: 8192 Bytes */
0211     REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE,  params->arbitration_slice);
0212 }
0213
0214 const struct mcif_wb_funcs dcn32_mmhubbub_funcs = {
0215     .warmup_mcif        = mmhubbub32_warmup_mcif,
0216     .enable_mcif        = mmhubbub2_enable_mcif,
0217     .disable_mcif       = mmhubbub2_disable_mcif,
0218     .config_mcif_buf    = mmhubbub32_config_mcif_buf,
0219     .config_mcif_arb    = mmhubbub32_config_mcif_arb,
0220     .config_mcif_irq    = mmhubbub2_config_mcif_irq,
0221     .dump_frame         = mcifwb2_dump_frame,
0222 };
0223
0224 void dcn32_mmhubbub_construct(struct dcn30_mmhubbub *mcif_wb30,
0225         struct dc_context *ctx,
0226         const struct dcn30_mmhubbub_registers *mcif_wb_regs,
0227         const struct dcn30_mmhubbub_shift *mcif_wb_shift,
0228         const struct dcn30_mmhubbub_mask *mcif_wb_mask,
0229         int inst)
0230 {
0231     mcif_wb30->base.ctx = ctx;
0232
0233     mcif_wb30->base.inst = inst;
0234     mcif_wb30->base.funcs = &dcn32_mmhubbub_funcs;
0235
0236     mcif_wb30->mcif_wb_regs = mcif_wb_regs;
0237     mcif_wb30->mcif_wb_shift = mcif_wb_shift;
0238     mcif_wb30->mcif_wb_mask = mcif_wb_mask;
0239 }