dc/dcn32/dcn32_hwseq.h

0001 /*
0002 * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_HWSS_DCN32_H__
0027 #define __DC_HWSS_DCN32_H__
0028
0029 #include "hw_sequencer_private.h"
0030
0031 struct dc;
0032
0033 void dcn32_dsc_pg_control(
0034         struct dce_hwseq *hws,
0035         unsigned int dsc_inst,
0036         bool power_on);
0037
0038 void dcn32_enable_power_gating_plane(
0039     struct dce_hwseq *hws,
0040     bool enable);
0041
0042 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
0043
0044 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
0045
0046 void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
0047
0048 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
0049
0050 bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx,
0051                 const struct dc_plane_state *plane_state);
0052
0053 bool dcn32_set_input_transfer_func(struct dc *dc,
0054                 struct pipe_ctx *pipe_ctx,
0055                 const struct dc_plane_state *plane_state);
0056
0057 bool dcn32_set_output_transfer_func(struct dc *dc,
0058                 struct pipe_ctx *pipe_ctx,
0059                 const struct dc_stream_state *stream);
0060
0061 void dcn32_init_hw(struct dc *dc);
0062
0063 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
0064
0065 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
0066
0067 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context);
0068
0069 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
0070
0071 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
0072
0073 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
0074
0075 void dcn32_subvp_pipe_control_lock(struct dc *dc,
0076         struct dc_state *context,
0077         bool lock,
0078         bool should_lock_all_pipes,
0079         struct pipe_ctx *top_pipe_to_program,
0080         bool subvp_prev_use);
0081
0082 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
0083         struct dc_link_settings *link_settings);
0084
0085 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
0086
0087 #endif /* __DC_HWSS_DCN32_H__ */