Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 
0027 #include "dm_services.h"
0028 #include "dm_helpers.h"
0029 #include "core_types.h"
0030 #include "resource.h"
0031 #include "dccg.h"
0032 #include "dce/dce_hwseq.h"
0033 #include "dcn30/dcn30_cm_common.h"
0034 #include "reg_helper.h"
0035 #include "abm.h"
0036 #include "hubp.h"
0037 #include "dchubbub.h"
0038 #include "timing_generator.h"
0039 #include "opp.h"
0040 #include "ipp.h"
0041 #include "mpc.h"
0042 #include "mcif_wb.h"
0043 #include "dc_dmub_srv.h"
0044 #include "link_hwss.h"
0045 #include "dpcd_defs.h"
0046 #include "dcn32_hwseq.h"
0047 #include "clk_mgr.h"
0048 #include "dsc.h"
0049 #include "dcn20/dcn20_optc.h"
0050 #include "dmub_subvp_state.h"
0051 #include "dce/dmub_hw_lock_mgr.h"
0052 #include "dc_link_dp.h"
0053 #include "dmub/inc/dmub_subvp_state.h"
0054 
0055 #define DC_LOGGER_INIT(logger)
0056 
0057 #define CTX \
0058     hws->ctx
0059 #define REG(reg)\
0060     hws->regs->reg
0061 #define DC_LOGGER \
0062         dc->ctx->logger
0063 
0064 
0065 #undef FN
0066 #define FN(reg_name, field_name) \
0067     hws->shifts->field_name, hws->masks->field_name
0068 
0069 void dcn32_dsc_pg_control(
0070         struct dce_hwseq *hws,
0071         unsigned int dsc_inst,
0072         bool power_on)
0073 {
0074     uint32_t power_gate = power_on ? 0 : 1;
0075     uint32_t pwr_status = power_on ? 0 : 2;
0076     uint32_t org_ip_request_cntl = 0;
0077 
0078     if (hws->ctx->dc->debug.disable_dsc_power_gate)
0079         return;
0080 
0081     REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
0082     if (org_ip_request_cntl == 0)
0083         REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
0084 
0085     switch (dsc_inst) {
0086     case 0: /* DSC0 */
0087         REG_UPDATE(DOMAIN16_PG_CONFIG,
0088                 DOMAIN_POWER_GATE, power_gate);
0089 
0090         REG_WAIT(DOMAIN16_PG_STATUS,
0091                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
0092                 1, 1000);
0093         break;
0094     case 1: /* DSC1 */
0095         REG_UPDATE(DOMAIN17_PG_CONFIG,
0096                 DOMAIN_POWER_GATE, power_gate);
0097 
0098         REG_WAIT(DOMAIN17_PG_STATUS,
0099                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
0100                 1, 1000);
0101         break;
0102     case 2: /* DSC2 */
0103         REG_UPDATE(DOMAIN18_PG_CONFIG,
0104                 DOMAIN_POWER_GATE, power_gate);
0105 
0106         REG_WAIT(DOMAIN18_PG_STATUS,
0107                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
0108                 1, 1000);
0109         break;
0110     case 3: /* DSC3 */
0111         REG_UPDATE(DOMAIN19_PG_CONFIG,
0112                 DOMAIN_POWER_GATE, power_gate);
0113 
0114         REG_WAIT(DOMAIN19_PG_STATUS,
0115                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
0116                 1, 1000);
0117         break;
0118     default:
0119         BREAK_TO_DEBUGGER();
0120         break;
0121     }
0122 
0123     if (org_ip_request_cntl == 0)
0124         REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
0125 }
0126 
0127 
0128 void dcn32_enable_power_gating_plane(
0129     struct dce_hwseq *hws,
0130     bool enable)
0131 {
0132     bool force_on = true; /* disable power gating */
0133 
0134     if (enable)
0135         force_on = false;
0136 
0137     /* DCHUBP0/1/2/3 */
0138     REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
0139     REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
0140     REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
0141     REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
0142 
0143     /* DCS0/1/2/3 */
0144     REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
0145     REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
0146     REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
0147     REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
0148 }
0149 
0150 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
0151 {
0152     uint32_t power_gate = power_on ? 0 : 1;
0153     uint32_t pwr_status = power_on ? 0 : 2;
0154 
0155     if (hws->ctx->dc->debug.disable_hubp_power_gate)
0156         return;
0157 
0158     if (REG(DOMAIN0_PG_CONFIG) == 0)
0159         return;
0160 
0161     switch (hubp_inst) {
0162     case 0:
0163         REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
0164         REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
0165         break;
0166     case 1:
0167         REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
0168         REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
0169         break;
0170     case 2:
0171         REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
0172         REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
0173         break;
0174     case 3:
0175         REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
0176         REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
0177         break;
0178     default:
0179         BREAK_TO_DEBUGGER();
0180         break;
0181     }
0182 }
0183 
0184 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
0185 {
0186     int i;
0187 
0188     /* First, check no-memory-request case */
0189     for (i = 0; i < dc->current_state->stream_count; i++) {
0190         if (dc->current_state->stream_status[i].plane_count)
0191             /* Fail eligibility on a visible stream */
0192             break;
0193     }
0194 
0195     if (i == dc->current_state->stream_count)
0196         return true;
0197 
0198     return false;
0199 }
0200 
0201 /* This function takes in the start address and surface size to be cached in CAB
0202  * and calculates the total number of cache lines required to store the surface.
0203  * The number of cache lines used for each surface is calculated independently of
0204  * one another. For example, if there is a primary surface(1), meta surface(2), and
0205  * cursor(3), this function should be called 3 times to calculate the number of cache
0206  * lines used for each of those surfaces.
0207  */
0208 static uint32_t dcn32_cache_lines_for_surface(struct dc *dc, uint32_t surface_size, uint64_t start_address)
0209 {
0210     uint32_t lines_used = 1;
0211     uint32_t num_cached_bytes = 0;
0212     uint32_t remaining_size = 0;
0213     uint32_t cache_line_size = dc->caps.cache_line_size;
0214     uint32_t remainder = 0;
0215 
0216     /* 1. Calculate surface size minus the number of bytes stored
0217      * in the first cache line (all bytes in first cache line might
0218      * not be fully used).
0219      */
0220     div_u64_rem(start_address, cache_line_size, &remainder);
0221     num_cached_bytes = cache_line_size - remainder;
0222     remaining_size = surface_size - num_cached_bytes;
0223 
0224     /* 2. Calculate number of cache lines that will be fully used with
0225      * the remaining number of bytes to be stored.
0226      */
0227     lines_used += (remaining_size / cache_line_size);
0228 
0229     /* 3. Check if we need an extra line due to the remaining size not being
0230      * a multiple of CACHE_LINE_SIZE.
0231      */
0232     if (remaining_size % cache_line_size > 0)
0233         lines_used++;
0234 
0235     return lines_used;
0236 }
0237 
0238 /* This function loops through every surface that needs to be cached in CAB for SS,
0239  * and calculates the total number of ways required to store all surfaces (primary,
0240  * meta, cursor).
0241  */
0242 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
0243 {
0244     uint8_t i, j;
0245     struct dc_stream_state *stream = NULL;
0246     struct dc_plane_state *plane = NULL;
0247     uint32_t surface_size = 0;
0248     uint32_t cursor_size = 0;
0249     uint32_t cache_lines_used = 0;
0250     uint32_t total_lines = 0;
0251     uint32_t lines_per_way = 0;
0252     uint32_t num_ways = 0;
0253     uint32_t prev_addr_low = 0;
0254 
0255     for (i = 0; i < ctx->stream_count; i++) {
0256         stream = ctx->streams[i];
0257 
0258         // Don't include PSR surface in the total surface size for CAB allocation
0259         if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)
0260             continue;
0261 
0262         if (ctx->stream_status[i].plane_count == 0)
0263             continue;
0264 
0265         // For each stream, loop through each plane to calculate the number of cache
0266         // lines required to store the surface in CAB
0267         for (j = 0; j < ctx->stream_status[i].plane_count; j++) {
0268             plane = ctx->stream_status[i].plane_states[j];
0269 
0270             // Calculate total surface size
0271             if (prev_addr_low != plane->address.grph.addr.u.low_part) {
0272                 /* if plane address are different from prev FB, then userspace allocated separate FBs*/
0273                 surface_size += plane->plane_size.surface_pitch *
0274                     plane->plane_size.surface_size.height *
0275                     (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
0276 
0277                 prev_addr_low = plane->address.grph.addr.u.low_part;
0278             } else {
0279                 /* We have the same fb for all the planes.
0280                  * Xorg always creates one giant fb that holds all surfaces,
0281                  * so allocating it once is sufficient.
0282                  * */
0283                 continue;
0284             }
0285             // Convert surface size + starting address to number of cache lines required
0286             // (alignment accounted for)
0287             cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
0288                     plane->address.grph.addr.quad_part);
0289 
0290             if (plane->address.grph.meta_addr.quad_part) {
0291                 // Meta surface
0292                 cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
0293                         plane->address.grph.meta_addr.quad_part);
0294             }
0295         }
0296 
0297         // Include cursor size for CAB allocation
0298         for (j = 0; j < dc->res_pool->pipe_count; j++) {
0299             struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[j];
0300             struct hubp *hubp = pipe->plane_res.hubp;
0301 
0302             if (pipe->stream && pipe->plane_state && hubp)
0303                 /* Find the cursor plane and use the exact size instead of
0304                  * using the max for calculation
0305                  */
0306                 if (hubp->curs_attr.width > 0) {
0307                     cursor_size = hubp->curs_attr.width * hubp->curs_attr.height;
0308                     break;
0309                 }
0310         }
0311 
0312         switch (stream->cursor_attributes.color_format) {
0313         case CURSOR_MODE_MONO:
0314             cursor_size /= 2;
0315             break;
0316         case CURSOR_MODE_COLOR_1BIT_AND:
0317         case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
0318         case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
0319             cursor_size *= 4;
0320             break;
0321 
0322         case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
0323         case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
0324             cursor_size *= 8;
0325             break;
0326         }
0327 
0328         if (stream->cursor_position.enable && plane->address.grph.cursor_cache_addr.quad_part) {
0329             cache_lines_used += dcn32_cache_lines_for_surface(dc, cursor_size,
0330                     plane->address.grph.cursor_cache_addr.quad_part);
0331         }
0332     }
0333 
0334     // Convert number of cache lines required to number of ways
0335     total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
0336     lines_per_way = total_lines / dc->caps.cache_num_ways;
0337     num_ways = cache_lines_used / lines_per_way;
0338 
0339     if (cache_lines_used % lines_per_way > 0)
0340         num_ways++;
0341 
0342     for (i = 0; i < ctx->stream_count; i++) {
0343         stream = ctx->streams[i];
0344         for (j = 0; j < ctx->stream_status[i].plane_count; j++) {
0345             plane = ctx->stream_status[i].plane_states[j];
0346 
0347             if (stream->cursor_position.enable && plane &&
0348                 !plane->address.grph.cursor_cache_addr.quad_part &&
0349                 cursor_size > 16384) {
0350                 /* Cursor caching is not supported since it won't be on the same line.
0351                  * So we need an extra line to accommodate it. With large cursors and a single 4k monitor
0352                  * this case triggers corruption. If we're at the edge, then dont trigger display refresh
0353                  * from MALL. We only need to cache cursor if its greater that 64x64 at 4 bpp.
0354                  */
0355                 num_ways++;
0356                 /* We only expect one cursor plane */
0357                 break;
0358             }
0359         }
0360     }
0361 
0362     return num_ways;
0363 }
0364 
0365 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
0366 {
0367     union dmub_rb_cmd cmd;
0368     uint8_t ways, i;
0369     int j;
0370     bool stereo_in_use = false;
0371     struct dc_plane_state *plane = NULL;
0372 
0373     if (!dc->ctx->dmub_srv)
0374         return false;
0375 
0376     if (enable) {
0377         if (dc->current_state) {
0378 
0379             /* 1. Check no memory request case for CAB.
0380              * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
0381              */
0382             if (dcn32_check_no_memory_request_for_cab(dc)) {
0383                 /* Enable no-memory-requests case */
0384                 memset(&cmd, 0, sizeof(cmd));
0385                 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
0386                 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
0387                 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
0388 
0389                 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
0390                 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
0391 
0392                 return true;
0393             }
0394 
0395             /* 2. Check if all surfaces can fit in CAB.
0396              * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
0397              * and configure HUBP's to fetch from MALL
0398              */
0399             ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
0400 
0401             /* MALL not supported with Stereo3D. If any plane is using stereo,
0402              * don't try to enter MALL.
0403              */
0404             for (i = 0; i < dc->current_state->stream_count; i++) {
0405                 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
0406                     plane = dc->current_state->stream_status[i].plane_states[j];
0407 
0408                     if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO) {
0409                         stereo_in_use = true;
0410                         break;
0411                     }
0412                 }
0413                 if (stereo_in_use)
0414                     break;
0415             }
0416             if (ways <= dc->caps.cache_num_ways && !stereo_in_use) {
0417                 memset(&cmd, 0, sizeof(cmd));
0418                 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
0419                 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
0420                 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
0421                 cmd.cab.cab_alloc_ways = ways;
0422 
0423                 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
0424                 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
0425 
0426                 return true;
0427             }
0428 
0429         }
0430         return false;
0431     }
0432 
0433     /* Disable CAB */
0434     memset(&cmd, 0, sizeof(cmd));
0435     cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
0436     cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;
0437     cmd.cab.header.payload_bytes =
0438             sizeof(cmd.cab) - sizeof(cmd.cab.header);
0439 
0440     dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
0441     dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
0442     dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
0443 
0444     return true;
0445 }
0446 
0447 /* Send DMCUB message with SubVP pipe info
0448  * - For each pipe in context, populate payload with required SubVP information
0449  *   if the pipe is using SubVP for MCLK switch
0450  * - This function must be called while the DMUB HW lock is acquired by driver
0451  */
0452 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)
0453 {
0454 /*
0455     int i;
0456     bool enable_subvp = false;
0457 
0458     if (!dc->ctx || !dc->ctx->dmub_srv)
0459         return;
0460 
0461     for (i = 0; i < dc->res_pool->pipe_count; i++) {
0462         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
0463 
0464         if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream &&
0465                 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) {
0466             // There is at least 1 SubVP pipe, so enable SubVP
0467             enable_subvp = true;
0468             break;
0469         }
0470     }
0471     dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);
0472 */
0473 }
0474 
0475 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and:
0476  * 1. Any full update for any SubVP main pipe
0477  * 2. Any immediate flip for any SubVP pipe
0478  * 3. Any flip for DRR pipe
0479  * 4. If SubVP was previously in use (i.e. in old context)
0480  */
0481 void dcn32_subvp_pipe_control_lock(struct dc *dc,
0482         struct dc_state *context,
0483         bool lock,
0484         bool should_lock_all_pipes,
0485         struct pipe_ctx *top_pipe_to_program,
0486         bool subvp_prev_use)
0487 {
0488     unsigned int i = 0;
0489     bool subvp_immediate_flip = false;
0490     bool subvp_in_use = false;
0491     struct pipe_ctx *pipe;
0492 
0493     for (i = 0; i < dc->res_pool->pipe_count; i++) {
0494         pipe = &context->res_ctx.pipe_ctx[i];
0495 
0496         if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
0497             subvp_in_use = true;
0498             break;
0499         }
0500     }
0501 
0502     if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {
0503         if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN &&
0504                 top_pipe_to_program->plane_state->flip_immediate)
0505             subvp_immediate_flip = true;
0506     }
0507 
0508     // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
0509     if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) {
0510         union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
0511 
0512         if (!lock) {
0513             for (i = 0; i < dc->res_pool->pipe_count; i++) {
0514                 pipe = &context->res_ctx.pipe_ctx[i];
0515                 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN &&
0516                         should_lock_all_pipes)
0517                     pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
0518             }
0519         }
0520 
0521         hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
0522         hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
0523         hw_lock_cmd.bits.lock = lock;
0524         hw_lock_cmd.bits.should_release = !lock;
0525         dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
0526     }
0527 }
0528 
0529 
0530 static bool dcn32_set_mpc_shaper_3dlut(
0531     struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
0532 {
0533     struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
0534     int mpcc_id = pipe_ctx->plane_res.hubp->inst;
0535     struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
0536     bool result = false;
0537 
0538     const struct pwl_params *shaper_lut = NULL;
0539     //get the shaper lut params
0540     if (stream->func_shaper) {
0541         if (stream->func_shaper->type == TF_TYPE_HWPWL)
0542             shaper_lut = &stream->func_shaper->pwl;
0543         else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
0544             cm_helper_translate_curve_to_hw_format(
0545                     stream->func_shaper,
0546                     &dpp_base->shaper_params, true);
0547             shaper_lut = &dpp_base->shaper_params;
0548         }
0549     }
0550 
0551     if (stream->lut3d_func &&
0552         stream->lut3d_func->state.bits.initialized == 1) {
0553 
0554         result = mpc->funcs->program_3dlut(mpc,
0555                                 &stream->lut3d_func->lut_3d,
0556                                 mpcc_id);
0557 
0558         result = mpc->funcs->program_shaper(mpc,
0559                                 shaper_lut,
0560                                 mpcc_id);
0561     }
0562 
0563     return result;
0564 }
0565 
0566 bool dcn32_set_mcm_luts(
0567     struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
0568 {
0569     struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
0570     int mpcc_id = pipe_ctx->plane_res.hubp->inst;
0571     struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
0572     bool result = true;
0573     struct pwl_params *lut_params = NULL;
0574 
0575     // 1D LUT
0576     if (plane_state->blend_tf) {
0577         if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
0578             lut_params = &plane_state->blend_tf->pwl;
0579         else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
0580             cm_helper_translate_curve_to_hw_format(
0581                     plane_state->blend_tf,
0582                     &dpp_base->regamma_params, false);
0583             lut_params = &dpp_base->regamma_params;
0584         }
0585     }
0586     result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
0587 
0588     // Shaper
0589     if (plane_state->in_shaper_func) {
0590         if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
0591             lut_params = &plane_state->in_shaper_func->pwl;
0592         else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
0593             // TODO: dpp_base replace
0594             ASSERT(false);
0595             cm_helper_translate_curve_to_hw_format(
0596                     plane_state->in_shaper_func,
0597                     &dpp_base->shaper_params, true);
0598             lut_params = &dpp_base->shaper_params;
0599         }
0600     }
0601 
0602     result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
0603 
0604     // 3D
0605     if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1)
0606         result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id);
0607     else
0608         result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);
0609 
0610     return result;
0611 }
0612 
0613 bool dcn32_set_input_transfer_func(struct dc *dc,
0614                 struct pipe_ctx *pipe_ctx,
0615                 const struct dc_plane_state *plane_state)
0616 {
0617     struct dce_hwseq *hws = dc->hwseq;
0618     struct mpc *mpc = dc->res_pool->mpc;
0619     struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
0620 
0621     enum dc_transfer_func_predefined tf;
0622     bool result = true;
0623     struct pwl_params *params = NULL;
0624 
0625     if (mpc == NULL || plane_state == NULL)
0626         return false;
0627 
0628     tf = TRANSFER_FUNCTION_UNITY;
0629 
0630     if (plane_state->in_transfer_func &&
0631         plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
0632         tf = plane_state->in_transfer_func->tf;
0633 
0634     dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
0635 
0636     if (plane_state->in_transfer_func) {
0637         if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
0638             params = &plane_state->in_transfer_func->pwl;
0639         else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
0640             cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
0641                     &dpp_base->degamma_params, false))
0642             params = &dpp_base->degamma_params;
0643     }
0644 
0645     result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
0646 
0647     if (result &&
0648             pipe_ctx->stream_res.opp &&
0649             pipe_ctx->stream_res.opp->ctx &&
0650             hws->funcs.set_mcm_luts)
0651         result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);
0652 
0653     return result;
0654 }
0655 
0656 bool dcn32_set_output_transfer_func(struct dc *dc,
0657                 struct pipe_ctx *pipe_ctx,
0658                 const struct dc_stream_state *stream)
0659 {
0660     int mpcc_id = pipe_ctx->plane_res.hubp->inst;
0661     struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
0662     struct pwl_params *params = NULL;
0663     bool ret = false;
0664 
0665     /* program OGAM or 3DLUT only for the top pipe*/
0666     if (pipe_ctx->top_pipe == NULL) {
0667         /*program shaper and 3dlut in MPC*/
0668         ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
0669         if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
0670             if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
0671                 params = &stream->out_transfer_func->pwl;
0672             else if (pipe_ctx->stream->out_transfer_func->type ==
0673                     TF_TYPE_DISTRIBUTED_POINTS &&
0674                     cm3_helper_translate_curve_to_hw_format(
0675                     stream->out_transfer_func,
0676                     &mpc->blender_params, false))
0677                 params = &mpc->blender_params;
0678          /* there are no ROM LUTs in OUTGAM */
0679         if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
0680             BREAK_TO_DEBUGGER();
0681         }
0682     }
0683 
0684     mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
0685     return ret;
0686 }
0687 
0688 /* Program P-State force value according to if pipe is using SubVP or not:
0689  * 1. Reset P-State force on all pipes first
0690  * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)
0691  */
0692 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context)
0693 {
0694     int i;
0695     int num_subvp = 0;
0696     /* Unforce p-state for each pipe
0697      */
0698     for (i = 0; i < dc->res_pool->pipe_count; i++) {
0699         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
0700         struct hubp *hubp = pipe->plane_res.hubp;
0701 
0702         if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
0703             hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
0704         if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
0705             num_subvp++;
0706     }
0707 
0708     if (num_subvp == 0)
0709         return;
0710 
0711     /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.
0712      */
0713     for (i = 0; i < dc->res_pool->pipe_count; i++) {
0714         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
0715 
0716         // For SubVP + DRR, also force disallow on the DRR pipe
0717         // (We will force allow in the DMUB sequence -- some DRR timings by default won't allow P-State so we have
0718         // to force once the vblank is stretched).
0719         if (pipe->stream && pipe->plane_state && (pipe->stream->mall_stream_config.type == SUBVP_MAIN ||
0720                 (pipe->stream->mall_stream_config.type == SUBVP_NONE && pipe->stream->ignore_msa_timing_param))) {
0721             struct hubp *hubp = pipe->plane_res.hubp;
0722 
0723             if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
0724                 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
0725         }
0726     }
0727 }
0728 
0729 /* Update MALL_SEL register based on if pipe / plane
0730  * is a phantom pipe, main pipe, and if using MALL
0731  * for SS.
0732  */
0733 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
0734 {
0735     int i;
0736     unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
0737     bool cache_cursor = false;
0738 
0739     for (i = 0; i < dc->res_pool->pipe_count; i++) {
0740         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
0741         struct hubp *hubp = pipe->plane_res.hubp;
0742 
0743         if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
0744             //Round cursor width up to next multiple of 64
0745             int cursor_width = ((hubp->curs_attr.width + 63) / 64) * 64;
0746             int cursor_height = hubp->curs_attr.height;
0747             int cursor_size = cursor_width * cursor_height;
0748 
0749             switch (hubp->curs_attr.color_format) {
0750             case CURSOR_MODE_MONO:
0751                 cursor_size /= 2;
0752                 break;
0753             case CURSOR_MODE_COLOR_1BIT_AND:
0754             case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
0755             case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
0756                 cursor_size *= 4;
0757                 break;
0758 
0759             case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
0760             case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
0761             default:
0762                 cursor_size *= 8;
0763                 break;
0764             }
0765 
0766             if (cursor_size > 16384)
0767                 cache_cursor = true;
0768 
0769             if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
0770                     hubp->funcs->hubp_update_mall_sel(hubp, 1, false);
0771             } else {
0772                 // MALL not supported with Stereo3D
0773                 hubp->funcs->hubp_update_mall_sel(hubp,
0774                     num_ways <= dc->caps.cache_num_ways &&
0775                     pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
0776                     pipe->plane_state->address.type !=  PLN_ADDR_TYPE_GRPH_STEREO ? 2 : 0,
0777                             cache_cursor);
0778             }
0779         }
0780     }
0781 }
0782 
0783 /* Program the sub-viewport pipe configuration after the main / phantom pipes
0784  * have been programmed in hardware.
0785  * 1. Update force P-State for all the main pipes (disallow P-state)
0786  * 2. Update MALL_SEL register
0787  * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes
0788  */
0789 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
0790 {
0791     int i;
0792     struct dce_hwseq *hws = dc->hwseq;
0793 
0794     // Don't force p-state disallow -- can't block dummy p-state
0795 
0796     // Update MALL_SEL register for each pipe
0797     if (hws && hws->funcs.update_mall_sel)
0798         hws->funcs.update_mall_sel(dc, context);
0799 
0800     // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes
0801     for (i = 0; i < dc->res_pool->pipe_count; i++) {
0802         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
0803         struct hubp *hubp = pipe->plane_res.hubp;
0804 
0805         if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
0806             /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases
0807              *      - need to investigate single pipe MPO + SubVP case to
0808              *        see if CURSOR_REQ_MODE will be back to 1 for SubVP
0809              *        when it should be 0 for MPO
0810              */
0811             if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
0812                 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
0813             }
0814         }
0815     }
0816 }
0817 
0818 void dcn32_init_hw(struct dc *dc)
0819 {
0820     struct abm **abms = dc->res_pool->multiple_abms;
0821     struct dce_hwseq *hws = dc->hwseq;
0822     struct dc_bios *dcb = dc->ctx->dc_bios;
0823     struct resource_pool *res_pool = dc->res_pool;
0824     int i;
0825     int edp_num;
0826     uint32_t backlight = MAX_BACKLIGHT_LEVEL;
0827 
0828     if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
0829         dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
0830 
0831     // Initialize the dccg
0832     if (res_pool->dccg->funcs->dccg_init)
0833         res_pool->dccg->funcs->dccg_init(res_pool->dccg);
0834 
0835     if (!dcb->funcs->is_accelerated_mode(dcb)) {
0836         hws->funcs.bios_golden_init(dc);
0837         hws->funcs.disable_vga(dc->hwseq);
0838     }
0839 
0840     // Set default OPTC memory power states
0841     if (dc->debug.enable_mem_low_power.bits.optc) {
0842         // Shutdown when unassigned and light sleep in VBLANK
0843         REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
0844     }
0845 
0846     if (dc->debug.enable_mem_low_power.bits.vga) {
0847         // Power down VGA memory
0848         REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
0849     }
0850 
0851     if (dc->ctx->dc_bios->fw_info_valid) {
0852         res_pool->ref_clocks.xtalin_clock_inKhz =
0853                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
0854 
0855         if (res_pool->dccg && res_pool->hubbub) {
0856             (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
0857                     dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
0858                     &res_pool->ref_clocks.dccg_ref_clock_inKhz);
0859 
0860             (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
0861                     res_pool->ref_clocks.dccg_ref_clock_inKhz,
0862                     &res_pool->ref_clocks.dchub_ref_clock_inKhz);
0863         } else {
0864             // Not all ASICs have DCCG sw component
0865             res_pool->ref_clocks.dccg_ref_clock_inKhz =
0866                     res_pool->ref_clocks.xtalin_clock_inKhz;
0867             res_pool->ref_clocks.dchub_ref_clock_inKhz =
0868                     res_pool->ref_clocks.xtalin_clock_inKhz;
0869         }
0870     } else
0871         ASSERT_CRITICAL(false);
0872 
0873     for (i = 0; i < dc->link_count; i++) {
0874         /* Power up AND update implementation according to the
0875          * required signal (which may be different from the
0876          * default signal on connector).
0877          */
0878         struct dc_link *link = dc->links[i];
0879 
0880         link->link_enc->funcs->hw_init(link->link_enc);
0881 
0882         /* Check for enabled DIG to identify enabled display */
0883         if (link->link_enc->funcs->is_dig_enabled &&
0884             link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
0885             link->link_status.link_active = true;
0886             if (link->link_enc->funcs->fec_is_active &&
0887                     link->link_enc->funcs->fec_is_active(link->link_enc))
0888                 link->fec_state = dc_link_fec_enabled;
0889         }
0890     }
0891 
0892     /* Power gate DSCs */
0893     for (i = 0; i < res_pool->res_cap->num_dsc; i++)
0894         if (hws->funcs.dsc_pg_control != NULL)
0895             hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
0896 
0897     /* we want to turn off all dp displays before doing detection */
0898     dc_link_blank_all_dp_displays(dc);
0899 
0900     /* If taking control over from VBIOS, we may want to optimize our first
0901      * mode set, so we need to skip powering down pipes until we know which
0902      * pipes we want to use.
0903      * Otherwise, if taking control is not possible, we need to power
0904      * everything down.
0905      */
0906     if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
0907         hws->funcs.init_pipes(dc, dc->current_state);
0908         if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
0909             dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
0910                     !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
0911     }
0912 
0913     /* In headless boot cases, DIG may be turned
0914      * on which causes HW/SW discrepancies.
0915      * To avoid this, power down hardware on boot
0916      * if DIG is turned on and seamless boot not enabled
0917      */
0918     if (!dc->config.seamless_boot_edp_requested) {
0919         struct dc_link *edp_links[MAX_NUM_EDP];
0920         struct dc_link *edp_link;
0921 
0922         get_edp_links(dc, edp_links, &edp_num);
0923         if (edp_num) {
0924             for (i = 0; i < edp_num; i++) {
0925                 edp_link = edp_links[i];
0926                 if (edp_link->link_enc->funcs->is_dig_enabled &&
0927                         edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
0928                         dc->hwss.edp_backlight_control &&
0929                         dc->hwss.power_down &&
0930                         dc->hwss.edp_power_control) {
0931                     dc->hwss.edp_backlight_control(edp_link, false);
0932                     dc->hwss.power_down(dc);
0933                     dc->hwss.edp_power_control(edp_link, false);
0934                 }
0935             }
0936         } else {
0937             for (i = 0; i < dc->link_count; i++) {
0938                 struct dc_link *link = dc->links[i];
0939 
0940                 if (link->link_enc->funcs->is_dig_enabled &&
0941                         link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
0942                         dc->hwss.power_down) {
0943                     dc->hwss.power_down(dc);
0944                     break;
0945                 }
0946 
0947             }
0948         }
0949     }
0950 
0951     for (i = 0; i < res_pool->audio_count; i++) {
0952         struct audio *audio = res_pool->audios[i];
0953 
0954         audio->funcs->hw_init(audio);
0955     }
0956 
0957     for (i = 0; i < dc->link_count; i++) {
0958         struct dc_link *link = dc->links[i];
0959 
0960         if (link->panel_cntl)
0961             backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
0962     }
0963 
0964     for (i = 0; i < dc->res_pool->pipe_count; i++) {
0965         if (abms[i] != NULL && abms[i]->funcs != NULL)
0966             abms[i]->funcs->abm_init(abms[i], backlight);
0967     }
0968 
0969     /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
0970     REG_WRITE(DIO_MEM_PWR_CTRL, 0);
0971 
0972     if (!dc->debug.disable_clock_gate) {
0973         /* enable all DCN clock gating */
0974         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
0975 
0976         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
0977 
0978         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
0979     }
0980     if (hws->funcs.enable_power_gating_plane)
0981         hws->funcs.enable_power_gating_plane(dc->hwseq, true);
0982 
0983     if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
0984         dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
0985 
0986     if (dc->clk_mgr->funcs->notify_wm_ranges)
0987         dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
0988 
0989     if (dc->clk_mgr->funcs->set_hard_max_memclk)
0990         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
0991 
0992     if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
0993         dc->res_pool->hubbub->funcs->force_pstate_change_control(
0994                 dc->res_pool->hubbub, false, false);
0995 
0996     if (dc->res_pool->hubbub->funcs->init_crb)
0997         dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
0998 
0999     // Get DMCUB capabilities
1000     if (dc->ctx->dmub_srv) {
1001         dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
1002         dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
1003     }
1004 }
1005 
1006 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
1007         int opp_cnt)
1008 {
1009     bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
1010     int flow_ctrl_cnt;
1011 
1012     if (opp_cnt >= 2)
1013         hblank_halved = true;
1014 
1015     flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
1016             stream->timing.h_border_left -
1017             stream->timing.h_border_right;
1018 
1019     if (hblank_halved)
1020         flow_ctrl_cnt /= 2;
1021 
1022     /* ODM combine 4:1 case */
1023     if (opp_cnt == 4)
1024         flow_ctrl_cnt /= 2;
1025 
1026     return flow_ctrl_cnt;
1027 }
1028 
1029 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
1030 {
1031     struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
1032     struct dc_stream_state *stream = pipe_ctx->stream;
1033     struct pipe_ctx *odm_pipe;
1034     int opp_cnt = 1;
1035 
1036     ASSERT(dsc);
1037     for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1038         opp_cnt++;
1039 
1040     if (enable) {
1041         struct dsc_config dsc_cfg;
1042         struct dsc_optc_config dsc_optc_cfg;
1043         enum optc_dsc_mode optc_dsc_mode;
1044 
1045         /* Enable DSC hw block */
1046         dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
1047         dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
1048         dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1049         dsc_cfg.color_depth = stream->timing.display_color_depth;
1050         dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1051         dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1052         ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
1053         dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
1054 
1055         dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
1056         dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
1057         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1058             struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
1059 
1060             ASSERT(odm_dsc);
1061             odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
1062             odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
1063         }
1064         dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
1065         dsc_cfg.pic_width *= opp_cnt;
1066 
1067         optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
1068 
1069         /* Enable DSC in OPTC */
1070         DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
1071         pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
1072                             optc_dsc_mode,
1073                             dsc_optc_cfg.bytes_per_pixel,
1074                             dsc_optc_cfg.slice_width);
1075     } else {
1076         /* disable DSC in OPTC */
1077         pipe_ctx->stream_res.tg->funcs->set_dsc_config(
1078                 pipe_ctx->stream_res.tg,
1079                 OPTC_DSC_DISABLED, 0, 0);
1080 
1081         /* disable DSC block */
1082         dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
1083         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1084             ASSERT(odm_pipe->stream_res.dsc);
1085             odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
1086         }
1087     }
1088 }
1089 
1090 /*
1091 * Given any pipe_ctx, return the total ODM combine factor, and optionally return
1092 * the OPPids which are used
1093 * */
1094 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
1095 {
1096     unsigned int opp_count = 1;
1097     struct pipe_ctx *odm_pipe;
1098 
1099     /* First get to the top pipe */
1100     for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
1101         ;
1102 
1103     /* First pipe is always used */
1104     if (opp_instances)
1105         opp_instances[0] = odm_pipe->stream_res.opp->inst;
1106 
1107     /* Find and count odm pipes, if any */
1108     for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1109         if (opp_instances)
1110             opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
1111         opp_count++;
1112     }
1113 
1114     return opp_count;
1115 }
1116 
1117 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1118 {
1119     struct pipe_ctx *odm_pipe;
1120     int opp_cnt = 0;
1121     int opp_inst[MAX_PIPES] = {0};
1122     bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing));
1123     struct mpc_dwb_flow_control flow_control;
1124     struct mpc *mpc = dc->res_pool->mpc;
1125     int i;
1126 
1127     opp_cnt = get_odm_config(pipe_ctx, opp_inst);
1128 
1129     if (opp_cnt > 1)
1130         pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1131                 pipe_ctx->stream_res.tg,
1132                 opp_inst, opp_cnt,
1133                 &pipe_ctx->stream->timing);
1134     else
1135         pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1136                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1137 
1138     rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
1139     flow_control.flow_ctrl_mode = 0;
1140     flow_control.flow_ctrl_cnt0 = 0x80;
1141     flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt);
1142     if (mpc->funcs->set_out_rate_control) {
1143         for (i = 0; i < opp_cnt; ++i) {
1144             mpc->funcs->set_out_rate_control(
1145                     mpc, opp_inst[i],
1146                     true,
1147                     rate_control_2x_pclk,
1148                     &flow_control);
1149         }
1150     }
1151 
1152     for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1153         odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
1154                 odm_pipe->stream_res.opp,
1155                 true);
1156     }
1157 
1158     // Don't program pixel clock after link is already enabled
1159 /*  if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1160             pipe_ctx->clock_source,
1161             &pipe_ctx->stream_res.pix_clk_params,
1162             &pipe_ctx->pll_settings)) {
1163         BREAK_TO_DEBUGGER();
1164     }*/
1165 
1166     if (pipe_ctx->stream_res.dsc)
1167         update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
1168 }
1169 
1170 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
1171 {
1172     struct dc_stream_state *stream = pipe_ctx->stream;
1173     unsigned int odm_combine_factor = 0;
1174     struct dc *dc = pipe_ctx->stream->ctx->dc;
1175     bool two_pix_per_container = false;
1176 
1177     // For phantom pipes, use the same programming as the main pipes
1178     if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1179         stream = pipe_ctx->stream->mall_stream_config.paired_stream;
1180     }
1181     two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
1182     odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1183 
1184     if (is_dp_128b_132b_signal(pipe_ctx)) {
1185         *k2_div = PIXEL_RATE_DIV_BY_1;
1186     } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
1187         *k1_div = PIXEL_RATE_DIV_BY_1;
1188         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1189             *k2_div = PIXEL_RATE_DIV_BY_2;
1190         else
1191             *k2_div = PIXEL_RATE_DIV_BY_4;
1192     } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1193         if (two_pix_per_container) {
1194             *k1_div = PIXEL_RATE_DIV_BY_1;
1195             *k2_div = PIXEL_RATE_DIV_BY_2;
1196         } else {
1197             *k1_div = PIXEL_RATE_DIV_BY_1;
1198             *k2_div = PIXEL_RATE_DIV_BY_4;
1199             if ((odm_combine_factor == 2) || dc->debug.enable_dp_dig_pixel_rate_div_policy)
1200                 *k2_div = PIXEL_RATE_DIV_BY_2;
1201         }
1202     }
1203 
1204     if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
1205         ASSERT(false);
1206 
1207     return odm_combine_factor;
1208 }
1209 
1210 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
1211 {
1212     uint32_t pix_per_cycle = 1;
1213     uint32_t odm_combine_factor = 1;
1214 
1215     if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
1216         return;
1217 
1218     odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1219     if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1
1220         || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1221         pix_per_cycle = 2;
1222 
1223     if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
1224         pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
1225                 pix_per_cycle);
1226 }
1227 
1228 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
1229         struct dc_link_settings *link_settings)
1230 {
1231     struct encoder_unblank_param params = {0};
1232     struct dc_stream_state *stream = pipe_ctx->stream;
1233     struct dc_link *link = stream->link;
1234     struct dce_hwseq *hws = link->dc->hwseq;
1235     struct pipe_ctx *odm_pipe;
1236     struct dc *dc = pipe_ctx->stream->ctx->dc;
1237     uint32_t pix_per_cycle = 1;
1238 
1239     params.opp_cnt = 1;
1240     for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1241         params.opp_cnt++;
1242 
1243     /* only 3 items below are used by unblank */
1244     params.timing = pipe_ctx->stream->timing;
1245 
1246     params.link_settings.link_rate = link_settings->link_rate;
1247 
1248     if (is_dp_128b_132b_signal(pipe_ctx)) {
1249         /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1250         pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
1251                 pipe_ctx->stream_res.hpo_dp_stream_enc,
1252                 pipe_ctx->stream_res.tg->inst);
1253     } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1254         if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1
1255             || dc->debug.enable_dp_dig_pixel_rate_div_policy) {
1256             params.timing.pix_clk_100hz /= 2;
1257             pix_per_cycle = 2;
1258         }
1259         pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1260                 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1);
1261         pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1262     }
1263 
1264     if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1265         hws->funcs.edp_backlight_control(link, true);
1266 }
1267 
1268 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
1269 {
1270     struct dc *dc = pipe_ctx->stream->ctx->dc;
1271 
1272     if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) &&
1273         dc->debug.enable_dp_dig_pixel_rate_div_policy)
1274         return true;
1275     return false;
1276 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!