dc/dcn32/dcn32_hubp.h

0001 /*
0002  * Copyright 2012-20 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_HUBP_DCN32_H__
0027 #define __DC_HUBP_DCN32_H__
0028
0029 #include "dcn20/dcn20_hubp.h"
0030 #include "dcn21/dcn21_hubp.h"
0031 #include "dcn30/dcn30_hubp.h"
0032 #include "dcn31/dcn31_hubp.h"
0033
0034 #define HUBP_REG_LIST_DCN32(id)\
0035     HUBP_REG_LIST_DCN30(id),\
0036     SRI(DCHUBP_MALL_CONFIG, HUBP, id),\
0037     SRI(DCHUBP_VMPG_CONFIG, HUBP, id),\
0038     SRI(UCLK_PSTATE_FORCE, HUBPREQ, id)
0039
0040 #define HUBP_MASK_SH_LIST_DCN32(mask_sh)\
0041     HUBP_MASK_SH_LIST_DCN31(mask_sh),\
0042     HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_SEL, mask_sh),\
0043     HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, mask_sh),\
0044     HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, VMPG_SIZE, mask_sh),\
0045     HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, PTE_BUFFER_MODE, mask_sh),\
0046     HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, BIGK_FRAGMENT_SIZE, mask_sh),\
0047     HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, mask_sh),\
0048     HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_EN, mask_sh),\
0049     HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_VALUE, mask_sh),\
0050     HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_EN, mask_sh),\
0051     HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_VALUE, mask_sh)
0052
0053 void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow);
0054
0055 void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);
0056
0057 void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable);
0058
0059 void hubp32_phantom_hubp_post_enable(struct hubp *hubp);
0060
0061 void hubp32_cursor_set_attributes(struct hubp *hubp,
0062         const struct dc_cursor_attributes *attr);
0063
0064 bool hubp32_construct(
0065     struct dcn20_hubp *hubp2,
0066     struct dc_context *ctx,
0067     uint32_t inst,
0068     const struct dcn_hubp2_registers *hubp_regs,
0069     const struct dcn_hubp2_shift *hubp_shift,
0070     const struct dcn_hubp2_mask *hubp_mask);
0071
0072 #endif /* __DC_HUBP_DCN32_H__ */