dc/dcn32/dcn32_hubp.c

0001 /*
0002  * Copyright 2012-20 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027 #include "dce_calcs.h"
0028 #include "reg_helper.h"
0029 #include "basics/conversion.h"
0030 #include "dcn32_hubp.h"
0031
0032 #define REG(reg)\
0033     hubp2->hubp_regs->reg
0034
0035 #define CTX \
0036     hubp2->base.ctx
0037
0038 #undef FN
0039 #define FN(reg_name, field_name) \
0040     hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
0041
0042 void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow)
0043 {
0044     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0045     REG_UPDATE_2(UCLK_PSTATE_FORCE,
0046             DATA_UCLK_PSTATE_FORCE_EN, pstate_disallow,
0047             DATA_UCLK_PSTATE_FORCE_VALUE, 0);
0048 }
0049
0050 void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)
0051 {
0052     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0053
0054     // Also cache cursor in MALL if using MALL for SS
0055     REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel,
0056             USE_MALL_FOR_CURSOR, c_cursor);
0057 }
0058
0059 void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable)
0060 {
0061     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0062     REG_UPDATE(DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, enable);
0063
0064     /* Programming guide suggests CURSOR_REQ_MODE = 1 for SubVP:
0065      * For Pstate change using the MALL with sub-viewport buffering,
0066      * the cursor does not use the MALL (USE_MALL_FOR_CURSOR is ignored)
0067      * and sub-viewport positioning by Display FW has to avoid the cursor
0068      * requests to DRAM (set CURSOR_REQ_MODE = 1 to minimize this exclusion).
0069      *
0070      * CURSOR_REQ_MODE = 1 begins fetching cursor data at the beginning of display prefetch.
0071      * Setting this should allow the sub-viewport position to always avoid the cursor because
0072      * we do not allow the sub-viewport region to overlap with display prefetch (i.e. during blank).
0073      */
0074     REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable);
0075 }
0076
0077 void hubp32_phantom_hubp_post_enable(struct hubp *hubp)
0078 {
0079     uint32_t reg_val;
0080     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0081
0082     REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, 1);
0083     reg_val = REG_READ(DCHUBP_CNTL);
0084     if (reg_val) {
0085         /* init sequence workaround: in case HUBP is
0086          * power gated, this wait would timeout.
0087          *
0088          * we just wrote reg_val to non-0, if it stay 0
0089          * it means HUBP is gated
0090          */
0091         REG_WAIT(DCHUBP_CNTL,
0092                 HUBP_NO_OUTSTANDING_REQ, 1,
0093                 1, 200);
0094     }
0095 }
0096
0097 void hubp32_cursor_set_attributes(
0098         struct hubp *hubp,
0099         const struct dc_cursor_attributes *attr)
0100 {
0101     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0102     enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
0103     enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk(
0104             attr->width, attr->color_format);
0105
0106     //Round cursor width up to next multiple of 64
0107     uint32_t cursor_width = ((attr->width + 63) / 64) * 64;
0108     uint32_t cursor_height = attr->height;
0109     uint32_t cursor_size = cursor_width * cursor_height;
0110
0111     hubp->curs_attr = *attr;
0112
0113     REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
0114             CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
0115     REG_UPDATE(CURSOR_SURFACE_ADDRESS,
0116             CURSOR_SURFACE_ADDRESS, attr->address.low_part);
0117
0118     REG_UPDATE_2(CURSOR_SIZE,
0119             CURSOR_WIDTH, attr->width,
0120             CURSOR_HEIGHT, attr->height);
0121
0122     REG_UPDATE_4(CURSOR_CONTROL,
0123             CURSOR_MODE, attr->color_format,
0124             CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,
0125             CURSOR_PITCH, hw_pitch,
0126             CURSOR_LINES_PER_CHUNK, lpc);
0127
0128     REG_SET_2(CURSOR_SETTINGS, 0,
0129             /* no shift of the cursor HDL schedule */
0130             CURSOR0_DST_Y_OFFSET, 0,
0131              /* used to shift the cursor chunk request deadline */
0132             CURSOR0_CHUNK_HDL_ADJUST, 3);
0133
0134     switch (attr->color_format) {
0135     case CURSOR_MODE_MONO:
0136         cursor_size /= 2;
0137         break;
0138     case CURSOR_MODE_COLOR_1BIT_AND:
0139     case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
0140     case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
0141         cursor_size *= 4;
0142         break;
0143
0144     case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
0145     case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
0146     default:
0147         cursor_size *= 8;
0148         break;
0149     }
0150
0151     if (cursor_size > 16384)
0152         REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, true);
0153     else
0154         REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, false);
0155 }
0156
0157 static struct hubp_funcs dcn32_hubp_funcs = {
0158     .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
0159     .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
0160     .hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
0161     .hubp_program_surface_config = hubp3_program_surface_config,
0162     .hubp_is_flip_pending = hubp2_is_flip_pending,
0163     .hubp_setup = hubp3_setup,
0164     .hubp_setup_interdependent = hubp2_setup_interdependent,
0165     .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
0166     .set_blank = hubp2_set_blank,
0167     .dcc_control = hubp3_dcc_control,
0168     .mem_program_viewport = min_set_viewport,
0169     .set_cursor_attributes  = hubp32_cursor_set_attributes,
0170     .set_cursor_position    = hubp2_cursor_set_position,
0171     .hubp_clk_cntl = hubp2_clk_cntl,
0172     .hubp_vtg_sel = hubp2_vtg_sel,
0173     .dmdata_set_attributes = hubp3_dmdata_set_attributes,
0174     .dmdata_load = hubp2_dmdata_load,
0175     .dmdata_status_done = hubp2_dmdata_status_done,
0176     .hubp_read_state = hubp3_read_state,
0177     .hubp_clear_underflow = hubp2_clear_underflow,
0178     .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
0179     .hubp_init = hubp3_init,
0180     .set_unbounded_requesting = hubp31_set_unbounded_requesting,
0181     .hubp_soft_reset = hubp31_soft_reset,
0182     .hubp_in_blank = hubp1_in_blank,
0183     .hubp_update_force_pstate_disallow = hubp32_update_force_pstate_disallow,
0184     .phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable,
0185     .hubp_update_mall_sel = hubp32_update_mall_sel,
0186     .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering,
0187     .hubp_set_flip_int = hubp1_set_flip_int
0188 };
0189
0190 bool hubp32_construct(
0191     struct dcn20_hubp *hubp2,
0192     struct dc_context *ctx,
0193     uint32_t inst,
0194     const struct dcn_hubp2_registers *hubp_regs,
0195     const struct dcn_hubp2_shift *hubp_shift,
0196     const struct dcn_hubp2_mask *hubp_mask)
0197 {
0198     hubp2->base.funcs = &dcn32_hubp_funcs;
0199     hubp2->base.ctx = ctx;
0200     hubp2->hubp_regs = hubp_regs;
0201     hubp2->hubp_shift = hubp_shift;
0202     hubp2->hubp_mask = hubp_mask;
0203     hubp2->base.inst = inst;
0204     hubp2->base.opp_id = OPP_ID_INVALID;
0205     hubp2->base.mpcc_id = 0xf;
0206
0207     return true;
0208 }