dc/dcn32/dcn32_dpp.c

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027 #include "core_types.h"
0028 #include "reg_helper.h"
0029 #include "dcn32_dpp.h"
0030 #include "basics/conversion.h"
0031 #include "dcn30/dcn30_cm_common.h"
0032
0033 /* Compute the maximum number of lines that we can fit in the line buffer */
0034 void dscl32_calc_lb_num_partitions(
0035         const struct scaler_data *scl_data,
0036         enum lb_memory_config lb_config,
0037         int *num_part_y,
0038         int *num_part_c)
0039 {
0040     int memory_line_size_y, memory_line_size_c, memory_line_size_a,
0041     lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
0042
0043     int line_size = scl_data->viewport.width < scl_data->recout.width ?
0044             scl_data->viewport.width : scl_data->recout.width;
0045     int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
0046             scl_data->viewport_c.width : scl_data->recout.width;
0047
0048     if (line_size == 0)
0049         line_size = 1;
0050
0051     if (line_size_c == 0)
0052         line_size_c = 1;
0053
0054     memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */
0055     memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */
0056     memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
0057
0058     if (lb_config == LB_MEMORY_CONFIG_1) {
0059         lb_memory_size = 970;
0060         lb_memory_size_c = 970;
0061         lb_memory_size_a = 970;
0062     } else if (lb_config == LB_MEMORY_CONFIG_2) {
0063         lb_memory_size = 1290;
0064         lb_memory_size_c = 1290;
0065         lb_memory_size_a = 1290;
0066     } else if (lb_config == LB_MEMORY_CONFIG_3) {
0067         if (scl_data->viewport.width  == scl_data->h_active &&
0068             scl_data->viewport.height == scl_data->v_active) {
0069             /* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */
0070             /* use increased LB size for calculation only if Scaler not enabled */
0071             lb_memory_size = 970 + 1290 + 1170 + 1170 + 1170;
0072             lb_memory_size_c = 970 + 1290;
0073             lb_memory_size_a = 970 + 1290 + 1170;
0074         } else {
0075             /* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */
0076             lb_memory_size = 970 + 1290 + 484 + 484 + 484;
0077             lb_memory_size_c = 970 + 1290;
0078             lb_memory_size_a = 970 + 1290 + 484;
0079         }
0080     } else {
0081         if (scl_data->viewport.width  == scl_data->h_active &&
0082             scl_data->viewport.height == scl_data->v_active) {
0083             /* use increased LB size for calculation only if Scaler not enabled */
0084             lb_memory_size = 970 + 1290 + 1170;
0085             lb_memory_size_c = 970 + 1290 + 1170;
0086             lb_memory_size_a = 970 + 1290 + 1170;
0087         } else {
0088             lb_memory_size = 970 + 1290 + 484;
0089             lb_memory_size_c = 970 + 1290 + 484;
0090             lb_memory_size_a = 970 + 1290 + 484;
0091         }
0092     }
0093     *num_part_y = lb_memory_size / memory_line_size_y;
0094     *num_part_c = lb_memory_size_c / memory_line_size_c;
0095     num_partitions_a = lb_memory_size_a / memory_line_size_a;
0096
0097     if (scl_data->lb_params.alpha_en
0098             && (num_partitions_a < *num_part_y))
0099         *num_part_y = num_partitions_a;
0100
0101     if (*num_part_y > 32)
0102         *num_part_y = 32;
0103     if (*num_part_c > 32)
0104         *num_part_c = 32;
0105 }
0106
0107 static struct dpp_funcs dcn32_dpp_funcs = {
0108     .dpp_program_gamcor_lut     = dpp3_program_gamcor_lut,
0109     .dpp_read_state             = dpp30_read_state,
0110     .dpp_reset                  = dpp_reset,
0111     .dpp_set_scaler             = dpp1_dscl_set_scaler_manual_scale,
0112     .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
0113     .dpp_set_gamut_remap        = dpp3_cm_set_gamut_remap,
0114     .dpp_set_csc_adjustment     = NULL,
0115     .dpp_set_csc_default        = NULL,
0116     .dpp_program_regamma_pwl    = NULL,
0117     .dpp_set_pre_degam          = dpp3_set_pre_degam,
0118     .dpp_program_input_lut      = NULL,
0119     .dpp_full_bypass            = dpp1_full_bypass,
0120     .dpp_setup                  = dpp3_cnv_setup,
0121     .dpp_program_degamma_pwl    = NULL,
0122     .dpp_program_cm_dealpha     = dpp3_program_cm_dealpha,
0123     .dpp_program_cm_bias        = dpp3_program_cm_bias,
0124
0125     .dpp_program_blnd_lut       = NULL, // BLNDGAM is removed completely in DCN3.2 DPP
0126     .dpp_program_shaper_lut     = NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
0127     .dpp_program_3dlut          = NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
0128
0129     .dpp_program_bias_and_scale = NULL,
0130     .dpp_cnv_set_alpha_keyer    = dpp2_cnv_set_alpha_keyer,
0131     .set_cursor_attributes      = dpp3_set_cursor_attributes,
0132     .set_cursor_position        = dpp1_set_cursor_position,
0133     .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
0134     .dpp_dppclk_control         = dpp1_dppclk_control,
0135     .dpp_set_hdr_multiplier     = dpp3_set_hdr_multiplier,
0136 };
0137
0138
0139 static struct dpp_caps dcn32_dpp_cap = {
0140     .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
0141     .max_lb_partitions = 31,
0142     .dscl_calc_lb_num_partitions = dscl32_calc_lb_num_partitions,
0143 };
0144
0145 bool dpp32_construct(
0146     struct dcn3_dpp *dpp,
0147     struct dc_context *ctx,
0148     uint32_t inst,
0149     const struct dcn3_dpp_registers *tf_regs,
0150     const struct dcn3_dpp_shift *tf_shift,
0151     const struct dcn3_dpp_mask *tf_mask)
0152 {
0153     dpp->base.ctx = ctx;
0154
0155     dpp->base.inst = inst;
0156     dpp->base.funcs = &dcn32_dpp_funcs;
0157     dpp->base.caps = &dcn32_dpp_cap;
0158
0159     dpp->tf_regs = tf_regs;
0160     dpp->tf_shift = tf_shift;
0161     dpp->tf_mask = tf_mask;
0162
0163     return true;
0164 }