dc/dcn32/dcn32_dio_link_encoder.h

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_LINK_ENCODER__DCN32_H__
0027 #define __DC_LINK_ENCODER__DCN32_H__
0028
0029 #include "dcn31/dcn31_dio_link_encoder.h"
0030
0031 #define LE_DCN32_REG_LIST(id)\
0032     LE_DCN31_REG_LIST(id),\
0033     SRI(DIG_FIFO_CTRL0, DIG, id)
0034
0035 #define LINK_ENCODER_MASK_SH_LIST_DCN32(mask_sh) \
0036     LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh),\
0037     LE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh)
0038
0039 void dcn32_link_encoder_construct(
0040     struct dcn20_link_encoder *enc20,
0041     const struct encoder_init_data *init_data,
0042     const struct encoder_feature_support *enc_features,
0043     const struct dcn10_link_enc_registers *link_regs,
0044     const struct dcn10_link_enc_aux_registers *aux_regs,
0045     const struct dcn10_link_enc_hpd_registers *hpd_regs,
0046     const struct dcn10_link_enc_shift *link_shift,
0047     const struct dcn10_link_enc_mask *link_mask);
0048
0049 void enc32_hw_init(struct link_encoder *enc);
0050
0051 void dcn32_link_encoder_enable_dp_output(
0052     struct link_encoder *enc,
0053     const struct dc_link_settings *link_settings,
0054     enum clock_source_id clock_source);
0055
0056 void enc32_set_dig_output_mode(
0057         struct link_encoder *enc,
0058         uint8_t pix_per_container);
0059
0060 #endif /* __DC_LINK_ENCODER__DCN32_H__ */