dc/dcn32/dcn32_dio_link_encoder.c

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026
0027 #include "reg_helper.h"
0028
0029 #include "core_types.h"
0030 #include "link_encoder.h"
0031 #include "dcn31/dcn31_dio_link_encoder.h"
0032 #include "dcn32_dio_link_encoder.h"
0033 #include "stream_encoder.h"
0034 #include "i2caux_interface.h"
0035 #include "dc_bios_types.h"
0036 #include "link_enc_cfg.h"
0037
0038 #include "gpio_service_interface.h"
0039
0040 #ifndef MIN
0041 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
0042 #endif
0043
0044 #define CTX \
0045     enc10->base.ctx
0046 #define DC_LOGGER \
0047     enc10->base.ctx->logger
0048
0049 #define REG(reg)\
0050     (enc10->link_regs->reg)
0051
0052 #undef FN
0053 #define FN(reg_name, field_name) \
0054     enc10->link_shift->field_name, enc10->link_mask->field_name
0055
0056 #define AUX_REG(reg)\
0057     (enc10->aux_regs->reg)
0058
0059 #define AUX_REG_READ(reg_name) \
0060         dm_read_reg(CTX, AUX_REG(reg_name))
0061
0062 #define AUX_REG_WRITE(reg_name, val) \
0063             dm_write_reg(CTX, AUX_REG(reg_name), val)
0064
0065
0066 void enc32_hw_init(struct link_encoder *enc)
0067 {
0068     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0069
0070 /*
0071     00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
0072     01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
0073     02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
0074     03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
0075     04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
0076     05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
0077     06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
0078     07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
0079 */
0080
0081 /*
0082     AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
0083     AUX_RX_START_WINDOW = 1 [6:4]
0084     AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
0085     AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
0086     AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
0087     AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
0088     AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
0089     AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
0090     AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
0091     AUX_RX_DETECTION_THRESHOLD [30:28] = 1
0092 */
0093     AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
0094
0095     AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
0096
0097     //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
0098     // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
0099     // 27MHz -> 0xd
0100     // 100MHz -> 0x32
0101     // 48MHz -> 0x18
0102
0103     // Set TMDS_CTL0 to 1.  This is a legacy setting.
0104     REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
0105
0106     dcn10_aux_initialize(enc10);
0107 }
0108
0109
0110 void dcn32_link_encoder_enable_dp_output(
0111     struct link_encoder *enc,
0112     const struct dc_link_settings *link_settings,
0113     enum clock_source_id clock_source)
0114 {
0115     if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
0116         dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
0117         return;
0118     }
0119 }
0120
0121 bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc)
0122 {
0123     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0124     uint32_t dp_alt_mode_disable = 0;
0125     bool is_usb_c_alt_mode = false;
0126
0127     if (enc->features.flags.bits.DP_IS_USB_C) {
0128         /* if value == 1 alt mode is disabled, otherwise it is enabled */
0129         REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
0130         is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
0131     }
0132
0133     return is_usb_c_alt_mode;
0134 }
0135
0136 void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc,
0137     struct dc_link_settings *link_settings)
0138 {
0139     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0140     uint32_t is_in_usb_c_dp4_mode = 0;
0141
0142     dcn10_link_encoder_get_max_link_cap(enc, link_settings);
0143
0144     /* in usb c dp2 mode, max lane count is 2 */
0145     if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
0146         REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
0147         if (!is_in_usb_c_dp4_mode)
0148             link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
0149     }
0150
0151 }
0152
0153 void enc32_set_dig_output_mode(struct link_encoder *enc, uint8_t pix_per_container)
0154 {
0155     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0156     REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container);
0157 }
0158
0159 static const struct link_encoder_funcs dcn32_link_enc_funcs = {
0160     .read_state = link_enc2_read_state,
0161     .validate_output_with_stream =
0162             dcn30_link_encoder_validate_output_with_stream,
0163     .hw_init = enc32_hw_init,
0164     .setup = dcn10_link_encoder_setup,
0165     .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
0166     .enable_dp_output = dcn32_link_encoder_enable_dp_output,
0167     .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
0168     .disable_output = dcn10_link_encoder_disable_output,
0169     .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
0170     .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
0171     .update_mst_stream_allocation_table =
0172         dcn10_link_encoder_update_mst_stream_allocation_table,
0173     .psr_program_dp_dphy_fast_training =
0174             dcn10_psr_program_dp_dphy_fast_training,
0175     .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
0176     .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
0177     .enable_hpd = dcn10_link_encoder_enable_hpd,
0178     .disable_hpd = dcn10_link_encoder_disable_hpd,
0179     .is_dig_enabled = dcn10_is_dig_enabled,
0180     .destroy = dcn10_link_encoder_destroy,
0181     .fec_set_enable = enc2_fec_set_enable,
0182     .fec_set_ready = enc2_fec_set_ready,
0183     .fec_is_active = enc2_fec_is_active,
0184     .get_dig_frontend = dcn10_get_dig_frontend,
0185     .get_dig_mode = dcn10_get_dig_mode,
0186     .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode,
0187     .get_max_link_cap = dcn32_link_encoder_get_max_link_cap,
0188     .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
0189     .set_dig_output_mode = enc32_set_dig_output_mode,
0190 };
0191
0192 void dcn32_link_encoder_construct(
0193     struct dcn20_link_encoder *enc20,
0194     const struct encoder_init_data *init_data,
0195     const struct encoder_feature_support *enc_features,
0196     const struct dcn10_link_enc_registers *link_regs,
0197     const struct dcn10_link_enc_aux_registers *aux_regs,
0198     const struct dcn10_link_enc_hpd_registers *hpd_regs,
0199     const struct dcn10_link_enc_shift *link_shift,
0200     const struct dcn10_link_enc_mask *link_mask)
0201 {
0202     struct bp_connector_speed_cap_info bp_cap_info = {0};
0203     const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
0204     enum bp_result result = BP_RESULT_OK;
0205     struct dcn10_link_encoder *enc10 = &enc20->enc10;
0206
0207     enc10->base.funcs = &dcn32_link_enc_funcs;
0208     enc10->base.ctx = init_data->ctx;
0209     enc10->base.id = init_data->encoder;
0210
0211     enc10->base.hpd_source = init_data->hpd_source;
0212     enc10->base.connector = init_data->connector;
0213
0214     if (enc10->base.connector.id == CONNECTOR_ID_USBC)
0215         enc10->base.features.flags.bits.DP_IS_USB_C = 1;
0216
0217     enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0218
0219     enc10->base.features = *enc_features;
0220
0221     enc10->base.transmitter = init_data->transmitter;
0222
0223     /* set the flag to indicate whether driver poll the I2C data pin
0224      * while doing the DP sink detect
0225      */
0226
0227 /*  if (dal_adapter_service_is_feature_supported(as,
0228         FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
0229         enc10->base.features.flags.bits.
0230             DP_SINK_DETECT_POLL_DATA_PIN = true;*/
0231
0232     enc10->base.output_signals =
0233         SIGNAL_TYPE_DVI_SINGLE_LINK |
0234         SIGNAL_TYPE_DVI_DUAL_LINK |
0235         SIGNAL_TYPE_LVDS |
0236         SIGNAL_TYPE_DISPLAY_PORT |
0237         SIGNAL_TYPE_DISPLAY_PORT_MST |
0238         SIGNAL_TYPE_EDP |
0239         SIGNAL_TYPE_HDMI_TYPE_A;
0240
0241     enc10->link_regs = link_regs;
0242     enc10->aux_regs = aux_regs;
0243     enc10->hpd_regs = hpd_regs;
0244     enc10->link_shift = link_shift;
0245     enc10->link_mask = link_mask;
0246
0247     switch (enc10->base.transmitter) {
0248     case TRANSMITTER_UNIPHY_A:
0249         enc10->base.preferred_engine = ENGINE_ID_DIGA;
0250     break;
0251     case TRANSMITTER_UNIPHY_B:
0252         enc10->base.preferred_engine = ENGINE_ID_DIGB;
0253     break;
0254     case TRANSMITTER_UNIPHY_C:
0255         enc10->base.preferred_engine = ENGINE_ID_DIGC;
0256     break;
0257     case TRANSMITTER_UNIPHY_D:
0258         enc10->base.preferred_engine = ENGINE_ID_DIGD;
0259     break;
0260     case TRANSMITTER_UNIPHY_E:
0261         enc10->base.preferred_engine = ENGINE_ID_DIGE;
0262     break;
0263     default:
0264         ASSERT_CRITICAL(false);
0265         enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0266     }
0267
0268     /* default to one to mirror Windows behavior */
0269     enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
0270
0271     if (bp_funcs->get_connector_speed_cap_info)
0272         result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
0273                         enc10->base.connector, &bp_cap_info);
0274
0275     /* Override features with DCE-specific values */
0276     if (result == BP_RESULT_OK) {
0277         enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
0278                 bp_cap_info.DP_HBR2_EN;
0279         enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
0280                 bp_cap_info.DP_HBR3_EN;
0281         enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
0282         enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
0283         enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
0284         enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
0285         enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
0286     } else {
0287         DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
0288                 __func__,
0289                 result);
0290     }
0291     if (enc10->base.ctx->dc->debug.hdmi20_disable) {
0292         enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
0293     }
0294 }