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0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 
0027 #include "dm_services.h"
0028 #include "dc.h"
0029 
0030 #include "dcn31/dcn31_init.h"
0031 
0032 #include "resource.h"
0033 #include "include/irq_service_interface.h"
0034 #include "dcn316_resource.h"
0035 
0036 #include "dcn20/dcn20_resource.h"
0037 #include "dcn30/dcn30_resource.h"
0038 #include "dcn31/dcn31_resource.h"
0039 
0040 #include "dcn10/dcn10_ipp.h"
0041 #include "dcn30/dcn30_hubbub.h"
0042 #include "dcn31/dcn31_hubbub.h"
0043 #include "dcn30/dcn30_mpc.h"
0044 #include "dcn31/dcn31_hubp.h"
0045 #include "irq/dcn31/irq_service_dcn31.h"
0046 #include "dcn30/dcn30_dpp.h"
0047 #include "dcn31/dcn31_optc.h"
0048 #include "dcn20/dcn20_hwseq.h"
0049 #include "dcn30/dcn30_hwseq.h"
0050 #include "dce110/dce110_hw_sequencer.h"
0051 #include "dcn30/dcn30_opp.h"
0052 #include "dcn20/dcn20_dsc.h"
0053 #include "dcn30/dcn30_vpg.h"
0054 #include "dcn30/dcn30_afmt.h"
0055 #include "dcn30/dcn30_dio_stream_encoder.h"
0056 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
0057 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
0058 #include "dcn31/dcn31_apg.h"
0059 #include "dcn31/dcn31_dio_link_encoder.h"
0060 #include "dcn31/dcn31_vpg.h"
0061 #include "dcn31/dcn31_afmt.h"
0062 #include "dce/dce_clock_source.h"
0063 #include "dce/dce_audio.h"
0064 #include "dce/dce_hwseq.h"
0065 #include "clk_mgr.h"
0066 #include "virtual/virtual_stream_encoder.h"
0067 #include "dce110/dce110_resource.h"
0068 #include "dml/display_mode_vba.h"
0069 #include "dml/dcn31/dcn31_fpu.h"
0070 #include "dcn31/dcn31_dccg.h"
0071 #include "dcn10/dcn10_resource.h"
0072 #include "dcn31/dcn31_panel_cntl.h"
0073 
0074 #include "dcn30/dcn30_dwb.h"
0075 #include "dcn30/dcn30_mmhubbub.h"
0076 
0077 #include "dcn/dcn_3_1_6_offset.h"
0078 #include "dcn/dcn_3_1_6_sh_mask.h"
0079 #include "dpcs/dpcs_4_2_3_offset.h"
0080 #include "dpcs/dpcs_4_2_3_sh_mask.h"
0081 
0082 #define regBIF_BX1_BIOS_SCRATCH_2                                                                       0x003a
0083 #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX                                                              1
0084 #define regBIF_BX1_BIOS_SCRATCH_3                                                                       0x003b
0085 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX                                                              1
0086 #define regBIF_BX1_BIOS_SCRATCH_6                                                                       0x003e
0087 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX                                                              1
0088 
0089 #define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
0090 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
0091 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
0092 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
0093 
0094 #define DCN_BASE__INST0_SEG0                       0x00000012
0095 #define DCN_BASE__INST0_SEG1                       0x000000C0
0096 #define DCN_BASE__INST0_SEG2                       0x000034C0
0097 #define DCN_BASE__INST0_SEG3                       0x00009000
0098 #define DCN_BASE__INST0_SEG4                       0x02403C00
0099 #define DCN_BASE__INST0_SEG5                       0
0100 
0101 #define DPCS_BASE__INST0_SEG0                      0x00000012
0102 #define DPCS_BASE__INST0_SEG1                      0x000000C0
0103 #define DPCS_BASE__INST0_SEG2                      0x000034C0
0104 #define DPCS_BASE__INST0_SEG3                      0x00009000
0105 #define DPCS_BASE__INST0_SEG4                      0x02403C00
0106 #define DPCS_BASE__INST0_SEG5                      0
0107 
0108 #define NBIO_BASE__INST0_SEG0                      0x00000000
0109 #define NBIO_BASE__INST0_SEG1                      0x00000014
0110 #define NBIO_BASE__INST0_SEG2                      0x00000D20
0111 #define NBIO_BASE__INST0_SEG3                      0x00010400
0112 #define NBIO_BASE__INST0_SEG4                      0x0241B000
0113 #define NBIO_BASE__INST0_SEG5                      0x04040000
0114 
0115 #include "reg_helper.h"
0116 #include "dce/dmub_abm.h"
0117 #include "dce/dmub_psr.h"
0118 #include "dce/dce_aux.h"
0119 #include "dce/dce_i2c.h"
0120 
0121 #include "dml/dcn30/display_mode_vba_30.h"
0122 #include "vm_helper.h"
0123 #include "dcn20/dcn20_vmid.h"
0124 
0125 #include "link_enc_cfg.h"
0126 
0127 #define DCN3_16_MAX_DET_SIZE 384
0128 #define DCN3_16_MIN_COMPBUF_SIZE_KB 128
0129 #define DCN3_16_CRB_SEGMENT_SIZE_KB 64
0130 
0131 enum dcn31_clk_src_array_id {
0132     DCN31_CLK_SRC_PLL0,
0133     DCN31_CLK_SRC_PLL1,
0134     DCN31_CLK_SRC_PLL2,
0135     DCN31_CLK_SRC_PLL3,
0136     DCN31_CLK_SRC_PLL4,
0137     DCN30_CLK_SRC_TOTAL
0138 };
0139 
0140 /* begin *********************
0141  * macros to expend register list macro defined in HW object header file
0142  */
0143 
0144 /* DCN */
0145 /* TODO awful hack. fixup dcn20_dwb.h */
0146 #undef BASE_INNER
0147 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0148 
0149 #define BASE(seg) BASE_INNER(seg)
0150 
0151 #define SR(reg_name)\
0152         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
0153                     reg ## reg_name
0154 
0155 #define SRI(reg_name, block, id)\
0156     .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0157                     reg ## block ## id ## _ ## reg_name
0158 
0159 #define SRI2(reg_name, block, id)\
0160     .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
0161                     reg ## reg_name
0162 
0163 #define SRIR(var_name, reg_name, block, id)\
0164     .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0165                     reg ## block ## id ## _ ## reg_name
0166 
0167 #define SRII(reg_name, block, id)\
0168     .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0169                     reg ## block ## id ## _ ## reg_name
0170 
0171 #define SRII_MPC_RMU(reg_name, block, id)\
0172     .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0173                     reg ## block ## id ## _ ## reg_name
0174 
0175 #define SRII_DWB(reg_name, temp_name, block, id)\
0176     .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
0177                     reg ## block ## id ## _ ## temp_name
0178 
0179 #define DCCG_SRII(reg_name, block, id)\
0180     .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0181                     reg ## block ## id ## _ ## reg_name
0182 
0183 #define VUPDATE_SRII(reg_name, block, id)\
0184     .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
0185                     reg ## reg_name ## _ ## block ## id
0186 
0187 /* NBIO */
0188 #define NBIO_BASE_INNER(seg) \
0189     NBIO_BASE__INST0_SEG ## seg
0190 
0191 #define NBIO_BASE(seg) \
0192     NBIO_BASE_INNER(seg)
0193 
0194 #define NBIO_SR(reg_name)\
0195         .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
0196                     regBIF_BX1_ ## reg_name
0197 
0198 static const struct bios_registers bios_regs = {
0199         NBIO_SR(BIOS_SCRATCH_3),
0200         NBIO_SR(BIOS_SCRATCH_6)
0201 };
0202 
0203 #define clk_src_regs(index, pllid)\
0204 [index] = {\
0205     CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
0206 }
0207 
0208 static const struct dce110_clk_src_regs clk_src_regs[] = {
0209     clk_src_regs(0, A),
0210     clk_src_regs(1, B),
0211     clk_src_regs(2, C),
0212     clk_src_regs(3, D),
0213     clk_src_regs(4, E)
0214 };
0215 
0216 static const struct dce110_clk_src_shift cs_shift = {
0217         CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
0218 };
0219 
0220 static const struct dce110_clk_src_mask cs_mask = {
0221         CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
0222 };
0223 
0224 #define abm_regs(id)\
0225 [id] = {\
0226         ABM_DCN302_REG_LIST(id)\
0227 }
0228 
0229 static const struct dce_abm_registers abm_regs[] = {
0230         abm_regs(0),
0231         abm_regs(1),
0232         abm_regs(2),
0233         abm_regs(3),
0234 };
0235 
0236 static const struct dce_abm_shift abm_shift = {
0237         ABM_MASK_SH_LIST_DCN30(__SHIFT)
0238 };
0239 
0240 static const struct dce_abm_mask abm_mask = {
0241         ABM_MASK_SH_LIST_DCN30(_MASK)
0242 };
0243 
0244 #define audio_regs(id)\
0245 [id] = {\
0246         AUD_COMMON_REG_LIST(id)\
0247 }
0248 
0249 static const struct dce_audio_registers audio_regs[] = {
0250     audio_regs(0),
0251     audio_regs(1),
0252     audio_regs(2),
0253     audio_regs(3),
0254     audio_regs(4),
0255     audio_regs(5),
0256     audio_regs(6)
0257 };
0258 
0259 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
0260         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
0261         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
0262         AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
0263 
0264 static const struct dce_audio_shift audio_shift = {
0265         DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
0266 };
0267 
0268 static const struct dce_audio_mask audio_mask = {
0269         DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
0270 };
0271 
0272 #define vpg_regs(id)\
0273 [id] = {\
0274     VPG_DCN31_REG_LIST(id)\
0275 }
0276 
0277 static const struct dcn31_vpg_registers vpg_regs[] = {
0278     vpg_regs(0),
0279     vpg_regs(1),
0280     vpg_regs(2),
0281     vpg_regs(3),
0282     vpg_regs(4),
0283     vpg_regs(5),
0284     vpg_regs(6),
0285     vpg_regs(7),
0286     vpg_regs(8),
0287     vpg_regs(9),
0288 };
0289 
0290 static const struct dcn31_vpg_shift vpg_shift = {
0291     DCN31_VPG_MASK_SH_LIST(__SHIFT)
0292 };
0293 
0294 static const struct dcn31_vpg_mask vpg_mask = {
0295     DCN31_VPG_MASK_SH_LIST(_MASK)
0296 };
0297 
0298 #define afmt_regs(id)\
0299 [id] = {\
0300     AFMT_DCN31_REG_LIST(id)\
0301 }
0302 
0303 static const struct dcn31_afmt_registers afmt_regs[] = {
0304     afmt_regs(0),
0305     afmt_regs(1),
0306     afmt_regs(2),
0307     afmt_regs(3),
0308     afmt_regs(4),
0309     afmt_regs(5)
0310 };
0311 
0312 static const struct dcn31_afmt_shift afmt_shift = {
0313     DCN31_AFMT_MASK_SH_LIST(__SHIFT)
0314 };
0315 
0316 static const struct dcn31_afmt_mask afmt_mask = {
0317     DCN31_AFMT_MASK_SH_LIST(_MASK)
0318 };
0319 
0320 
0321 #define apg_regs(id)\
0322 [id] = {\
0323     APG_DCN31_REG_LIST(id)\
0324 }
0325 
0326 static const struct dcn31_apg_registers apg_regs[] = {
0327     apg_regs(0),
0328     apg_regs(1),
0329     apg_regs(2),
0330     apg_regs(3)
0331 };
0332 
0333 static const struct dcn31_apg_shift apg_shift = {
0334     DCN31_APG_MASK_SH_LIST(__SHIFT)
0335 };
0336 
0337 static const struct dcn31_apg_mask apg_mask = {
0338         DCN31_APG_MASK_SH_LIST(_MASK)
0339 };
0340 
0341 
0342 #define stream_enc_regs(id)\
0343 [id] = {\
0344     SE_DCN3_REG_LIST(id)\
0345 }
0346 
0347 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
0348     stream_enc_regs(0),
0349     stream_enc_regs(1),
0350     stream_enc_regs(2),
0351     stream_enc_regs(3),
0352     stream_enc_regs(4)
0353 };
0354 
0355 static const struct dcn10_stream_encoder_shift se_shift = {
0356         SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0357 };
0358 
0359 static const struct dcn10_stream_encoder_mask se_mask = {
0360         SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
0361 };
0362 
0363 
0364 #define aux_regs(id)\
0365 [id] = {\
0366     DCN2_AUX_REG_LIST(id)\
0367 }
0368 
0369 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
0370         aux_regs(0),
0371         aux_regs(1),
0372         aux_regs(2),
0373         aux_regs(3),
0374         aux_regs(4)
0375 };
0376 
0377 #define hpd_regs(id)\
0378 [id] = {\
0379     HPD_REG_LIST(id)\
0380 }
0381 
0382 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
0383         hpd_regs(0),
0384         hpd_regs(1),
0385         hpd_regs(2),
0386         hpd_regs(3),
0387         hpd_regs(4)
0388 };
0389 
0390 #define link_regs(id, phyid)\
0391 [id] = {\
0392     LE_DCN31_REG_LIST(id), \
0393     UNIPHY_DCN2_REG_LIST(phyid), \
0394     DPCS_DCN31_REG_LIST(id), \
0395 }
0396 
0397 static const struct dce110_aux_registers_shift aux_shift = {
0398     DCN_AUX_MASK_SH_LIST(__SHIFT)
0399 };
0400 
0401 static const struct dce110_aux_registers_mask aux_mask = {
0402     DCN_AUX_MASK_SH_LIST(_MASK)
0403 };
0404 
0405 static const struct dcn10_link_enc_registers link_enc_regs[] = {
0406     link_regs(0, A),
0407     link_regs(1, B),
0408     link_regs(2, C),
0409     link_regs(3, D),
0410     link_regs(4, E)
0411 };
0412 
0413 static const struct dcn10_link_enc_shift le_shift = {
0414     LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
0415     DPCS_DCN31_MASK_SH_LIST(__SHIFT)
0416 };
0417 
0418 static const struct dcn10_link_enc_mask le_mask = {
0419     LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
0420     DPCS_DCN31_MASK_SH_LIST(_MASK)
0421 };
0422 
0423 
0424 
0425 #define hpo_dp_stream_encoder_reg_list(id)\
0426 [id] = {\
0427     DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
0428 }
0429 
0430 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
0431     hpo_dp_stream_encoder_reg_list(0),
0432     hpo_dp_stream_encoder_reg_list(1),
0433     hpo_dp_stream_encoder_reg_list(2),
0434     hpo_dp_stream_encoder_reg_list(3),
0435 };
0436 
0437 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
0438     DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
0439 };
0440 
0441 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
0442     DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
0443 };
0444 
0445 
0446 #define hpo_dp_link_encoder_reg_list(id)\
0447 [id] = {\
0448     DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
0449     DCN3_1_RDPCSTX_REG_LIST(0),\
0450     DCN3_1_RDPCSTX_REG_LIST(1),\
0451     DCN3_1_RDPCSTX_REG_LIST(2),\
0452     DCN3_1_RDPCSTX_REG_LIST(3),\
0453     DCN3_1_RDPCSTX_REG_LIST(4)\
0454 }
0455 
0456 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
0457     hpo_dp_link_encoder_reg_list(0),
0458     hpo_dp_link_encoder_reg_list(1),
0459 };
0460 
0461 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
0462     DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
0463 };
0464 
0465 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
0466     DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
0467 };
0468 
0469 
0470 #define dpp_regs(id)\
0471 [id] = {\
0472     DPP_REG_LIST_DCN30(id),\
0473 }
0474 
0475 static const struct dcn3_dpp_registers dpp_regs[] = {
0476     dpp_regs(0),
0477     dpp_regs(1),
0478     dpp_regs(2),
0479     dpp_regs(3)
0480 };
0481 
0482 static const struct dcn3_dpp_shift tf_shift = {
0483         DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
0484 };
0485 
0486 static const struct dcn3_dpp_mask tf_mask = {
0487         DPP_REG_LIST_SH_MASK_DCN30(_MASK)
0488 };
0489 
0490 #define opp_regs(id)\
0491 [id] = {\
0492     OPP_REG_LIST_DCN30(id),\
0493 }
0494 
0495 static const struct dcn20_opp_registers opp_regs[] = {
0496     opp_regs(0),
0497     opp_regs(1),
0498     opp_regs(2),
0499     opp_regs(3)
0500 };
0501 
0502 static const struct dcn20_opp_shift opp_shift = {
0503     OPP_MASK_SH_LIST_DCN20(__SHIFT)
0504 };
0505 
0506 static const struct dcn20_opp_mask opp_mask = {
0507     OPP_MASK_SH_LIST_DCN20(_MASK)
0508 };
0509 
0510 #define aux_engine_regs(id)\
0511 [id] = {\
0512     AUX_COMMON_REG_LIST0(id), \
0513     .AUXN_IMPCAL = 0, \
0514     .AUXP_IMPCAL = 0, \
0515     .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
0516 }
0517 
0518 static const struct dce110_aux_registers aux_engine_regs[] = {
0519         aux_engine_regs(0),
0520         aux_engine_regs(1),
0521         aux_engine_regs(2),
0522         aux_engine_regs(3),
0523         aux_engine_regs(4)
0524 };
0525 
0526 #define dwbc_regs_dcn3(id)\
0527 [id] = {\
0528     DWBC_COMMON_REG_LIST_DCN30(id),\
0529 }
0530 
0531 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
0532     dwbc_regs_dcn3(0),
0533 };
0534 
0535 static const struct dcn30_dwbc_shift dwbc30_shift = {
0536     DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0537 };
0538 
0539 static const struct dcn30_dwbc_mask dwbc30_mask = {
0540     DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
0541 };
0542 
0543 #define mcif_wb_regs_dcn3(id)\
0544 [id] = {\
0545     MCIF_WB_COMMON_REG_LIST_DCN30(id),\
0546 }
0547 
0548 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
0549     mcif_wb_regs_dcn3(0)
0550 };
0551 
0552 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
0553     MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0554 };
0555 
0556 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
0557     MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
0558 };
0559 
0560 #define dsc_regsDCN20(id)\
0561 [id] = {\
0562     DSC_REG_LIST_DCN20(id)\
0563 }
0564 
0565 static const struct dcn20_dsc_registers dsc_regs[] = {
0566     dsc_regsDCN20(0),
0567     dsc_regsDCN20(1),
0568     dsc_regsDCN20(2)
0569 };
0570 
0571 static const struct dcn20_dsc_shift dsc_shift = {
0572     DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
0573 };
0574 
0575 static const struct dcn20_dsc_mask dsc_mask = {
0576     DSC_REG_LIST_SH_MASK_DCN20(_MASK)
0577 };
0578 
0579 static const struct dcn30_mpc_registers mpc_regs = {
0580         MPC_REG_LIST_DCN3_0(0),
0581         MPC_REG_LIST_DCN3_0(1),
0582         MPC_REG_LIST_DCN3_0(2),
0583         MPC_REG_LIST_DCN3_0(3),
0584         MPC_OUT_MUX_REG_LIST_DCN3_0(0),
0585         MPC_OUT_MUX_REG_LIST_DCN3_0(1),
0586         MPC_OUT_MUX_REG_LIST_DCN3_0(2),
0587         MPC_OUT_MUX_REG_LIST_DCN3_0(3),
0588         MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
0589         MPC_RMU_REG_LIST_DCN3AG(0),
0590         MPC_RMU_REG_LIST_DCN3AG(1),
0591         //MPC_RMU_REG_LIST_DCN3AG(2),
0592         MPC_DWB_MUX_REG_LIST_DCN3_0(0),
0593 };
0594 
0595 static const struct dcn30_mpc_shift mpc_shift = {
0596     MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0597 };
0598 
0599 static const struct dcn30_mpc_mask mpc_mask = {
0600     MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
0601 };
0602 
0603 #define optc_regs(id)\
0604 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
0605 
0606 static const struct dcn_optc_registers optc_regs[] = {
0607     optc_regs(0),
0608     optc_regs(1),
0609     optc_regs(2),
0610     optc_regs(3)
0611 };
0612 
0613 static const struct dcn_optc_shift optc_shift = {
0614     OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
0615 };
0616 
0617 static const struct dcn_optc_mask optc_mask = {
0618     OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
0619 };
0620 
0621 #define hubp_regs(id)\
0622 [id] = {\
0623     HUBP_REG_LIST_DCN30(id)\
0624 }
0625 
0626 static const struct dcn_hubp2_registers hubp_regs[] = {
0627         hubp_regs(0),
0628         hubp_regs(1),
0629         hubp_regs(2),
0630         hubp_regs(3)
0631 };
0632 
0633 
0634 static const struct dcn_hubp2_shift hubp_shift = {
0635         HUBP_MASK_SH_LIST_DCN31(__SHIFT)
0636 };
0637 
0638 static const struct dcn_hubp2_mask hubp_mask = {
0639         HUBP_MASK_SH_LIST_DCN31(_MASK)
0640 };
0641 static const struct dcn_hubbub_registers hubbub_reg = {
0642         HUBBUB_REG_LIST_DCN31(0)
0643 };
0644 
0645 static const struct dcn_hubbub_shift hubbub_shift = {
0646         HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
0647 };
0648 
0649 static const struct dcn_hubbub_mask hubbub_mask = {
0650         HUBBUB_MASK_SH_LIST_DCN31(_MASK)
0651 };
0652 
0653 static const struct dccg_registers dccg_regs = {
0654         DCCG_REG_LIST_DCN31()
0655 };
0656 
0657 static const struct dccg_shift dccg_shift = {
0658         DCCG_MASK_SH_LIST_DCN31(__SHIFT)
0659 };
0660 
0661 static const struct dccg_mask dccg_mask = {
0662         DCCG_MASK_SH_LIST_DCN31(_MASK)
0663 };
0664 
0665 
0666 #define SRII2(reg_name_pre, reg_name_post, id)\
0667     .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
0668             ## id ## _ ## reg_name_post ## _BASE_IDX) + \
0669             reg ## reg_name_pre ## id ## _ ## reg_name_post
0670 
0671 
0672 #define HWSEQ_DCN31_REG_LIST()\
0673     SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
0674     SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
0675     SR(DIO_MEM_PWR_CTRL), \
0676     SR(ODM_MEM_PWR_CTRL3), \
0677     SR(DMU_MEM_PWR_CNTL), \
0678     SR(MMHUBBUB_MEM_PWR_CNTL), \
0679     SR(DCCG_GATE_DISABLE_CNTL), \
0680     SR(DCCG_GATE_DISABLE_CNTL2), \
0681     SR(DCFCLK_CNTL),\
0682     SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
0683     SRII(PIXEL_RATE_CNTL, OTG, 0), \
0684     SRII(PIXEL_RATE_CNTL, OTG, 1),\
0685     SRII(PIXEL_RATE_CNTL, OTG, 2),\
0686     SRII(PIXEL_RATE_CNTL, OTG, 3),\
0687     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
0688     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
0689     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
0690     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
0691     SR(MICROSECOND_TIME_BASE_DIV), \
0692     SR(MILLISECOND_TIME_BASE_DIV), \
0693     SR(DISPCLK_FREQ_CHANGE_CNTL), \
0694     SR(RBBMIF_TIMEOUT_DIS), \
0695     SR(RBBMIF_TIMEOUT_DIS_2), \
0696     SR(DCHUBBUB_CRC_CTRL), \
0697     SR(DPP_TOP0_DPP_CRC_CTRL), \
0698     SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
0699     SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
0700     SR(MPC_CRC_CTRL), \
0701     SR(MPC_CRC_RESULT_GB), \
0702     SR(MPC_CRC_RESULT_C), \
0703     SR(MPC_CRC_RESULT_AR), \
0704     SR(DOMAIN0_PG_CONFIG), \
0705     SR(DOMAIN1_PG_CONFIG), \
0706     SR(DOMAIN2_PG_CONFIG), \
0707     SR(DOMAIN3_PG_CONFIG), \
0708     SR(DOMAIN16_PG_CONFIG), \
0709     SR(DOMAIN17_PG_CONFIG), \
0710     SR(DOMAIN18_PG_CONFIG), \
0711     SR(DOMAIN0_PG_STATUS), \
0712     SR(DOMAIN1_PG_STATUS), \
0713     SR(DOMAIN2_PG_STATUS), \
0714     SR(DOMAIN3_PG_STATUS), \
0715     SR(DOMAIN16_PG_STATUS), \
0716     SR(DOMAIN17_PG_STATUS), \
0717     SR(DOMAIN18_PG_STATUS), \
0718     SR(D1VGA_CONTROL), \
0719     SR(D2VGA_CONTROL), \
0720     SR(D3VGA_CONTROL), \
0721     SR(D4VGA_CONTROL), \
0722     SR(D5VGA_CONTROL), \
0723     SR(D6VGA_CONTROL), \
0724     SR(DC_IP_REQUEST_CNTL), \
0725     SR(AZALIA_AUDIO_DTO), \
0726     SR(AZALIA_CONTROLLER_CLOCK_GATING), \
0727     SR(HPO_TOP_HW_CONTROL)
0728 
0729 static const struct dce_hwseq_registers hwseq_reg = {
0730         HWSEQ_DCN31_REG_LIST()
0731 };
0732 
0733 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
0734     HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
0735     HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
0736     HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
0737     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0738     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0739     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0740     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0741     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0742     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0743     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0744     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0745     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0746     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0747     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0748     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0749     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0750     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0751     HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0752     HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0753     HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0754     HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0755     HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0756     HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0757     HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0758     HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
0759     HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
0760     HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
0761     HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
0762     HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
0763     HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
0764     HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
0765     HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
0766     HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
0767 
0768 static const struct dce_hwseq_shift hwseq_shift = {
0769         HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
0770 };
0771 
0772 static const struct dce_hwseq_mask hwseq_mask = {
0773         HWSEQ_DCN31_MASK_SH_LIST(_MASK)
0774 };
0775 #define vmid_regs(id)\
0776 [id] = {\
0777         DCN20_VMID_REG_LIST(id)\
0778 }
0779 
0780 static const struct dcn_vmid_registers vmid_regs[] = {
0781     vmid_regs(0),
0782     vmid_regs(1),
0783     vmid_regs(2),
0784     vmid_regs(3),
0785     vmid_regs(4),
0786     vmid_regs(5),
0787     vmid_regs(6),
0788     vmid_regs(7),
0789     vmid_regs(8),
0790     vmid_regs(9),
0791     vmid_regs(10),
0792     vmid_regs(11),
0793     vmid_regs(12),
0794     vmid_regs(13),
0795     vmid_regs(14),
0796     vmid_regs(15)
0797 };
0798 
0799 static const struct dcn20_vmid_shift vmid_shifts = {
0800         DCN20_VMID_MASK_SH_LIST(__SHIFT)
0801 };
0802 
0803 static const struct dcn20_vmid_mask vmid_masks = {
0804         DCN20_VMID_MASK_SH_LIST(_MASK)
0805 };
0806 
0807 static const struct resource_caps res_cap_dcn31 = {
0808     .num_timing_generator = 4,
0809     .num_opp = 4,
0810     .num_video_plane = 4,
0811     .num_audio = 5,
0812     .num_stream_encoder = 5,
0813     .num_dig_link_enc = 5,
0814     .num_hpo_dp_stream_encoder = 4,
0815     .num_hpo_dp_link_encoder = 2,
0816     .num_pll = 5,
0817     .num_dwb = 1,
0818     .num_ddc = 5,
0819     .num_vmid = 16,
0820     .num_mpc_3dlut = 2,
0821     .num_dsc = 3,
0822 };
0823 
0824 static const struct dc_plane_cap plane_cap = {
0825     .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
0826     .blends_with_above = true,
0827     .blends_with_below = true,
0828     .per_pixel_alpha = true,
0829 
0830     .pixel_format_support = {
0831             .argb8888 = true,
0832             .nv12 = true,
0833             .fp16 = true,
0834             .p010 = true,
0835             .ayuv = false,
0836     },
0837 
0838     .max_upscale_factor = {
0839             .argb8888 = 16000,
0840             .nv12 = 16000,
0841             .fp16 = 16000
0842     },
0843 
0844     // 6:1 downscaling ratio: 1000/6 = 166.666
0845     .max_downscale_factor = {
0846             .argb8888 = 167,
0847             .nv12 = 167,
0848             .fp16 = 167
0849     },
0850     64,
0851     64
0852 };
0853 
0854 static const struct dc_debug_options debug_defaults_drv = {
0855     .disable_z10 = true, /*hw not support it*/
0856     .disable_dmcu = true,
0857     .force_abm_enable = false,
0858     .timing_trace = false,
0859     .clock_trace = true,
0860     .disable_pplib_clock_request = false,
0861     .pipe_split_policy = MPC_SPLIT_DYNAMIC,
0862     .force_single_disp_pipe_split = false,
0863     .disable_dcc = DCC_ENABLE,
0864     .vsr_support = true,
0865     .performance_trace = false,
0866     .max_downscale_src_width = 4096,/*upto true 4k*/
0867     .disable_pplib_wm_range = false,
0868     .scl_reset_length10 = true,
0869     .sanity_checks = false,
0870     .underflow_assert_delay_us = 0xFFFFFFFF,
0871     .dwb_fi_phase = -1, // -1 = disable,
0872     .dmub_command_table = true,
0873     .pstate_enabled = true,
0874     .use_max_lb = true,
0875     .enable_mem_low_power = {
0876         .bits = {
0877             .vga = true,
0878             .i2c = true,
0879             .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
0880             .dscl = true,
0881             .cm = true,
0882             .mpc = true,
0883             .optc = true,
0884             .vpg = true,
0885             .afmt = true,
0886         }
0887     },
0888     .optimize_edp_link_rate = true,
0889     .enable_sw_cntl_psr = true,
0890 };
0891 
0892 static const struct dc_debug_options debug_defaults_diags = {
0893     .disable_dmcu = true,
0894     .force_abm_enable = false,
0895     .timing_trace = true,
0896     .clock_trace = true,
0897     .disable_dpp_power_gate = true,
0898     .disable_hubp_power_gate = true,
0899     .disable_clock_gate = true,
0900     .disable_pplib_clock_request = true,
0901     .disable_pplib_wm_range = true,
0902     .disable_stutter = false,
0903     .scl_reset_length10 = true,
0904     .dwb_fi_phase = -1, // -1 = disable
0905     .dmub_command_table = true,
0906     .enable_tri_buf = true,
0907     .use_max_lb = true
0908 };
0909 
0910 static void dcn31_dpp_destroy(struct dpp **dpp)
0911 {
0912     kfree(TO_DCN20_DPP(*dpp));
0913     *dpp = NULL;
0914 }
0915 
0916 static struct dpp *dcn31_dpp_create(
0917     struct dc_context *ctx,
0918     uint32_t inst)
0919 {
0920     struct dcn3_dpp *dpp =
0921         kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
0922 
0923     if (!dpp)
0924         return NULL;
0925 
0926     if (dpp3_construct(dpp, ctx, inst,
0927             &dpp_regs[inst], &tf_shift, &tf_mask))
0928         return &dpp->base;
0929 
0930     BREAK_TO_DEBUGGER();
0931     kfree(dpp);
0932     return NULL;
0933 }
0934 
0935 static struct output_pixel_processor *dcn31_opp_create(
0936     struct dc_context *ctx, uint32_t inst)
0937 {
0938     struct dcn20_opp *opp =
0939         kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
0940 
0941     if (!opp) {
0942         BREAK_TO_DEBUGGER();
0943         return NULL;
0944     }
0945 
0946     dcn20_opp_construct(opp, ctx, inst,
0947             &opp_regs[inst], &opp_shift, &opp_mask);
0948     return &opp->base;
0949 }
0950 
0951 static struct dce_aux *dcn31_aux_engine_create(
0952     struct dc_context *ctx,
0953     uint32_t inst)
0954 {
0955     struct aux_engine_dce110 *aux_engine =
0956         kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
0957 
0958     if (!aux_engine)
0959         return NULL;
0960 
0961     dce110_aux_engine_construct(aux_engine, ctx, inst,
0962                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
0963                     &aux_engine_regs[inst],
0964                     &aux_mask,
0965                     &aux_shift,
0966                     ctx->dc->caps.extended_aux_timeout_support);
0967 
0968     return &aux_engine->base;
0969 }
0970 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
0971 
0972 static const struct dce_i2c_registers i2c_hw_regs[] = {
0973         i2c_inst_regs(1),
0974         i2c_inst_regs(2),
0975         i2c_inst_regs(3),
0976         i2c_inst_regs(4),
0977         i2c_inst_regs(5),
0978 };
0979 
0980 static const struct dce_i2c_shift i2c_shifts = {
0981         I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0982 };
0983 
0984 static const struct dce_i2c_mask i2c_masks = {
0985         I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
0986 };
0987 
0988 static struct dce_i2c_hw *dcn31_i2c_hw_create(
0989     struct dc_context *ctx,
0990     uint32_t inst)
0991 {
0992     struct dce_i2c_hw *dce_i2c_hw =
0993         kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
0994 
0995     if (!dce_i2c_hw)
0996         return NULL;
0997 
0998     dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
0999                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1000 
1001     return dce_i2c_hw;
1002 }
1003 static struct mpc *dcn31_mpc_create(
1004         struct dc_context *ctx,
1005         int num_mpcc,
1006         int num_rmu)
1007 {
1008     struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1009                       GFP_KERNEL);
1010 
1011     if (!mpc30)
1012         return NULL;
1013 
1014     dcn30_mpc_construct(mpc30, ctx,
1015             &mpc_regs,
1016             &mpc_shift,
1017             &mpc_mask,
1018             num_mpcc,
1019             num_rmu);
1020 
1021     return &mpc30->base;
1022 }
1023 
1024 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1025 {
1026     int i;
1027 
1028     struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1029                       GFP_KERNEL);
1030 
1031     if (!hubbub3)
1032         return NULL;
1033 
1034     hubbub31_construct(hubbub3, ctx,
1035             &hubbub_reg,
1036             &hubbub_shift,
1037             &hubbub_mask,
1038             dcn3_16_ip.det_buffer_size_kbytes,
1039             dcn3_16_ip.pixel_chunk_size_kbytes,
1040             dcn3_16_ip.config_return_buffer_size_in_kbytes);
1041 
1042 
1043     for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1044         struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1045 
1046         vmid->ctx = ctx;
1047 
1048         vmid->regs = &vmid_regs[i];
1049         vmid->shifts = &vmid_shifts;
1050         vmid->masks = &vmid_masks;
1051     }
1052 
1053     return &hubbub3->base;
1054 }
1055 
1056 static struct timing_generator *dcn31_timing_generator_create(
1057         struct dc_context *ctx,
1058         uint32_t instance)
1059 {
1060     struct optc *tgn10 =
1061         kzalloc(sizeof(struct optc), GFP_KERNEL);
1062 
1063     if (!tgn10)
1064         return NULL;
1065 
1066     tgn10->base.inst = instance;
1067     tgn10->base.ctx = ctx;
1068 
1069     tgn10->tg_regs = &optc_regs[instance];
1070     tgn10->tg_shift = &optc_shift;
1071     tgn10->tg_mask = &optc_mask;
1072 
1073     dcn31_timing_generator_init(tgn10);
1074 
1075     return &tgn10->base;
1076 }
1077 
1078 static const struct encoder_feature_support link_enc_feature = {
1079         .max_hdmi_deep_color = COLOR_DEPTH_121212,
1080         .max_hdmi_pixel_clock = 600000,
1081         .hdmi_ycbcr420_supported = true,
1082         .dp_ycbcr420_supported = true,
1083         .fec_supported = true,
1084         .flags.bits.IS_HBR2_CAPABLE = true,
1085         .flags.bits.IS_HBR3_CAPABLE = true,
1086         .flags.bits.IS_TPS3_CAPABLE = true,
1087         .flags.bits.IS_TPS4_CAPABLE = true
1088 };
1089 
1090 static struct link_encoder *dcn31_link_encoder_create(
1091     struct dc_context *ctx,
1092     const struct encoder_init_data *enc_init_data)
1093 {
1094     struct dcn20_link_encoder *enc20 =
1095         kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1096 
1097     if (!enc20)
1098         return NULL;
1099 
1100     dcn31_link_encoder_construct(enc20,
1101             enc_init_data,
1102             &link_enc_feature,
1103             &link_enc_regs[enc_init_data->transmitter],
1104             &link_enc_aux_regs[enc_init_data->channel - 1],
1105             &link_enc_hpd_regs[enc_init_data->hpd_source],
1106             &le_shift,
1107             &le_mask);
1108 
1109     return &enc20->enc10.base;
1110 }
1111 
1112 /* Create a minimal link encoder object not associated with a particular
1113  * physical connector.
1114  * resource_funcs.link_enc_create_minimal
1115  */
1116 static struct link_encoder *dcn31_link_enc_create_minimal(
1117         struct dc_context *ctx, enum engine_id eng_id)
1118 {
1119     struct dcn20_link_encoder *enc20;
1120 
1121     if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1122         return NULL;
1123 
1124     enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1125     if (!enc20)
1126         return NULL;
1127 
1128     dcn31_link_encoder_construct_minimal(
1129             enc20,
1130             ctx,
1131             &link_enc_feature,
1132             &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1133             eng_id);
1134 
1135     return &enc20->enc10.base;
1136 }
1137 
1138 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1139 {
1140     struct dcn31_panel_cntl *panel_cntl =
1141         kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1142 
1143     if (!panel_cntl)
1144         return NULL;
1145 
1146     dcn31_panel_cntl_construct(panel_cntl, init_data);
1147 
1148     return &panel_cntl->base;
1149 }
1150 
1151 static void read_dce_straps(
1152     struct dc_context *ctx,
1153     struct resource_straps *straps)
1154 {
1155     generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1156         FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1157 
1158 }
1159 
1160 static struct audio *dcn31_create_audio(
1161         struct dc_context *ctx, unsigned int inst)
1162 {
1163     return dce_audio_create(ctx, inst,
1164             &audio_regs[inst], &audio_shift, &audio_mask);
1165 }
1166 
1167 static struct vpg *dcn31_vpg_create(
1168     struct dc_context *ctx,
1169     uint32_t inst)
1170 {
1171     struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1172 
1173     if (!vpg31)
1174         return NULL;
1175 
1176     vpg31_construct(vpg31, ctx, inst,
1177             &vpg_regs[inst],
1178             &vpg_shift,
1179             &vpg_mask);
1180 
1181     return &vpg31->base;
1182 }
1183 
1184 static struct afmt *dcn31_afmt_create(
1185     struct dc_context *ctx,
1186     uint32_t inst)
1187 {
1188     struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1189 
1190     if (!afmt31)
1191         return NULL;
1192 
1193     afmt31_construct(afmt31, ctx, inst,
1194             &afmt_regs[inst],
1195             &afmt_shift,
1196             &afmt_mask);
1197 
1198     // Light sleep by default, no need to power down here
1199 
1200     return &afmt31->base;
1201 }
1202 
1203 
1204 static struct apg *dcn31_apg_create(
1205     struct dc_context *ctx,
1206     uint32_t inst)
1207 {
1208     struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1209 
1210     if (!apg31)
1211         return NULL;
1212 
1213     apg31_construct(apg31, ctx, inst,
1214             &apg_regs[inst],
1215             &apg_shift,
1216             &apg_mask);
1217 
1218     return &apg31->base;
1219 }
1220 
1221 
1222 static struct stream_encoder *dcn316_stream_encoder_create(
1223     enum engine_id eng_id,
1224     struct dc_context *ctx)
1225 {
1226     struct dcn10_stream_encoder *enc1;
1227     struct vpg *vpg;
1228     struct afmt *afmt;
1229     int vpg_inst;
1230     int afmt_inst;
1231 
1232     /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1233     if (eng_id <= ENGINE_ID_DIGF) {
1234         vpg_inst = eng_id;
1235         afmt_inst = eng_id;
1236     } else
1237         return NULL;
1238 
1239     enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1240     vpg = dcn31_vpg_create(ctx, vpg_inst);
1241     afmt = dcn31_afmt_create(ctx, afmt_inst);
1242 
1243     if (!enc1 || !vpg || !afmt) {
1244         kfree(enc1);
1245         kfree(vpg);
1246         kfree(afmt);
1247         return NULL;
1248     }
1249 
1250     dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1251                     eng_id, vpg, afmt,
1252                     &stream_enc_regs[eng_id],
1253                     &se_shift, &se_mask);
1254 
1255     return &enc1->base;
1256 }
1257 
1258 
1259 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1260     enum engine_id eng_id,
1261     struct dc_context *ctx)
1262 {
1263     struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1264     struct vpg *vpg;
1265     struct apg *apg;
1266     uint32_t hpo_dp_inst;
1267     uint32_t vpg_inst;
1268     uint32_t apg_inst;
1269 
1270     ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1271     hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1272 
1273     /* Mapping of VPG register blocks to HPO DP block instance:
1274      * VPG[6] -> HPO_DP[0]
1275      * VPG[7] -> HPO_DP[1]
1276      * VPG[8] -> HPO_DP[2]
1277      * VPG[9] -> HPO_DP[3]
1278      */
1279     vpg_inst = hpo_dp_inst + 6;
1280 
1281     /* Mapping of APG register blocks to HPO DP block instance:
1282      * APG[0] -> HPO_DP[0]
1283      * APG[1] -> HPO_DP[1]
1284      * APG[2] -> HPO_DP[2]
1285      * APG[3] -> HPO_DP[3]
1286      */
1287     apg_inst = hpo_dp_inst;
1288 
1289     /* allocate HPO stream encoder and create VPG sub-block */
1290     hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1291     vpg = dcn31_vpg_create(ctx, vpg_inst);
1292     apg = dcn31_apg_create(ctx, apg_inst);
1293 
1294     if (!hpo_dp_enc31 || !vpg || !apg) {
1295         kfree(hpo_dp_enc31);
1296         kfree(vpg);
1297         kfree(apg);
1298         return NULL;
1299     }
1300 
1301     dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1302                     hpo_dp_inst, eng_id, vpg, apg,
1303                     &hpo_dp_stream_enc_regs[hpo_dp_inst],
1304                     &hpo_dp_se_shift, &hpo_dp_se_mask);
1305 
1306     return &hpo_dp_enc31->base;
1307 }
1308 
1309 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1310     uint8_t inst,
1311     struct dc_context *ctx)
1312 {
1313     struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1314 
1315     /* allocate HPO link encoder */
1316     hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1317 
1318     hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1319                     &hpo_dp_link_enc_regs[inst],
1320                     &hpo_dp_le_shift, &hpo_dp_le_mask);
1321 
1322     return &hpo_dp_enc31->base;
1323 }
1324 
1325 
1326 static struct dce_hwseq *dcn31_hwseq_create(
1327     struct dc_context *ctx)
1328 {
1329     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1330 
1331     if (hws) {
1332         hws->ctx = ctx;
1333         hws->regs = &hwseq_reg;
1334         hws->shifts = &hwseq_shift;
1335         hws->masks = &hwseq_mask;
1336         /* DCN3.1 FPGA Workaround
1337          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1338          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1339          * function core_link_enable_stream
1340          */
1341         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1342             hws->wa.dp_hpo_and_otg_sequence = true;
1343     }
1344     return hws;
1345 }
1346 static const struct resource_create_funcs res_create_funcs = {
1347     .read_dce_straps = read_dce_straps,
1348     .create_audio = dcn31_create_audio,
1349     .create_stream_encoder = dcn316_stream_encoder_create,
1350     .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1351     .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1352     .create_hwseq = dcn31_hwseq_create,
1353 };
1354 
1355 static const struct resource_create_funcs res_create_maximus_funcs = {
1356     .read_dce_straps = NULL,
1357     .create_audio = NULL,
1358     .create_stream_encoder = NULL,
1359     .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1360     .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1361     .create_hwseq = dcn31_hwseq_create,
1362 };
1363 
1364 static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)
1365 {
1366     unsigned int i;
1367 
1368     for (i = 0; i < pool->base.stream_enc_count; i++) {
1369         if (pool->base.stream_enc[i] != NULL) {
1370             if (pool->base.stream_enc[i]->vpg != NULL) {
1371                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1372                 pool->base.stream_enc[i]->vpg = NULL;
1373             }
1374             if (pool->base.stream_enc[i]->afmt != NULL) {
1375                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1376                 pool->base.stream_enc[i]->afmt = NULL;
1377             }
1378             kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1379             pool->base.stream_enc[i] = NULL;
1380         }
1381     }
1382 
1383     for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1384         if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1385             if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1386                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1387                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1388             }
1389             if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1390                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1391                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1392             }
1393             kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1394             pool->base.hpo_dp_stream_enc[i] = NULL;
1395         }
1396     }
1397 
1398     for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1399         if (pool->base.hpo_dp_link_enc[i] != NULL) {
1400             kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1401             pool->base.hpo_dp_link_enc[i] = NULL;
1402         }
1403     }
1404 
1405     for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1406         if (pool->base.dscs[i] != NULL)
1407             dcn20_dsc_destroy(&pool->base.dscs[i]);
1408     }
1409 
1410     if (pool->base.mpc != NULL) {
1411         kfree(TO_DCN20_MPC(pool->base.mpc));
1412         pool->base.mpc = NULL;
1413     }
1414     if (pool->base.hubbub != NULL) {
1415         kfree(pool->base.hubbub);
1416         pool->base.hubbub = NULL;
1417     }
1418     for (i = 0; i < pool->base.pipe_count; i++) {
1419         if (pool->base.dpps[i] != NULL)
1420             dcn31_dpp_destroy(&pool->base.dpps[i]);
1421 
1422         if (pool->base.ipps[i] != NULL)
1423             pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1424 
1425         if (pool->base.hubps[i] != NULL) {
1426             kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1427             pool->base.hubps[i] = NULL;
1428         }
1429 
1430         if (pool->base.irqs != NULL) {
1431             dal_irq_service_destroy(&pool->base.irqs);
1432         }
1433     }
1434 
1435     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1436         if (pool->base.engines[i] != NULL)
1437             dce110_engine_destroy(&pool->base.engines[i]);
1438         if (pool->base.hw_i2cs[i] != NULL) {
1439             kfree(pool->base.hw_i2cs[i]);
1440             pool->base.hw_i2cs[i] = NULL;
1441         }
1442         if (pool->base.sw_i2cs[i] != NULL) {
1443             kfree(pool->base.sw_i2cs[i]);
1444             pool->base.sw_i2cs[i] = NULL;
1445         }
1446     }
1447 
1448     for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1449         if (pool->base.opps[i] != NULL)
1450             pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1451     }
1452 
1453     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1454         if (pool->base.timing_generators[i] != NULL)    {
1455             kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1456             pool->base.timing_generators[i] = NULL;
1457         }
1458     }
1459 
1460     for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1461         if (pool->base.dwbc[i] != NULL) {
1462             kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1463             pool->base.dwbc[i] = NULL;
1464         }
1465         if (pool->base.mcif_wb[i] != NULL) {
1466             kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1467             pool->base.mcif_wb[i] = NULL;
1468         }
1469     }
1470 
1471     for (i = 0; i < pool->base.audio_count; i++) {
1472         if (pool->base.audios[i])
1473             dce_aud_destroy(&pool->base.audios[i]);
1474     }
1475 
1476     for (i = 0; i < pool->base.clk_src_count; i++) {
1477         if (pool->base.clock_sources[i] != NULL) {
1478             dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1479             pool->base.clock_sources[i] = NULL;
1480         }
1481     }
1482 
1483     for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1484         if (pool->base.mpc_lut[i] != NULL) {
1485             dc_3dlut_func_release(pool->base.mpc_lut[i]);
1486             pool->base.mpc_lut[i] = NULL;
1487         }
1488         if (pool->base.mpc_shaper[i] != NULL) {
1489             dc_transfer_func_release(pool->base.mpc_shaper[i]);
1490             pool->base.mpc_shaper[i] = NULL;
1491         }
1492     }
1493 
1494     if (pool->base.dp_clock_source != NULL) {
1495         dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1496         pool->base.dp_clock_source = NULL;
1497     }
1498 
1499     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1500         if (pool->base.multiple_abms[i] != NULL)
1501             dce_abm_destroy(&pool->base.multiple_abms[i]);
1502     }
1503 
1504     if (pool->base.psr != NULL)
1505         dmub_psr_destroy(&pool->base.psr);
1506 
1507     if (pool->base.dccg != NULL)
1508         dcn_dccg_destroy(&pool->base.dccg);
1509 }
1510 
1511 static struct hubp *dcn31_hubp_create(
1512     struct dc_context *ctx,
1513     uint32_t inst)
1514 {
1515     struct dcn20_hubp *hubp2 =
1516         kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1517 
1518     if (!hubp2)
1519         return NULL;
1520 
1521     if (hubp31_construct(hubp2, ctx, inst,
1522             &hubp_regs[inst], &hubp_shift, &hubp_mask))
1523         return &hubp2->base;
1524 
1525     BREAK_TO_DEBUGGER();
1526     kfree(hubp2);
1527     return NULL;
1528 }
1529 
1530 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1531 {
1532     int i;
1533     uint32_t pipe_count = pool->res_cap->num_dwb;
1534 
1535     for (i = 0; i < pipe_count; i++) {
1536         struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1537                             GFP_KERNEL);
1538 
1539         if (!dwbc30) {
1540             dm_error("DC: failed to create dwbc30!\n");
1541             return false;
1542         }
1543 
1544         dcn30_dwbc_construct(dwbc30, ctx,
1545                 &dwbc30_regs[i],
1546                 &dwbc30_shift,
1547                 &dwbc30_mask,
1548                 i);
1549 
1550         pool->dwbc[i] = &dwbc30->base;
1551     }
1552     return true;
1553 }
1554 
1555 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1556 {
1557     int i;
1558     uint32_t pipe_count = pool->res_cap->num_dwb;
1559 
1560     for (i = 0; i < pipe_count; i++) {
1561         struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1562                             GFP_KERNEL);
1563 
1564         if (!mcif_wb30) {
1565             dm_error("DC: failed to create mcif_wb30!\n");
1566             return false;
1567         }
1568 
1569         dcn30_mmhubbub_construct(mcif_wb30, ctx,
1570                 &mcif_wb30_regs[i],
1571                 &mcif_wb30_shift,
1572                 &mcif_wb30_mask,
1573                 i);
1574 
1575         pool->mcif_wb[i] = &mcif_wb30->base;
1576     }
1577     return true;
1578 }
1579 
1580 static struct display_stream_compressor *dcn31_dsc_create(
1581     struct dc_context *ctx, uint32_t inst)
1582 {
1583     struct dcn20_dsc *dsc =
1584         kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1585 
1586     if (!dsc) {
1587         BREAK_TO_DEBUGGER();
1588         return NULL;
1589     }
1590 
1591     dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1592     return &dsc->base;
1593 }
1594 
1595 static void dcn316_destroy_resource_pool(struct resource_pool **pool)
1596 {
1597     struct dcn316_resource_pool *dcn31_pool = TO_DCN316_RES_POOL(*pool);
1598 
1599     dcn316_resource_destruct(dcn31_pool);
1600     kfree(dcn31_pool);
1601     *pool = NULL;
1602 }
1603 
1604 static struct clock_source *dcn31_clock_source_create(
1605         struct dc_context *ctx,
1606         struct dc_bios *bios,
1607         enum clock_source_id id,
1608         const struct dce110_clk_src_regs *regs,
1609         bool dp_clk_src)
1610 {
1611     struct dce110_clk_src *clk_src =
1612         kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1613 
1614     if (!clk_src)
1615         return NULL;
1616 
1617     if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1618             regs, &cs_shift, &cs_mask)) {
1619         clk_src->base.dp_clk_src = dp_clk_src;
1620         return &clk_src->base;
1621     }
1622 
1623     kfree(clk_src);
1624 
1625     BREAK_TO_DEBUGGER();
1626     return NULL;
1627 }
1628 
1629 static bool is_dual_plane(enum surface_pixel_format format)
1630 {
1631     return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1632 }
1633 
1634 static int dcn316_populate_dml_pipes_from_context(
1635     struct dc *dc, struct dc_state *context,
1636     display_e2e_pipe_params_st *pipes,
1637     bool fast_validate)
1638 {
1639     int i, pipe_cnt;
1640     struct resource_context *res_ctx = &context->res_ctx;
1641     struct pipe_ctx *pipe;
1642     const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;
1643 
1644     DC_FP_START();
1645     dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1646     DC_FP_END();
1647 
1648     for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1649         struct dc_crtc_timing *timing;
1650 
1651         if (!res_ctx->pipe_ctx[i].stream)
1652             continue;
1653         pipe = &res_ctx->pipe_ctx[i];
1654         timing = &pipe->stream->timing;
1655 
1656         /*
1657          * Immediate flip can be set dynamically after enabling the plane.
1658          * We need to require support for immediate flip or underflow can be
1659          * intermittently experienced depending on peak b/w requirements.
1660          */
1661         pipes[pipe_cnt].pipe.src.immediate_flip = true;
1662 
1663         pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1664         pipes[pipe_cnt].pipe.src.gpuvm = true;
1665         pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1666         pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1667         pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1668         DC_FP_START();
1669         dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1670         DC_FP_END();
1671 
1672         if (pipes[pipe_cnt].dout.dsc_enable) {
1673             switch (timing->display_color_depth) {
1674             case COLOR_DEPTH_888:
1675                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1676                 break;
1677             case COLOR_DEPTH_101010:
1678                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1679                 break;
1680             case COLOR_DEPTH_121212:
1681                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1682                 break;
1683             default:
1684                 ASSERT(0);
1685                 break;
1686             }
1687         }
1688 
1689         pipe_cnt++;
1690     }
1691 
1692     if (pipe_cnt)
1693         context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1694                 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_16_CRB_SEGMENT_SIZE_KB;
1695     if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE)
1696         context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE;
1697     ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE);
1698     dc->config.enable_4to1MPC = false;
1699     if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1700         if (is_dual_plane(pipe->plane_state->format)
1701                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1702             dc->config.enable_4to1MPC = true;
1703             context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1704                     (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / 4) * DCN3_16_CRB_SEGMENT_SIZE_KB;
1705         } else if (!is_dual_plane(pipe->plane_state->format)) {
1706             context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1707             pipes[0].pipe.src.unbounded_req_mode = true;
1708         }
1709     }
1710 
1711     return pipe_cnt;
1712 }
1713 
1714 static struct dc_cap_funcs cap_funcs = {
1715     .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1716 };
1717 
1718 static struct resource_funcs dcn316_res_pool_funcs = {
1719     .destroy = dcn316_destroy_resource_pool,
1720     .link_enc_create = dcn31_link_encoder_create,
1721     .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1722     .link_encs_assign = link_enc_cfg_link_encs_assign,
1723     .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1724     .panel_cntl_create = dcn31_panel_cntl_create,
1725     .validate_bandwidth = dcn31_validate_bandwidth,
1726     .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1727     .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1728     .populate_dml_pipes = dcn316_populate_dml_pipes_from_context,
1729     .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1730     .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1731     .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1732     .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1733     .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1734     .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1735     .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1736     .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1737     .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1738     .update_bw_bounding_box = dcn316_update_bw_bounding_box,
1739     .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1740 };
1741 
1742 static bool dcn316_resource_construct(
1743     uint8_t num_virtual_links,
1744     struct dc *dc,
1745     struct dcn316_resource_pool *pool)
1746 {
1747     int i;
1748     struct dc_context *ctx = dc->ctx;
1749     struct irq_service_init_data init_data;
1750 
1751     ctx->dc_bios->regs = &bios_regs;
1752 
1753     pool->base.res_cap = &res_cap_dcn31;
1754 
1755     pool->base.funcs = &dcn316_res_pool_funcs;
1756 
1757     /*************************************************
1758      *  Resource + asic cap harcoding                *
1759      *************************************************/
1760     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1761     pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1762     pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1763     dc->caps.max_downscale_ratio = 600;
1764     dc->caps.i2c_speed_in_khz = 100;
1765     dc->caps.i2c_speed_in_khz_hdcp = 100;
1766     dc->caps.max_cursor_size = 256;
1767     dc->caps.min_horizontal_blanking_period = 80;
1768     dc->caps.dmdata_alloc_size = 2048;
1769     dc->caps.max_slave_planes = 2;
1770     dc->caps.max_slave_yuv_planes = 2;
1771     dc->caps.max_slave_rgb_planes = 2;
1772     dc->caps.post_blend_color_processing = true;
1773     dc->caps.force_dp_tps4_for_cp2520 = true;
1774     dc->caps.dp_hpo = true;
1775     dc->caps.dp_hdmi21_pcon_support = true;
1776     dc->caps.edp_dsc_support = true;
1777     dc->caps.extended_aux_timeout_support = true;
1778     dc->caps.dmcub_support = true;
1779     dc->caps.is_apu = true;
1780 
1781     /* Color pipeline capabilities */
1782     dc->caps.color.dpp.dcn_arch = 1;
1783     dc->caps.color.dpp.input_lut_shared = 0;
1784     dc->caps.color.dpp.icsc = 1;
1785     dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1786     dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1787     dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1788     dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1789     dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1790     dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1791     dc->caps.color.dpp.post_csc = 1;
1792     dc->caps.color.dpp.gamma_corr = 1;
1793     dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1794 
1795     dc->caps.color.dpp.hw_3d_lut = 1;
1796     dc->caps.color.dpp.ogam_ram = 1;
1797     // no OGAM ROM on DCN301
1798     dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1799     dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1800     dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1801     dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1802     dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1803     dc->caps.color.dpp.ocsc = 0;
1804 
1805     dc->caps.color.mpc.gamut_remap = 1;
1806     dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1807     dc->caps.color.mpc.ogam_ram = 1;
1808     dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1809     dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1810     dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1811     dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1812     dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1813     dc->caps.color.mpc.ocsc = 1;
1814 
1815     /* read VBIOS LTTPR caps */
1816     {
1817         if (ctx->dc_bios->funcs->get_lttpr_caps) {
1818             enum bp_result bp_query_result;
1819             uint8_t is_vbios_lttpr_enable = 0;
1820 
1821             bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1822             dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1823         }
1824 
1825         /* interop bit is implicit */
1826         {
1827             dc->caps.vbios_lttpr_aware = true;
1828         }
1829     }
1830 
1831     if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1832         dc->debug = debug_defaults_drv;
1833     else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1834         dc->debug = debug_defaults_diags;
1835     } else
1836         dc->debug = debug_defaults_diags;
1837     // Init the vm_helper
1838     if (dc->vm_helper)
1839         vm_helper_init(dc->vm_helper, 16);
1840 
1841     /*************************************************
1842      *  Create resources                             *
1843      *************************************************/
1844 
1845     /* Clock Sources for Pixel Clock*/
1846     pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1847             dcn31_clock_source_create(ctx, ctx->dc_bios,
1848                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1849                 &clk_src_regs[0], false);
1850     pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1851             dcn31_clock_source_create(ctx, ctx->dc_bios,
1852                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1853                 &clk_src_regs[1], false);
1854     pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1855             dcn31_clock_source_create(ctx, ctx->dc_bios,
1856                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1857                 &clk_src_regs[2], false);
1858     pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1859             dcn31_clock_source_create(ctx, ctx->dc_bios,
1860                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1861                 &clk_src_regs[3], false);
1862     pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1863             dcn31_clock_source_create(ctx, ctx->dc_bios,
1864                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1865                 &clk_src_regs[4], false);
1866 
1867     pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1868 
1869     /* todo: not reuse phy_pll registers */
1870     pool->base.dp_clock_source =
1871             dcn31_clock_source_create(ctx, ctx->dc_bios,
1872                 CLOCK_SOURCE_ID_DP_DTO,
1873                 &clk_src_regs[0], true);
1874 
1875     for (i = 0; i < pool->base.clk_src_count; i++) {
1876         if (pool->base.clock_sources[i] == NULL) {
1877             dm_error("DC: failed to create clock sources!\n");
1878             BREAK_TO_DEBUGGER();
1879             goto create_fail;
1880         }
1881     }
1882 
1883     /* TODO: DCCG */
1884     pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1885     if (pool->base.dccg == NULL) {
1886         dm_error("DC: failed to create dccg!\n");
1887         BREAK_TO_DEBUGGER();
1888         goto create_fail;
1889     }
1890 
1891     /* TODO: IRQ */
1892     init_data.ctx = dc->ctx;
1893     pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
1894     if (!pool->base.irqs)
1895         goto create_fail;
1896 
1897     /* HUBBUB */
1898     pool->base.hubbub = dcn31_hubbub_create(ctx);
1899     if (pool->base.hubbub == NULL) {
1900         BREAK_TO_DEBUGGER();
1901         dm_error("DC: failed to create hubbub!\n");
1902         goto create_fail;
1903     }
1904 
1905     /* HUBPs, DPPs, OPPs and TGs */
1906     for (i = 0; i < pool->base.pipe_count; i++) {
1907         pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
1908         if (pool->base.hubps[i] == NULL) {
1909             BREAK_TO_DEBUGGER();
1910             dm_error(
1911                 "DC: failed to create hubps!\n");
1912             goto create_fail;
1913         }
1914 
1915         pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
1916         if (pool->base.dpps[i] == NULL) {
1917             BREAK_TO_DEBUGGER();
1918             dm_error(
1919                 "DC: failed to create dpps!\n");
1920             goto create_fail;
1921         }
1922     }
1923 
1924     for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1925         pool->base.opps[i] = dcn31_opp_create(ctx, i);
1926         if (pool->base.opps[i] == NULL) {
1927             BREAK_TO_DEBUGGER();
1928             dm_error(
1929                 "DC: failed to create output pixel processor!\n");
1930             goto create_fail;
1931         }
1932     }
1933 
1934     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1935         pool->base.timing_generators[i] = dcn31_timing_generator_create(
1936                 ctx, i);
1937         if (pool->base.timing_generators[i] == NULL) {
1938             BREAK_TO_DEBUGGER();
1939             dm_error("DC: failed to create tg!\n");
1940             goto create_fail;
1941         }
1942     }
1943     pool->base.timing_generator_count = i;
1944 
1945     /* PSR */
1946     pool->base.psr = dmub_psr_create(ctx);
1947     if (pool->base.psr == NULL) {
1948         dm_error("DC: failed to create psr obj!\n");
1949         BREAK_TO_DEBUGGER();
1950         goto create_fail;
1951     }
1952 
1953     /* ABM */
1954     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1955         pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1956                 &abm_regs[i],
1957                 &abm_shift,
1958                 &abm_mask);
1959         if (pool->base.multiple_abms[i] == NULL) {
1960             dm_error("DC: failed to create abm for pipe %d!\n", i);
1961             BREAK_TO_DEBUGGER();
1962             goto create_fail;
1963         }
1964     }
1965 
1966     /* MPC and DSC */
1967     pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1968     if (pool->base.mpc == NULL) {
1969         BREAK_TO_DEBUGGER();
1970         dm_error("DC: failed to create mpc!\n");
1971         goto create_fail;
1972     }
1973 
1974     for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1975         pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
1976         if (pool->base.dscs[i] == NULL) {
1977             BREAK_TO_DEBUGGER();
1978             dm_error("DC: failed to create display stream compressor %d!\n", i);
1979             goto create_fail;
1980         }
1981     }
1982 
1983     /* DWB and MMHUBBUB */
1984     if (!dcn31_dwbc_create(ctx, &pool->base)) {
1985         BREAK_TO_DEBUGGER();
1986         dm_error("DC: failed to create dwbc!\n");
1987         goto create_fail;
1988     }
1989 
1990     if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
1991         BREAK_TO_DEBUGGER();
1992         dm_error("DC: failed to create mcif_wb!\n");
1993         goto create_fail;
1994     }
1995 
1996     /* AUX and I2C */
1997     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1998         pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
1999         if (pool->base.engines[i] == NULL) {
2000             BREAK_TO_DEBUGGER();
2001             dm_error(
2002                 "DC:failed to create aux engine!!\n");
2003             goto create_fail;
2004         }
2005         pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2006         if (pool->base.hw_i2cs[i] == NULL) {
2007             BREAK_TO_DEBUGGER();
2008             dm_error(
2009                 "DC:failed to create hw i2c!!\n");
2010             goto create_fail;
2011         }
2012         pool->base.sw_i2cs[i] = NULL;
2013     }
2014 
2015     /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2016     if (!resource_construct(num_virtual_links, dc, &pool->base,
2017             (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2018             &res_create_funcs : &res_create_maximus_funcs)))
2019             goto create_fail;
2020 
2021     /* HW Sequencer and Plane caps */
2022     dcn31_hw_sequencer_construct(dc);
2023 
2024     dc->caps.max_planes =  pool->base.pipe_count;
2025 
2026     for (i = 0; i < dc->caps.max_planes; ++i)
2027         dc->caps.planes[i] = plane_cap;
2028 
2029     dc->cap_funcs = cap_funcs;
2030 
2031     dc->dcn_ip->max_num_dpp = dcn3_16_ip.max_num_dpp;
2032 
2033     return true;
2034 
2035 create_fail:
2036 
2037     dcn316_resource_destruct(pool);
2038 
2039     return false;
2040 }
2041 
2042 struct resource_pool *dcn316_create_resource_pool(
2043         const struct dc_init_data *init_data,
2044         struct dc *dc)
2045 {
2046     struct dcn316_resource_pool *pool =
2047         kzalloc(sizeof(struct dcn316_resource_pool), GFP_KERNEL);
2048 
2049     if (!pool)
2050         return NULL;
2051 
2052     if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool))
2053         return &pool->base;
2054 
2055     BREAK_TO_DEBUGGER();
2056     kfree(pool);
2057     return NULL;
2058 }
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