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0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 
0027 #include "dm_services.h"
0028 #include "dc.h"
0029 
0030 #include "dcn31/dcn31_init.h"
0031 
0032 #include "resource.h"
0033 #include "include/irq_service_interface.h"
0034 #include "dcn315_resource.h"
0035 
0036 #include "dcn20/dcn20_resource.h"
0037 #include "dcn30/dcn30_resource.h"
0038 #include "dcn31/dcn31_resource.h"
0039 
0040 #include "dcn10/dcn10_ipp.h"
0041 #include "dcn30/dcn30_hubbub.h"
0042 #include "dcn31/dcn31_hubbub.h"
0043 #include "dcn30/dcn30_mpc.h"
0044 #include "dcn31/dcn31_hubp.h"
0045 #include "irq/dcn315/irq_service_dcn315.h"
0046 #include "dcn30/dcn30_dpp.h"
0047 #include "dcn31/dcn31_optc.h"
0048 #include "dcn20/dcn20_hwseq.h"
0049 #include "dcn30/dcn30_hwseq.h"
0050 #include "dce110/dce110_hw_sequencer.h"
0051 #include "dcn30/dcn30_opp.h"
0052 #include "dcn20/dcn20_dsc.h"
0053 #include "dcn30/dcn30_vpg.h"
0054 #include "dcn30/dcn30_afmt.h"
0055 #include "dcn30/dcn30_dio_stream_encoder.h"
0056 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
0057 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
0058 #include "dcn31/dcn31_apg.h"
0059 #include "dcn31/dcn31_dio_link_encoder.h"
0060 #include "dcn31/dcn31_vpg.h"
0061 #include "dcn31/dcn31_afmt.h"
0062 #include "dce/dce_clock_source.h"
0063 #include "dce/dce_audio.h"
0064 #include "dce/dce_hwseq.h"
0065 #include "clk_mgr.h"
0066 #include "virtual/virtual_stream_encoder.h"
0067 #include "dce110/dce110_resource.h"
0068 #include "dml/display_mode_vba.h"
0069 #include "dml/dcn31/dcn31_fpu.h"
0070 #include "dcn31/dcn31_dccg.h"
0071 #include "dcn10/dcn10_resource.h"
0072 #include "dcn31/dcn31_panel_cntl.h"
0073 
0074 #include "dcn30/dcn30_dwb.h"
0075 #include "dcn30/dcn30_mmhubbub.h"
0076 
0077 #include "dcn/dcn_3_1_5_offset.h"
0078 #include "dcn/dcn_3_1_5_sh_mask.h"
0079 #include "dpcs/dpcs_4_2_2_offset.h"
0080 #include "dpcs/dpcs_4_2_2_sh_mask.h"
0081 
0082 #define NBIO_BASE__INST0_SEG0                      0x00000000
0083 #define NBIO_BASE__INST0_SEG1                      0x00000014
0084 #define NBIO_BASE__INST0_SEG2                      0x00000D20
0085 #define NBIO_BASE__INST0_SEG3                      0x00010400
0086 #define NBIO_BASE__INST0_SEG4                      0x0241B000
0087 #define NBIO_BASE__INST0_SEG5                      0x04040000
0088 
0089 #define DPCS_BASE__INST0_SEG0                      0x00000012
0090 #define DPCS_BASE__INST0_SEG1                      0x000000C0
0091 #define DPCS_BASE__INST0_SEG2                      0x000034C0
0092 #define DPCS_BASE__INST0_SEG3                      0x00009000
0093 #define DPCS_BASE__INST0_SEG4                      0x02403C00
0094 #define DPCS_BASE__INST0_SEG5                      0
0095 
0096 #define DCN_BASE__INST0_SEG0                       0x00000012
0097 #define DCN_BASE__INST0_SEG1                       0x000000C0
0098 #define DCN_BASE__INST0_SEG2                       0x000034C0
0099 #define DCN_BASE__INST0_SEG3                       0x00009000
0100 #define DCN_BASE__INST0_SEG4                       0x02403C00
0101 #define DCN_BASE__INST0_SEG5                       0
0102 
0103 #define regBIF_BX_PF2_RSMU_INDEX                                                                        0x0000
0104 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX                                                               1
0105 #define regBIF_BX_PF2_RSMU_DATA                                                                         0x0001
0106 #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX                                                                1
0107 #define regBIF_BX2_BIOS_SCRATCH_6                                                                       0x003e
0108 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX                                                              1
0109 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                         0x0
0110 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                           0xFFFFFFFFL
0111 #define regBIF_BX2_BIOS_SCRATCH_2                                                                       0x003a
0112 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX                                                              1
0113 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                         0x0
0114 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                           0xFFFFFFFFL
0115 #define regBIF_BX2_BIOS_SCRATCH_3                                                                       0x003b
0116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX                                                              1
0117 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                         0x0
0118 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                           0xFFFFFFFFL
0119 
0120 #define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
0121 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
0122 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
0123 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
0124 
0125 #include "reg_helper.h"
0126 #include "dce/dmub_abm.h"
0127 #include "dce/dmub_psr.h"
0128 #include "dce/dce_aux.h"
0129 #include "dce/dce_i2c.h"
0130 
0131 #include "dml/dcn30/display_mode_vba_30.h"
0132 #include "vm_helper.h"
0133 #include "dcn20/dcn20_vmid.h"
0134 
0135 #include "link_enc_cfg.h"
0136 
0137 #define DCN3_15_MAX_DET_SIZE 384
0138 #define DCN3_15_CRB_SEGMENT_SIZE_KB 64
0139 
0140 enum dcn31_clk_src_array_id {
0141     DCN31_CLK_SRC_PLL0,
0142     DCN31_CLK_SRC_PLL1,
0143     DCN31_CLK_SRC_PLL2,
0144     DCN31_CLK_SRC_PLL3,
0145     DCN31_CLK_SRC_PLL4,
0146     DCN30_CLK_SRC_TOTAL
0147 };
0148 
0149 /* begin *********************
0150  * macros to expend register list macro defined in HW object header file
0151  */
0152 
0153 /* DCN */
0154 /* TODO awful hack. fixup dcn20_dwb.h */
0155 #undef BASE_INNER
0156 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0157 
0158 #define BASE(seg) BASE_INNER(seg)
0159 
0160 #define SR(reg_name)\
0161         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
0162                     reg ## reg_name
0163 
0164 #define SRI(reg_name, block, id)\
0165     .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0166                     reg ## block ## id ## _ ## reg_name
0167 
0168 #define SRI2(reg_name, block, id)\
0169     .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
0170                     reg ## reg_name
0171 
0172 #define SRIR(var_name, reg_name, block, id)\
0173     .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0174                     reg ## block ## id ## _ ## reg_name
0175 
0176 #define SRII(reg_name, block, id)\
0177     .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0178                     reg ## block ## id ## _ ## reg_name
0179 
0180 #define SRII_MPC_RMU(reg_name, block, id)\
0181     .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0182                     reg ## block ## id ## _ ## reg_name
0183 
0184 #define SRII_DWB(reg_name, temp_name, block, id)\
0185     .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
0186                     reg ## block ## id ## _ ## temp_name
0187 
0188 #define DCCG_SRII(reg_name, block, id)\
0189     .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0190                     reg ## block ## id ## _ ## reg_name
0191 
0192 #define VUPDATE_SRII(reg_name, block, id)\
0193     .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
0194                     reg ## reg_name ## _ ## block ## id
0195 
0196 /* NBIO */
0197 #define NBIO_BASE_INNER(seg) \
0198     NBIO_BASE__INST0_SEG ## seg
0199 
0200 #define NBIO_BASE(seg) \
0201     NBIO_BASE_INNER(seg)
0202 
0203 #define NBIO_SR(reg_name)\
0204         .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
0205                     regBIF_BX2_ ## reg_name
0206 
0207 static const struct bios_registers bios_regs = {
0208         NBIO_SR(BIOS_SCRATCH_3),
0209         NBIO_SR(BIOS_SCRATCH_6)
0210 };
0211 
0212 #define clk_src_regs(index, pllid)\
0213 [index] = {\
0214     CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
0215 }
0216 
0217 static const struct dce110_clk_src_regs clk_src_regs[] = {
0218     clk_src_regs(0, A),
0219     clk_src_regs(1, B),
0220     clk_src_regs(2, C),
0221     clk_src_regs(3, D),
0222     clk_src_regs(4, E)
0223 };
0224 
0225 static const struct dce110_clk_src_shift cs_shift = {
0226         CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
0227 };
0228 
0229 static const struct dce110_clk_src_mask cs_mask = {
0230         CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
0231 };
0232 
0233 #define abm_regs(id)\
0234 [id] = {\
0235         ABM_DCN302_REG_LIST(id)\
0236 }
0237 
0238 static const struct dce_abm_registers abm_regs[] = {
0239         abm_regs(0),
0240         abm_regs(1),
0241         abm_regs(2),
0242         abm_regs(3),
0243 };
0244 
0245 static const struct dce_abm_shift abm_shift = {
0246         ABM_MASK_SH_LIST_DCN30(__SHIFT)
0247 };
0248 
0249 static const struct dce_abm_mask abm_mask = {
0250         ABM_MASK_SH_LIST_DCN30(_MASK)
0251 };
0252 
0253 #define audio_regs(id)\
0254 [id] = {\
0255         AUD_COMMON_REG_LIST(id)\
0256 }
0257 
0258 static const struct dce_audio_registers audio_regs[] = {
0259     audio_regs(0),
0260     audio_regs(1),
0261     audio_regs(2),
0262     audio_regs(3),
0263     audio_regs(4),
0264     audio_regs(5),
0265     audio_regs(6)
0266 };
0267 
0268 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
0269         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
0270         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
0271         AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
0272 
0273 static const struct dce_audio_shift audio_shift = {
0274         DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
0275 };
0276 
0277 static const struct dce_audio_mask audio_mask = {
0278         DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
0279 };
0280 
0281 #define vpg_regs(id)\
0282 [id] = {\
0283     VPG_DCN31_REG_LIST(id)\
0284 }
0285 
0286 static const struct dcn31_vpg_registers vpg_regs[] = {
0287     vpg_regs(0),
0288     vpg_regs(1),
0289     vpg_regs(2),
0290     vpg_regs(3),
0291     vpg_regs(4),
0292     vpg_regs(5),
0293     vpg_regs(6),
0294     vpg_regs(7),
0295     vpg_regs(8),
0296     vpg_regs(9),
0297 };
0298 
0299 static const struct dcn31_vpg_shift vpg_shift = {
0300     DCN31_VPG_MASK_SH_LIST(__SHIFT)
0301 };
0302 
0303 static const struct dcn31_vpg_mask vpg_mask = {
0304     DCN31_VPG_MASK_SH_LIST(_MASK)
0305 };
0306 
0307 #define afmt_regs(id)\
0308 [id] = {\
0309     AFMT_DCN31_REG_LIST(id)\
0310 }
0311 
0312 static const struct dcn31_afmt_registers afmt_regs[] = {
0313     afmt_regs(0),
0314     afmt_regs(1),
0315     afmt_regs(2),
0316     afmt_regs(3),
0317     afmt_regs(4),
0318     afmt_regs(5)
0319 };
0320 
0321 static const struct dcn31_afmt_shift afmt_shift = {
0322     DCN31_AFMT_MASK_SH_LIST(__SHIFT)
0323 };
0324 
0325 static const struct dcn31_afmt_mask afmt_mask = {
0326     DCN31_AFMT_MASK_SH_LIST(_MASK)
0327 };
0328 
0329 #define apg_regs(id)\
0330 [id] = {\
0331     APG_DCN31_REG_LIST(id)\
0332 }
0333 
0334 static const struct dcn31_apg_registers apg_regs[] = {
0335     apg_regs(0),
0336     apg_regs(1),
0337     apg_regs(2),
0338     apg_regs(3)
0339 };
0340 
0341 static const struct dcn31_apg_shift apg_shift = {
0342     DCN31_APG_MASK_SH_LIST(__SHIFT)
0343 };
0344 
0345 static const struct dcn31_apg_mask apg_mask = {
0346         DCN31_APG_MASK_SH_LIST(_MASK)
0347 };
0348 
0349 #define stream_enc_regs(id)\
0350 [id] = {\
0351     SE_DCN3_REG_LIST(id)\
0352 }
0353 
0354 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
0355     stream_enc_regs(0),
0356     stream_enc_regs(1),
0357     stream_enc_regs(2),
0358     stream_enc_regs(3),
0359     stream_enc_regs(4)
0360 };
0361 
0362 static const struct dcn10_stream_encoder_shift se_shift = {
0363         SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0364 };
0365 
0366 static const struct dcn10_stream_encoder_mask se_mask = {
0367         SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
0368 };
0369 
0370 
0371 #define aux_regs(id)\
0372 [id] = {\
0373     DCN2_AUX_REG_LIST(id)\
0374 }
0375 
0376 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
0377         aux_regs(0),
0378         aux_regs(1),
0379         aux_regs(2),
0380         aux_regs(3),
0381         aux_regs(4)
0382 };
0383 
0384 #define hpd_regs(id)\
0385 [id] = {\
0386     HPD_REG_LIST(id)\
0387 }
0388 
0389 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
0390         hpd_regs(0),
0391         hpd_regs(1),
0392         hpd_regs(2),
0393         hpd_regs(3),
0394         hpd_regs(4)
0395 };
0396 
0397 #define link_regs(id, phyid)\
0398 [id] = {\
0399     LE_DCN31_REG_LIST(id), \
0400     UNIPHY_DCN2_REG_LIST(phyid), \
0401     DPCS_DCN31_REG_LIST(id), \
0402 }
0403 
0404 static const struct dce110_aux_registers_shift aux_shift = {
0405     DCN_AUX_MASK_SH_LIST(__SHIFT)
0406 };
0407 
0408 static const struct dce110_aux_registers_mask aux_mask = {
0409     DCN_AUX_MASK_SH_LIST(_MASK)
0410 };
0411 
0412 static const struct dcn10_link_enc_registers link_enc_regs[] = {
0413     link_regs(0, A),
0414     link_regs(1, B),
0415     link_regs(2, C),
0416     link_regs(3, D),
0417     link_regs(4, E)
0418 };
0419 
0420 static const struct dcn10_link_enc_shift le_shift = {
0421     LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
0422     DPCS_DCN31_MASK_SH_LIST(__SHIFT)
0423 };
0424 
0425 static const struct dcn10_link_enc_mask le_mask = {
0426     LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
0427     DPCS_DCN31_MASK_SH_LIST(_MASK)
0428 };
0429 
0430 #define hpo_dp_stream_encoder_reg_list(id)\
0431 [id] = {\
0432     DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
0433 }
0434 
0435 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
0436     hpo_dp_stream_encoder_reg_list(0),
0437     hpo_dp_stream_encoder_reg_list(1),
0438     hpo_dp_stream_encoder_reg_list(2),
0439     hpo_dp_stream_encoder_reg_list(3),
0440 };
0441 
0442 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
0443     DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
0444 };
0445 
0446 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
0447     DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
0448 };
0449 
0450 
0451 #define hpo_dp_link_encoder_reg_list(id)\
0452 [id] = {\
0453     DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
0454     DCN3_1_RDPCSTX_REG_LIST(0),\
0455     DCN3_1_RDPCSTX_REG_LIST(1),\
0456     DCN3_1_RDPCSTX_REG_LIST(2),\
0457     DCN3_1_RDPCSTX_REG_LIST(3),\
0458     DCN3_1_RDPCSTX_REG_LIST(4)\
0459 }
0460 
0461 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
0462     hpo_dp_link_encoder_reg_list(0),
0463     hpo_dp_link_encoder_reg_list(1),
0464 };
0465 
0466 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
0467     DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
0468 };
0469 
0470 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
0471     DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
0472 };
0473 
0474 #define dpp_regs(id)\
0475 [id] = {\
0476     DPP_REG_LIST_DCN30(id),\
0477 }
0478 
0479 static const struct dcn3_dpp_registers dpp_regs[] = {
0480     dpp_regs(0),
0481     dpp_regs(1),
0482     dpp_regs(2),
0483     dpp_regs(3)
0484 };
0485 
0486 static const struct dcn3_dpp_shift tf_shift = {
0487         DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
0488 };
0489 
0490 static const struct dcn3_dpp_mask tf_mask = {
0491         DPP_REG_LIST_SH_MASK_DCN30(_MASK)
0492 };
0493 
0494 #define opp_regs(id)\
0495 [id] = {\
0496     OPP_REG_LIST_DCN30(id),\
0497 }
0498 
0499 static const struct dcn20_opp_registers opp_regs[] = {
0500     opp_regs(0),
0501     opp_regs(1),
0502     opp_regs(2),
0503     opp_regs(3)
0504 };
0505 
0506 static const struct dcn20_opp_shift opp_shift = {
0507     OPP_MASK_SH_LIST_DCN20(__SHIFT)
0508 };
0509 
0510 static const struct dcn20_opp_mask opp_mask = {
0511     OPP_MASK_SH_LIST_DCN20(_MASK)
0512 };
0513 
0514 #define aux_engine_regs(id)\
0515 [id] = {\
0516     AUX_COMMON_REG_LIST0(id), \
0517     .AUXN_IMPCAL = 0, \
0518     .AUXP_IMPCAL = 0, \
0519     .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
0520 }
0521 
0522 static const struct dce110_aux_registers aux_engine_regs[] = {
0523         aux_engine_regs(0),
0524         aux_engine_regs(1),
0525         aux_engine_regs(2),
0526         aux_engine_regs(3),
0527         aux_engine_regs(4)
0528 };
0529 
0530 #define dwbc_regs_dcn3(id)\
0531 [id] = {\
0532     DWBC_COMMON_REG_LIST_DCN30(id),\
0533 }
0534 
0535 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
0536     dwbc_regs_dcn3(0),
0537 };
0538 
0539 static const struct dcn30_dwbc_shift dwbc30_shift = {
0540     DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0541 };
0542 
0543 static const struct dcn30_dwbc_mask dwbc30_mask = {
0544     DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
0545 };
0546 
0547 #define mcif_wb_regs_dcn3(id)\
0548 [id] = {\
0549     MCIF_WB_COMMON_REG_LIST_DCN30(id),\
0550 }
0551 
0552 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
0553     mcif_wb_regs_dcn3(0)
0554 };
0555 
0556 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
0557     MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0558 };
0559 
0560 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
0561     MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
0562 };
0563 
0564 #define dsc_regsDCN20(id)\
0565 [id] = {\
0566     DSC_REG_LIST_DCN20(id)\
0567 }
0568 
0569 static const struct dcn20_dsc_registers dsc_regs[] = {
0570     dsc_regsDCN20(0),
0571     dsc_regsDCN20(1),
0572     dsc_regsDCN20(2)
0573 };
0574 
0575 static const struct dcn20_dsc_shift dsc_shift = {
0576     DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
0577 };
0578 
0579 static const struct dcn20_dsc_mask dsc_mask = {
0580     DSC_REG_LIST_SH_MASK_DCN20(_MASK)
0581 };
0582 
0583 static const struct dcn30_mpc_registers mpc_regs = {
0584         MPC_REG_LIST_DCN3_0(0),
0585         MPC_REG_LIST_DCN3_0(1),
0586         MPC_REG_LIST_DCN3_0(2),
0587         MPC_REG_LIST_DCN3_0(3),
0588         MPC_OUT_MUX_REG_LIST_DCN3_0(0),
0589         MPC_OUT_MUX_REG_LIST_DCN3_0(1),
0590         MPC_OUT_MUX_REG_LIST_DCN3_0(2),
0591         MPC_OUT_MUX_REG_LIST_DCN3_0(3),
0592         MPC_DWB_MUX_REG_LIST_DCN3_0(0),
0593 };
0594 
0595 static const struct dcn30_mpc_shift mpc_shift = {
0596     MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0597 };
0598 
0599 static const struct dcn30_mpc_mask mpc_mask = {
0600     MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
0601 };
0602 
0603 #define optc_regs(id)\
0604 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
0605 
0606 static const struct dcn_optc_registers optc_regs[] = {
0607     optc_regs(0),
0608     optc_regs(1),
0609     optc_regs(2),
0610     optc_regs(3)
0611 };
0612 
0613 static const struct dcn_optc_shift optc_shift = {
0614     OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
0615 };
0616 
0617 static const struct dcn_optc_mask optc_mask = {
0618     OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
0619 };
0620 
0621 #define hubp_regs(id)\
0622 [id] = {\
0623     HUBP_REG_LIST_DCN30(id)\
0624 }
0625 
0626 static const struct dcn_hubp2_registers hubp_regs[] = {
0627         hubp_regs(0),
0628         hubp_regs(1),
0629         hubp_regs(2),
0630         hubp_regs(3)
0631 };
0632 
0633 
0634 static const struct dcn_hubp2_shift hubp_shift = {
0635         HUBP_MASK_SH_LIST_DCN31(__SHIFT)
0636 };
0637 
0638 static const struct dcn_hubp2_mask hubp_mask = {
0639         HUBP_MASK_SH_LIST_DCN31(_MASK)
0640 };
0641 static const struct dcn_hubbub_registers hubbub_reg = {
0642         HUBBUB_REG_LIST_DCN31(0)
0643 };
0644 
0645 static const struct dcn_hubbub_shift hubbub_shift = {
0646         HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
0647 };
0648 
0649 static const struct dcn_hubbub_mask hubbub_mask = {
0650         HUBBUB_MASK_SH_LIST_DCN31(_MASK)
0651 };
0652 
0653 static const struct dccg_registers dccg_regs = {
0654         DCCG_REG_LIST_DCN31()
0655 };
0656 
0657 static const struct dccg_shift dccg_shift = {
0658         DCCG_MASK_SH_LIST_DCN31(__SHIFT)
0659 };
0660 
0661 static const struct dccg_mask dccg_mask = {
0662         DCCG_MASK_SH_LIST_DCN31(_MASK)
0663 };
0664 
0665 
0666 #define SRII2(reg_name_pre, reg_name_post, id)\
0667     .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
0668             ## id ## _ ## reg_name_post ## _BASE_IDX) + \
0669             reg ## reg_name_pre ## id ## _ ## reg_name_post
0670 
0671 
0672 #define HWSEQ_DCN31_REG_LIST()\
0673     SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
0674     SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
0675     SR(DIO_MEM_PWR_CTRL), \
0676     SR(ODM_MEM_PWR_CTRL3), \
0677     SR(DMU_MEM_PWR_CNTL), \
0678     SR(MMHUBBUB_MEM_PWR_CNTL), \
0679     SR(DCCG_GATE_DISABLE_CNTL), \
0680     SR(DCCG_GATE_DISABLE_CNTL2), \
0681     SR(DCFCLK_CNTL),\
0682     SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
0683     SRII(PIXEL_RATE_CNTL, OTG, 0), \
0684     SRII(PIXEL_RATE_CNTL, OTG, 1),\
0685     SRII(PIXEL_RATE_CNTL, OTG, 2),\
0686     SRII(PIXEL_RATE_CNTL, OTG, 3),\
0687     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
0688     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
0689     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
0690     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
0691     SR(MICROSECOND_TIME_BASE_DIV), \
0692     SR(MILLISECOND_TIME_BASE_DIV), \
0693     SR(DISPCLK_FREQ_CHANGE_CNTL), \
0694     SR(RBBMIF_TIMEOUT_DIS), \
0695     SR(RBBMIF_TIMEOUT_DIS_2), \
0696     SR(DCHUBBUB_CRC_CTRL), \
0697     SR(DPP_TOP0_DPP_CRC_CTRL), \
0698     SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
0699     SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
0700     SR(MPC_CRC_CTRL), \
0701     SR(MPC_CRC_RESULT_GB), \
0702     SR(MPC_CRC_RESULT_C), \
0703     SR(MPC_CRC_RESULT_AR), \
0704     SR(DOMAIN0_PG_CONFIG), \
0705     SR(DOMAIN1_PG_CONFIG), \
0706     SR(DOMAIN2_PG_CONFIG), \
0707     SR(DOMAIN3_PG_CONFIG), \
0708     SR(DOMAIN16_PG_CONFIG), \
0709     SR(DOMAIN17_PG_CONFIG), \
0710     SR(DOMAIN18_PG_CONFIG), \
0711     SR(DOMAIN0_PG_STATUS), \
0712     SR(DOMAIN1_PG_STATUS), \
0713     SR(DOMAIN2_PG_STATUS), \
0714     SR(DOMAIN3_PG_STATUS), \
0715     SR(DOMAIN16_PG_STATUS), \
0716     SR(DOMAIN17_PG_STATUS), \
0717     SR(DOMAIN18_PG_STATUS), \
0718     SR(D1VGA_CONTROL), \
0719     SR(D2VGA_CONTROL), \
0720     SR(D3VGA_CONTROL), \
0721     SR(D4VGA_CONTROL), \
0722     SR(D5VGA_CONTROL), \
0723     SR(D6VGA_CONTROL), \
0724     SR(DC_IP_REQUEST_CNTL), \
0725     SR(AZALIA_AUDIO_DTO), \
0726     SR(AZALIA_CONTROLLER_CLOCK_GATING), \
0727     SR(HPO_TOP_HW_CONTROL)
0728 
0729 static const struct dce_hwseq_registers hwseq_reg = {
0730         HWSEQ_DCN31_REG_LIST()
0731 };
0732 
0733 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
0734     HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
0735     HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
0736     HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
0737     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0738     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0739     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0740     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0741     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0742     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0743     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0744     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0745     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0746     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0747     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0748     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0749     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0750     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0751     HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0752     HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0753     HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0754     HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0755     HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0756     HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0757     HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0758     HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
0759     HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
0760     HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
0761     HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
0762     HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
0763     HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
0764     HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
0765     HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
0766     HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
0767 
0768 static const struct dce_hwseq_shift hwseq_shift = {
0769         HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
0770 };
0771 
0772 static const struct dce_hwseq_mask hwseq_mask = {
0773         HWSEQ_DCN31_MASK_SH_LIST(_MASK)
0774 };
0775 #define vmid_regs(id)\
0776 [id] = {\
0777         DCN20_VMID_REG_LIST(id)\
0778 }
0779 
0780 static const struct dcn_vmid_registers vmid_regs[] = {
0781     vmid_regs(0),
0782     vmid_regs(1),
0783     vmid_regs(2),
0784     vmid_regs(3),
0785     vmid_regs(4),
0786     vmid_regs(5),
0787     vmid_regs(6),
0788     vmid_regs(7),
0789     vmid_regs(8),
0790     vmid_regs(9),
0791     vmid_regs(10),
0792     vmid_regs(11),
0793     vmid_regs(12),
0794     vmid_regs(13),
0795     vmid_regs(14),
0796     vmid_regs(15)
0797 };
0798 
0799 static const struct dcn20_vmid_shift vmid_shifts = {
0800         DCN20_VMID_MASK_SH_LIST(__SHIFT)
0801 };
0802 
0803 static const struct dcn20_vmid_mask vmid_masks = {
0804         DCN20_VMID_MASK_SH_LIST(_MASK)
0805 };
0806 
0807 static const struct resource_caps res_cap_dcn31 = {
0808     .num_timing_generator = 4,
0809     .num_opp = 4,
0810     .num_video_plane = 4,
0811     .num_audio = 5,
0812     .num_stream_encoder = 5,
0813     .num_dig_link_enc = 5,
0814     .num_hpo_dp_stream_encoder = 4,
0815     .num_hpo_dp_link_encoder = 2,
0816     .num_pll = 5,
0817     .num_dwb = 1,
0818     .num_ddc = 5,
0819     .num_vmid = 16,
0820     .num_mpc_3dlut = 2,
0821     .num_dsc = 3,
0822 };
0823 
0824 static const struct dc_plane_cap plane_cap = {
0825     .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
0826     .blends_with_above = true,
0827     .blends_with_below = true,
0828     .per_pixel_alpha = true,
0829 
0830     .pixel_format_support = {
0831             .argb8888 = true,
0832             .nv12 = true,
0833             .fp16 = true,
0834             .p010 = true,
0835             .ayuv = false,
0836     },
0837 
0838     .max_upscale_factor = {
0839             .argb8888 = 16000,
0840             .nv12 = 16000,
0841             .fp16 = 16000
0842     },
0843 
0844     // 6:1 downscaling ratio: 1000/6 = 166.666
0845     .max_downscale_factor = {
0846             .argb8888 = 167,
0847             .nv12 = 167,
0848             .fp16 = 167
0849     },
0850     64,
0851     64
0852 };
0853 
0854 static const struct dc_debug_options debug_defaults_drv = {
0855     .disable_z10 = true, /*hw not support it*/
0856     .disable_dmcu = true,
0857     .force_abm_enable = false,
0858     .timing_trace = false,
0859     .clock_trace = true,
0860     .disable_pplib_clock_request = false,
0861     .pipe_split_policy = MPC_SPLIT_DYNAMIC,
0862     .force_single_disp_pipe_split = false,
0863     .disable_dcc = DCC_ENABLE,
0864     .vsr_support = true,
0865     .performance_trace = false,
0866     .max_downscale_src_width = 4096,/*upto true 4k*/
0867     .disable_pplib_wm_range = false,
0868     .scl_reset_length10 = true,
0869     .sanity_checks = false,
0870     .underflow_assert_delay_us = 0xFFFFFFFF,
0871     .dwb_fi_phase = -1, // -1 = disable,
0872     .dmub_command_table = true,
0873     .pstate_enabled = true,
0874     .use_max_lb = true,
0875     .enable_mem_low_power = {
0876         .bits = {
0877             .vga = true,
0878             .i2c = true,
0879             .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
0880             .dscl = true,
0881             .cm = true,
0882             .mpc = true,
0883             .optc = true,
0884             .vpg = true,
0885             .afmt = true,
0886         }
0887     },
0888     .optimize_edp_link_rate = true,
0889     .enable_sw_cntl_psr = true,
0890     .psr_power_use_phy_fsm = 0,
0891 };
0892 
0893 static const struct dc_debug_options debug_defaults_diags = {
0894     .disable_dmcu = true,
0895     .force_abm_enable = false,
0896     .timing_trace = true,
0897     .clock_trace = true,
0898     .disable_dpp_power_gate = true,
0899     .disable_hubp_power_gate = true,
0900     .disable_clock_gate = true,
0901     .disable_pplib_clock_request = true,
0902     .disable_pplib_wm_range = true,
0903     .disable_stutter = false,
0904     .scl_reset_length10 = true,
0905     .dwb_fi_phase = -1, // -1 = disable
0906     .dmub_command_table = true,
0907     .enable_tri_buf = true,
0908     .use_max_lb = true
0909 };
0910 
0911 static void dcn31_dpp_destroy(struct dpp **dpp)
0912 {
0913     kfree(TO_DCN20_DPP(*dpp));
0914     *dpp = NULL;
0915 }
0916 
0917 static struct dpp *dcn31_dpp_create(
0918     struct dc_context *ctx,
0919     uint32_t inst)
0920 {
0921     struct dcn3_dpp *dpp =
0922         kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
0923 
0924     if (!dpp)
0925         return NULL;
0926 
0927     if (dpp3_construct(dpp, ctx, inst,
0928             &dpp_regs[inst], &tf_shift, &tf_mask))
0929         return &dpp->base;
0930 
0931     BREAK_TO_DEBUGGER();
0932     kfree(dpp);
0933     return NULL;
0934 }
0935 
0936 static struct output_pixel_processor *dcn31_opp_create(
0937     struct dc_context *ctx, uint32_t inst)
0938 {
0939     struct dcn20_opp *opp =
0940         kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
0941 
0942     if (!opp) {
0943         BREAK_TO_DEBUGGER();
0944         return NULL;
0945     }
0946 
0947     dcn20_opp_construct(opp, ctx, inst,
0948             &opp_regs[inst], &opp_shift, &opp_mask);
0949     return &opp->base;
0950 }
0951 
0952 static struct dce_aux *dcn31_aux_engine_create(
0953     struct dc_context *ctx,
0954     uint32_t inst)
0955 {
0956     struct aux_engine_dce110 *aux_engine =
0957         kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
0958 
0959     if (!aux_engine)
0960         return NULL;
0961 
0962     dce110_aux_engine_construct(aux_engine, ctx, inst,
0963                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
0964                     &aux_engine_regs[inst],
0965                     &aux_mask,
0966                     &aux_shift,
0967                     ctx->dc->caps.extended_aux_timeout_support);
0968 
0969     return &aux_engine->base;
0970 }
0971 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
0972 
0973 static const struct dce_i2c_registers i2c_hw_regs[] = {
0974         i2c_inst_regs(1),
0975         i2c_inst_regs(2),
0976         i2c_inst_regs(3),
0977         i2c_inst_regs(4),
0978         i2c_inst_regs(5),
0979 };
0980 
0981 static const struct dce_i2c_shift i2c_shifts = {
0982         I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0983 };
0984 
0985 static const struct dce_i2c_mask i2c_masks = {
0986         I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
0987 };
0988 
0989 static struct dce_i2c_hw *dcn31_i2c_hw_create(
0990     struct dc_context *ctx,
0991     uint32_t inst)
0992 {
0993     struct dce_i2c_hw *dce_i2c_hw =
0994         kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
0995 
0996     if (!dce_i2c_hw)
0997         return NULL;
0998 
0999     dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1000                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1001 
1002     return dce_i2c_hw;
1003 }
1004 static struct mpc *dcn31_mpc_create(
1005         struct dc_context *ctx,
1006         int num_mpcc,
1007         int num_rmu)
1008 {
1009     struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1010                       GFP_KERNEL);
1011 
1012     if (!mpc30)
1013         return NULL;
1014 
1015     dcn30_mpc_construct(mpc30, ctx,
1016             &mpc_regs,
1017             &mpc_shift,
1018             &mpc_mask,
1019             num_mpcc,
1020             num_rmu);
1021 
1022     return &mpc30->base;
1023 }
1024 
1025 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1026 {
1027     int i;
1028 
1029     struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1030                       GFP_KERNEL);
1031 
1032     if (!hubbub3)
1033         return NULL;
1034 
1035     hubbub31_construct(hubbub3, ctx,
1036             &hubbub_reg,
1037             &hubbub_shift,
1038             &hubbub_mask,
1039             dcn3_15_ip.det_buffer_size_kbytes,
1040             dcn3_15_ip.pixel_chunk_size_kbytes,
1041             dcn3_15_ip.config_return_buffer_size_in_kbytes);
1042 
1043 
1044     for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1045         struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1046 
1047         vmid->ctx = ctx;
1048 
1049         vmid->regs = &vmid_regs[i];
1050         vmid->shifts = &vmid_shifts;
1051         vmid->masks = &vmid_masks;
1052     }
1053 
1054     return &hubbub3->base;
1055 }
1056 
1057 static struct timing_generator *dcn31_timing_generator_create(
1058         struct dc_context *ctx,
1059         uint32_t instance)
1060 {
1061     struct optc *tgn10 =
1062         kzalloc(sizeof(struct optc), GFP_KERNEL);
1063 
1064     if (!tgn10)
1065         return NULL;
1066 
1067     tgn10->base.inst = instance;
1068     tgn10->base.ctx = ctx;
1069 
1070     tgn10->tg_regs = &optc_regs[instance];
1071     tgn10->tg_shift = &optc_shift;
1072     tgn10->tg_mask = &optc_mask;
1073 
1074     dcn31_timing_generator_init(tgn10);
1075 
1076     return &tgn10->base;
1077 }
1078 
1079 static const struct encoder_feature_support link_enc_feature = {
1080         .max_hdmi_deep_color = COLOR_DEPTH_121212,
1081         .max_hdmi_pixel_clock = 600000,
1082         .hdmi_ycbcr420_supported = true,
1083         .dp_ycbcr420_supported = true,
1084         .fec_supported = true,
1085         .flags.bits.IS_HBR2_CAPABLE = true,
1086         .flags.bits.IS_HBR3_CAPABLE = true,
1087         .flags.bits.IS_TPS3_CAPABLE = true,
1088         .flags.bits.IS_TPS4_CAPABLE = true
1089 };
1090 
1091 static struct link_encoder *dcn31_link_encoder_create(
1092     struct dc_context *ctx,
1093     const struct encoder_init_data *enc_init_data)
1094 {
1095     struct dcn20_link_encoder *enc20 =
1096         kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1097 
1098     if (!enc20)
1099         return NULL;
1100 
1101     dcn31_link_encoder_construct(enc20,
1102             enc_init_data,
1103             &link_enc_feature,
1104             &link_enc_regs[enc_init_data->transmitter],
1105             &link_enc_aux_regs[enc_init_data->channel - 1],
1106             &link_enc_hpd_regs[enc_init_data->hpd_source],
1107             &le_shift,
1108             &le_mask);
1109 
1110     return &enc20->enc10.base;
1111 }
1112 
1113 /* Create a minimal link encoder object not associated with a particular
1114  * physical connector.
1115  * resource_funcs.link_enc_create_minimal
1116  */
1117 static struct link_encoder *dcn31_link_enc_create_minimal(
1118         struct dc_context *ctx, enum engine_id eng_id)
1119 {
1120     struct dcn20_link_encoder *enc20;
1121 
1122     if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1123         return NULL;
1124 
1125     enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1126     if (!enc20)
1127         return NULL;
1128 
1129     dcn31_link_encoder_construct_minimal(
1130             enc20,
1131             ctx,
1132             &link_enc_feature,
1133             &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1134             eng_id);
1135 
1136     return &enc20->enc10.base;
1137 }
1138 
1139 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1140 {
1141     struct dcn31_panel_cntl *panel_cntl =
1142         kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1143 
1144     if (!panel_cntl)
1145         return NULL;
1146 
1147     dcn31_panel_cntl_construct(panel_cntl, init_data);
1148 
1149     return &panel_cntl->base;
1150 }
1151 
1152 static void read_dce_straps(
1153     struct dc_context *ctx,
1154     struct resource_straps *straps)
1155 {
1156     generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1157         FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1158 
1159 }
1160 
1161 static struct audio *dcn31_create_audio(
1162         struct dc_context *ctx, unsigned int inst)
1163 {
1164     return dce_audio_create(ctx, inst,
1165             &audio_regs[inst], &audio_shift, &audio_mask);
1166 }
1167 
1168 static struct vpg *dcn31_vpg_create(
1169     struct dc_context *ctx,
1170     uint32_t inst)
1171 {
1172     struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1173 
1174     if (!vpg31)
1175         return NULL;
1176 
1177     vpg31_construct(vpg31, ctx, inst,
1178             &vpg_regs[inst],
1179             &vpg_shift,
1180             &vpg_mask);
1181 
1182     return &vpg31->base;
1183 }
1184 
1185 static struct afmt *dcn31_afmt_create(
1186     struct dc_context *ctx,
1187     uint32_t inst)
1188 {
1189     struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1190 
1191     if (!afmt31)
1192         return NULL;
1193 
1194     afmt31_construct(afmt31, ctx, inst,
1195             &afmt_regs[inst],
1196             &afmt_shift,
1197             &afmt_mask);
1198 
1199     // Light sleep by default, no need to power down here
1200 
1201     return &afmt31->base;
1202 }
1203 
1204 static struct apg *dcn31_apg_create(
1205     struct dc_context *ctx,
1206     uint32_t inst)
1207 {
1208     struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1209 
1210     if (!apg31)
1211         return NULL;
1212 
1213     apg31_construct(apg31, ctx, inst,
1214             &apg_regs[inst],
1215             &apg_shift,
1216             &apg_mask);
1217 
1218     return &apg31->base;
1219 }
1220 
1221 static struct stream_encoder *dcn315_stream_encoder_create(
1222     enum engine_id eng_id,
1223     struct dc_context *ctx)
1224 {
1225     struct dcn10_stream_encoder *enc1;
1226     struct vpg *vpg;
1227     struct afmt *afmt;
1228     int vpg_inst;
1229     int afmt_inst;
1230 
1231     /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/
1232 
1233     /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1234     if (eng_id <= ENGINE_ID_DIGF) {
1235         vpg_inst = eng_id;
1236         afmt_inst = eng_id;
1237     } else
1238         return NULL;
1239 
1240     enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1241     vpg = dcn31_vpg_create(ctx, vpg_inst);
1242     afmt = dcn31_afmt_create(ctx, afmt_inst);
1243 
1244     if (!enc1 || !vpg || !afmt) {
1245         kfree(enc1);
1246         kfree(vpg);
1247         kfree(afmt);
1248         return NULL;
1249     }
1250 
1251     dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1252                     eng_id, vpg, afmt,
1253                     &stream_enc_regs[eng_id],
1254                     &se_shift, &se_mask);
1255 
1256     return &enc1->base;
1257 }
1258 
1259 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1260     enum engine_id eng_id,
1261     struct dc_context *ctx)
1262 {
1263     struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1264     struct vpg *vpg;
1265     struct apg *apg;
1266     uint32_t hpo_dp_inst;
1267     uint32_t vpg_inst;
1268     uint32_t apg_inst;
1269 
1270     ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1271     hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1272 
1273     /* Mapping of VPG register blocks to HPO DP block instance:
1274      * VPG[6] -> HPO_DP[0]
1275      * VPG[7] -> HPO_DP[1]
1276      * VPG[8] -> HPO_DP[2]
1277      * VPG[9] -> HPO_DP[3]
1278      */
1279     vpg_inst = hpo_dp_inst + 6;
1280 
1281     /* Mapping of APG register blocks to HPO DP block instance:
1282      * APG[0] -> HPO_DP[0]
1283      * APG[1] -> HPO_DP[1]
1284      * APG[2] -> HPO_DP[2]
1285      * APG[3] -> HPO_DP[3]
1286      */
1287     apg_inst = hpo_dp_inst;
1288 
1289     /* allocate HPO stream encoder and create VPG sub-block */
1290     hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1291     vpg = dcn31_vpg_create(ctx, vpg_inst);
1292     apg = dcn31_apg_create(ctx, apg_inst);
1293 
1294     if (!hpo_dp_enc31 || !vpg || !apg) {
1295         kfree(hpo_dp_enc31);
1296         kfree(vpg);
1297         kfree(apg);
1298         return NULL;
1299     }
1300 
1301     dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1302                     hpo_dp_inst, eng_id, vpg, apg,
1303                     &hpo_dp_stream_enc_regs[hpo_dp_inst],
1304                     &hpo_dp_se_shift, &hpo_dp_se_mask);
1305 
1306     return &hpo_dp_enc31->base;
1307 }
1308 
1309 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1310     uint8_t inst,
1311     struct dc_context *ctx)
1312 {
1313     struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1314 
1315     /* allocate HPO link encoder */
1316     hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1317 
1318     hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1319                     &hpo_dp_link_enc_regs[inst],
1320                     &hpo_dp_le_shift, &hpo_dp_le_mask);
1321 
1322     return &hpo_dp_enc31->base;
1323 }
1324 
1325 static struct dce_hwseq *dcn31_hwseq_create(
1326     struct dc_context *ctx)
1327 {
1328     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1329 
1330     if (hws) {
1331         hws->ctx = ctx;
1332         hws->regs = &hwseq_reg;
1333         hws->shifts = &hwseq_shift;
1334         hws->masks = &hwseq_mask;
1335         /* DCN3.1 FPGA Workaround
1336          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1337          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1338          * function core_link_enable_stream
1339          */
1340         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1341             hws->wa.dp_hpo_and_otg_sequence = true;
1342     }
1343     return hws;
1344 }
1345 static const struct resource_create_funcs res_create_funcs = {
1346     .read_dce_straps = read_dce_straps,
1347     .create_audio = dcn31_create_audio,
1348     .create_stream_encoder = dcn315_stream_encoder_create,
1349     .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1350     .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1351     .create_hwseq = dcn31_hwseq_create,
1352 };
1353 
1354 static const struct resource_create_funcs res_create_maximus_funcs = {
1355     .read_dce_straps = NULL,
1356     .create_audio = NULL,
1357     .create_stream_encoder = NULL,
1358     .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1359     .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1360     .create_hwseq = dcn31_hwseq_create,
1361 };
1362 
1363 static void dcn315_resource_destruct(struct dcn315_resource_pool *pool)
1364 {
1365     unsigned int i;
1366 
1367     for (i = 0; i < pool->base.stream_enc_count; i++) {
1368         if (pool->base.stream_enc[i] != NULL) {
1369             if (pool->base.stream_enc[i]->vpg != NULL) {
1370                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1371                 pool->base.stream_enc[i]->vpg = NULL;
1372             }
1373             if (pool->base.stream_enc[i]->afmt != NULL) {
1374                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1375                 pool->base.stream_enc[i]->afmt = NULL;
1376             }
1377             kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1378             pool->base.stream_enc[i] = NULL;
1379         }
1380     }
1381 
1382     for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1383         if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1384             if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1385                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1386                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1387             }
1388             if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1389                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1390                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1391             }
1392             kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1393             pool->base.hpo_dp_stream_enc[i] = NULL;
1394         }
1395     }
1396 
1397     for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1398         if (pool->base.hpo_dp_link_enc[i] != NULL) {
1399             kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1400             pool->base.hpo_dp_link_enc[i] = NULL;
1401         }
1402     }
1403 
1404     for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1405         if (pool->base.dscs[i] != NULL)
1406             dcn20_dsc_destroy(&pool->base.dscs[i]);
1407     }
1408 
1409     if (pool->base.mpc != NULL) {
1410         kfree(TO_DCN20_MPC(pool->base.mpc));
1411         pool->base.mpc = NULL;
1412     }
1413     if (pool->base.hubbub != NULL) {
1414         kfree(pool->base.hubbub);
1415         pool->base.hubbub = NULL;
1416     }
1417     for (i = 0; i < pool->base.pipe_count; i++) {
1418         if (pool->base.dpps[i] != NULL)
1419             dcn31_dpp_destroy(&pool->base.dpps[i]);
1420 
1421         if (pool->base.ipps[i] != NULL)
1422             pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1423 
1424         if (pool->base.hubps[i] != NULL) {
1425             kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1426             pool->base.hubps[i] = NULL;
1427         }
1428 
1429         if (pool->base.irqs != NULL) {
1430             dal_irq_service_destroy(&pool->base.irqs);
1431         }
1432     }
1433 
1434     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1435         if (pool->base.engines[i] != NULL)
1436             dce110_engine_destroy(&pool->base.engines[i]);
1437         if (pool->base.hw_i2cs[i] != NULL) {
1438             kfree(pool->base.hw_i2cs[i]);
1439             pool->base.hw_i2cs[i] = NULL;
1440         }
1441         if (pool->base.sw_i2cs[i] != NULL) {
1442             kfree(pool->base.sw_i2cs[i]);
1443             pool->base.sw_i2cs[i] = NULL;
1444         }
1445     }
1446 
1447     for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1448         if (pool->base.opps[i] != NULL)
1449             pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1450     }
1451 
1452     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1453         if (pool->base.timing_generators[i] != NULL)    {
1454             kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1455             pool->base.timing_generators[i] = NULL;
1456         }
1457     }
1458 
1459     for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1460         if (pool->base.dwbc[i] != NULL) {
1461             kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1462             pool->base.dwbc[i] = NULL;
1463         }
1464         if (pool->base.mcif_wb[i] != NULL) {
1465             kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1466             pool->base.mcif_wb[i] = NULL;
1467         }
1468     }
1469 
1470     for (i = 0; i < pool->base.audio_count; i++) {
1471         if (pool->base.audios[i])
1472             dce_aud_destroy(&pool->base.audios[i]);
1473     }
1474 
1475     for (i = 0; i < pool->base.clk_src_count; i++) {
1476         if (pool->base.clock_sources[i] != NULL) {
1477             dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1478             pool->base.clock_sources[i] = NULL;
1479         }
1480     }
1481 
1482     for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1483         if (pool->base.mpc_lut[i] != NULL) {
1484             dc_3dlut_func_release(pool->base.mpc_lut[i]);
1485             pool->base.mpc_lut[i] = NULL;
1486         }
1487         if (pool->base.mpc_shaper[i] != NULL) {
1488             dc_transfer_func_release(pool->base.mpc_shaper[i]);
1489             pool->base.mpc_shaper[i] = NULL;
1490         }
1491     }
1492 
1493     if (pool->base.dp_clock_source != NULL) {
1494         dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1495         pool->base.dp_clock_source = NULL;
1496     }
1497 
1498     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1499         if (pool->base.multiple_abms[i] != NULL)
1500             dce_abm_destroy(&pool->base.multiple_abms[i]);
1501     }
1502 
1503     if (pool->base.psr != NULL)
1504         dmub_psr_destroy(&pool->base.psr);
1505 
1506     if (pool->base.dccg != NULL)
1507         dcn_dccg_destroy(&pool->base.dccg);
1508 }
1509 
1510 static struct hubp *dcn31_hubp_create(
1511     struct dc_context *ctx,
1512     uint32_t inst)
1513 {
1514     struct dcn20_hubp *hubp2 =
1515         kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1516 
1517     if (!hubp2)
1518         return NULL;
1519 
1520     if (hubp31_construct(hubp2, ctx, inst,
1521             &hubp_regs[inst], &hubp_shift, &hubp_mask))
1522         return &hubp2->base;
1523 
1524     BREAK_TO_DEBUGGER();
1525     kfree(hubp2);
1526     return NULL;
1527 }
1528 
1529 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1530 {
1531     int i;
1532     uint32_t pipe_count = pool->res_cap->num_dwb;
1533 
1534     for (i = 0; i < pipe_count; i++) {
1535         struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1536                             GFP_KERNEL);
1537 
1538         if (!dwbc30) {
1539             dm_error("DC: failed to create dwbc30!\n");
1540             return false;
1541         }
1542 
1543         dcn30_dwbc_construct(dwbc30, ctx,
1544                 &dwbc30_regs[i],
1545                 &dwbc30_shift,
1546                 &dwbc30_mask,
1547                 i);
1548 
1549         pool->dwbc[i] = &dwbc30->base;
1550     }
1551     return true;
1552 }
1553 
1554 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1555 {
1556     int i;
1557     uint32_t pipe_count = pool->res_cap->num_dwb;
1558 
1559     for (i = 0; i < pipe_count; i++) {
1560         struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1561                             GFP_KERNEL);
1562 
1563         if (!mcif_wb30) {
1564             dm_error("DC: failed to create mcif_wb30!\n");
1565             return false;
1566         }
1567 
1568         dcn30_mmhubbub_construct(mcif_wb30, ctx,
1569                 &mcif_wb30_regs[i],
1570                 &mcif_wb30_shift,
1571                 &mcif_wb30_mask,
1572                 i);
1573 
1574         pool->mcif_wb[i] = &mcif_wb30->base;
1575     }
1576     return true;
1577 }
1578 
1579 static struct display_stream_compressor *dcn31_dsc_create(
1580     struct dc_context *ctx, uint32_t inst)
1581 {
1582     struct dcn20_dsc *dsc =
1583         kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1584 
1585     if (!dsc) {
1586         BREAK_TO_DEBUGGER();
1587         return NULL;
1588     }
1589 
1590     dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1591     return &dsc->base;
1592 }
1593 
1594 static void dcn315_destroy_resource_pool(struct resource_pool **pool)
1595 {
1596     struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool);
1597 
1598     dcn315_resource_destruct(dcn31_pool);
1599     kfree(dcn31_pool);
1600     *pool = NULL;
1601 }
1602 
1603 static struct clock_source *dcn31_clock_source_create(
1604         struct dc_context *ctx,
1605         struct dc_bios *bios,
1606         enum clock_source_id id,
1607         const struct dce110_clk_src_regs *regs,
1608         bool dp_clk_src)
1609 {
1610     struct dce110_clk_src *clk_src =
1611         kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1612 
1613     if (!clk_src)
1614         return NULL;
1615 
1616     if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1617             regs, &cs_shift, &cs_mask)) {
1618         clk_src->base.dp_clk_src = dp_clk_src;
1619         return &clk_src->base;
1620     }
1621 
1622     BREAK_TO_DEBUGGER();
1623     return NULL;
1624 }
1625 
1626 static bool is_dual_plane(enum surface_pixel_format format)
1627 {
1628     return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1629 }
1630 
1631 static int dcn315_populate_dml_pipes_from_context(
1632     struct dc *dc, struct dc_state *context,
1633     display_e2e_pipe_params_st *pipes,
1634     bool fast_validate)
1635 {
1636     int i, pipe_cnt;
1637     struct resource_context *res_ctx = &context->res_ctx;
1638     struct pipe_ctx *pipe;
1639     const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;
1640 
1641     DC_FP_START();
1642     dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1643     DC_FP_END();
1644 
1645     for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1646         struct dc_crtc_timing *timing;
1647 
1648         if (!res_ctx->pipe_ctx[i].stream)
1649             continue;
1650         pipe = &res_ctx->pipe_ctx[i];
1651         timing = &pipe->stream->timing;
1652 
1653         /*
1654          * Immediate flip can be set dynamically after enabling the plane.
1655          * We need to require support for immediate flip or underflow can be
1656          * intermittently experienced depending on peak b/w requirements.
1657          */
1658         pipes[pipe_cnt].pipe.src.immediate_flip = true;
1659 
1660         pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1661         pipes[pipe_cnt].pipe.src.gpuvm = true;
1662         pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1663         pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1664         pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1665         DC_FP_START();
1666         dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1667         DC_FP_END();
1668 
1669         if (pipes[pipe_cnt].dout.dsc_enable) {
1670             switch (timing->display_color_depth) {
1671             case COLOR_DEPTH_888:
1672                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1673                 break;
1674             case COLOR_DEPTH_101010:
1675                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1676                 break;
1677             case COLOR_DEPTH_121212:
1678                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1679                 break;
1680             default:
1681                 ASSERT(0);
1682                 break;
1683             }
1684         }
1685 
1686         pipe_cnt++;
1687     }
1688 
1689     if (pipe_cnt)
1690         context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1691                 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB;
1692     if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE)
1693         context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE;
1694     ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_15_DEFAULT_DET_SIZE);
1695     dc->config.enable_4to1MPC = false;
1696     if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1697         if (is_dual_plane(pipe->plane_state->format)
1698                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1699             dc->config.enable_4to1MPC = true;
1700             context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1701                     (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB;
1702         } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
1703             /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1704             context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1705             pipes[0].pipe.src.unbounded_req_mode = true;
1706         }
1707     }
1708 
1709     return pipe_cnt;
1710 }
1711 
1712 static struct dc_cap_funcs cap_funcs = {
1713     .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1714 };
1715 
1716 static struct resource_funcs dcn315_res_pool_funcs = {
1717     .destroy = dcn315_destroy_resource_pool,
1718     .link_enc_create = dcn31_link_encoder_create,
1719     .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1720     .link_encs_assign = link_enc_cfg_link_encs_assign,
1721     .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1722     .panel_cntl_create = dcn31_panel_cntl_create,
1723     .validate_bandwidth = dcn31_validate_bandwidth,
1724     .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1725     .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1726     .populate_dml_pipes = dcn315_populate_dml_pipes_from_context,
1727     .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1728     .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1729     .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1730     .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1731     .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1732     .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1733     .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1734     .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1735     .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1736     .update_bw_bounding_box = dcn315_update_bw_bounding_box,
1737     .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1738 };
1739 
1740 static bool dcn315_resource_construct(
1741     uint8_t num_virtual_links,
1742     struct dc *dc,
1743     struct dcn315_resource_pool *pool)
1744 {
1745     int i;
1746     struct dc_context *ctx = dc->ctx;
1747     struct irq_service_init_data init_data;
1748 
1749     ctx->dc_bios->regs = &bios_regs;
1750 
1751     pool->base.res_cap = &res_cap_dcn31;
1752 
1753     pool->base.funcs = &dcn315_res_pool_funcs;
1754 
1755     /*************************************************
1756      *  Resource + asic cap harcoding                *
1757      *************************************************/
1758     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1759     pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1760     pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1761     dc->caps.max_downscale_ratio = 600;
1762     dc->caps.i2c_speed_in_khz = 100;
1763     dc->caps.i2c_speed_in_khz_hdcp = 100;
1764     dc->caps.max_cursor_size = 256;
1765     dc->caps.min_horizontal_blanking_period = 80;
1766     dc->caps.dmdata_alloc_size = 2048;
1767     dc->caps.max_slave_planes = 2;
1768     dc->caps.max_slave_yuv_planes = 2;
1769     dc->caps.max_slave_rgb_planes = 2;
1770     dc->caps.post_blend_color_processing = true;
1771     dc->caps.force_dp_tps4_for_cp2520 = true;
1772     dc->caps.dp_hpo = true;
1773     dc->caps.dp_hdmi21_pcon_support = true;
1774     dc->caps.edp_dsc_support = true;
1775     dc->caps.extended_aux_timeout_support = true;
1776     dc->caps.dmcub_support = true;
1777     dc->caps.is_apu = true;
1778 
1779     /* Color pipeline capabilities */
1780     dc->caps.color.dpp.dcn_arch = 1;
1781     dc->caps.color.dpp.input_lut_shared = 0;
1782     dc->caps.color.dpp.icsc = 1;
1783     dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1784     dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1785     dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1786     dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1787     dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1788     dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1789     dc->caps.color.dpp.post_csc = 1;
1790     dc->caps.color.dpp.gamma_corr = 1;
1791     dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1792 
1793     dc->caps.color.dpp.hw_3d_lut = 1;
1794     dc->caps.color.dpp.ogam_ram = 1;
1795     // no OGAM ROM on DCN301
1796     dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1797     dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1798     dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1799     dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1800     dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1801     dc->caps.color.dpp.ocsc = 0;
1802 
1803     dc->caps.color.mpc.gamut_remap = 1;
1804     dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1805     dc->caps.color.mpc.ogam_ram = 1;
1806     dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1807     dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1808     dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1809     dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1810     dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1811     dc->caps.color.mpc.ocsc = 1;
1812 
1813     /* read VBIOS LTTPR caps */
1814     {
1815         if (ctx->dc_bios->funcs->get_lttpr_caps) {
1816             enum bp_result bp_query_result;
1817             uint8_t is_vbios_lttpr_enable = 0;
1818 
1819             bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1820             dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1821         }
1822 
1823         /* interop bit is implicit */
1824         {
1825             dc->caps.vbios_lttpr_aware = true;
1826         }
1827     }
1828 
1829     if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1830         dc->debug = debug_defaults_drv;
1831     else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1832         dc->debug = debug_defaults_diags;
1833     } else
1834         dc->debug = debug_defaults_diags;
1835     // Init the vm_helper
1836     if (dc->vm_helper)
1837         vm_helper_init(dc->vm_helper, 16);
1838 
1839     /*************************************************
1840      *  Create resources                             *
1841      *************************************************/
1842 
1843     /* Clock Sources for Pixel Clock*/
1844     pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1845             dcn31_clock_source_create(ctx, ctx->dc_bios,
1846                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1847                 &clk_src_regs[0], false);
1848     pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1849             dcn31_clock_source_create(ctx, ctx->dc_bios,
1850                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1851                 &clk_src_regs[1], false);
1852     pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1853             dcn31_clock_source_create(ctx, ctx->dc_bios,
1854                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1855                 &clk_src_regs[2], false);
1856     pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1857             dcn31_clock_source_create(ctx, ctx->dc_bios,
1858                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1859                 &clk_src_regs[3], false);
1860     pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1861             dcn31_clock_source_create(ctx, ctx->dc_bios,
1862                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1863                 &clk_src_regs[4], false);
1864 
1865     pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1866 
1867     /* todo: not reuse phy_pll registers */
1868     pool->base.dp_clock_source =
1869             dcn31_clock_source_create(ctx, ctx->dc_bios,
1870                 CLOCK_SOURCE_ID_DP_DTO,
1871                 &clk_src_regs[0], true);
1872 
1873     for (i = 0; i < pool->base.clk_src_count; i++) {
1874         if (pool->base.clock_sources[i] == NULL) {
1875             dm_error("DC: failed to create clock sources!\n");
1876             BREAK_TO_DEBUGGER();
1877             goto create_fail;
1878         }
1879     }
1880 
1881     /* TODO: DCCG */
1882     pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1883     if (pool->base.dccg == NULL) {
1884         dm_error("DC: failed to create dccg!\n");
1885         BREAK_TO_DEBUGGER();
1886         goto create_fail;
1887     }
1888 
1889     /* TODO: IRQ */
1890     init_data.ctx = dc->ctx;
1891     pool->base.irqs = dal_irq_service_dcn315_create(&init_data);
1892     if (!pool->base.irqs)
1893         goto create_fail;
1894 
1895     /* HUBBUB */
1896     pool->base.hubbub = dcn31_hubbub_create(ctx);
1897     if (pool->base.hubbub == NULL) {
1898         BREAK_TO_DEBUGGER();
1899         dm_error("DC: failed to create hubbub!\n");
1900         goto create_fail;
1901     }
1902 
1903     /* HUBPs, DPPs, OPPs and TGs */
1904     for (i = 0; i < pool->base.pipe_count; i++) {
1905         pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
1906         if (pool->base.hubps[i] == NULL) {
1907             BREAK_TO_DEBUGGER();
1908             dm_error(
1909                 "DC: failed to create hubps!\n");
1910             goto create_fail;
1911         }
1912 
1913         pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
1914         if (pool->base.dpps[i] == NULL) {
1915             BREAK_TO_DEBUGGER();
1916             dm_error(
1917                 "DC: failed to create dpps!\n");
1918             goto create_fail;
1919         }
1920     }
1921 
1922     for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1923         pool->base.opps[i] = dcn31_opp_create(ctx, i);
1924         if (pool->base.opps[i] == NULL) {
1925             BREAK_TO_DEBUGGER();
1926             dm_error(
1927                 "DC: failed to create output pixel processor!\n");
1928             goto create_fail;
1929         }
1930     }
1931 
1932     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1933         pool->base.timing_generators[i] = dcn31_timing_generator_create(
1934                 ctx, i);
1935         if (pool->base.timing_generators[i] == NULL) {
1936             BREAK_TO_DEBUGGER();
1937             dm_error("DC: failed to create tg!\n");
1938             goto create_fail;
1939         }
1940     }
1941     pool->base.timing_generator_count = i;
1942 
1943     /* PSR */
1944     pool->base.psr = dmub_psr_create(ctx);
1945     if (pool->base.psr == NULL) {
1946         dm_error("DC: failed to create psr obj!\n");
1947         BREAK_TO_DEBUGGER();
1948         goto create_fail;
1949     }
1950 
1951     /* ABM */
1952     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1953         pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1954                 &abm_regs[i],
1955                 &abm_shift,
1956                 &abm_mask);
1957         if (pool->base.multiple_abms[i] == NULL) {
1958             dm_error("DC: failed to create abm for pipe %d!\n", i);
1959             BREAK_TO_DEBUGGER();
1960             goto create_fail;
1961         }
1962     }
1963 
1964     /* MPC and DSC */
1965     pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1966     if (pool->base.mpc == NULL) {
1967         BREAK_TO_DEBUGGER();
1968         dm_error("DC: failed to create mpc!\n");
1969         goto create_fail;
1970     }
1971 
1972     for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1973         pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
1974         if (pool->base.dscs[i] == NULL) {
1975             BREAK_TO_DEBUGGER();
1976             dm_error("DC: failed to create display stream compressor %d!\n", i);
1977             goto create_fail;
1978         }
1979     }
1980 
1981     /* DWB and MMHUBBUB */
1982     if (!dcn31_dwbc_create(ctx, &pool->base)) {
1983         BREAK_TO_DEBUGGER();
1984         dm_error("DC: failed to create dwbc!\n");
1985         goto create_fail;
1986     }
1987 
1988     if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
1989         BREAK_TO_DEBUGGER();
1990         dm_error("DC: failed to create mcif_wb!\n");
1991         goto create_fail;
1992     }
1993 
1994     /* AUX and I2C */
1995     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1996         pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
1997         if (pool->base.engines[i] == NULL) {
1998             BREAK_TO_DEBUGGER();
1999             dm_error(
2000                 "DC:failed to create aux engine!!\n");
2001             goto create_fail;
2002         }
2003         pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2004         if (pool->base.hw_i2cs[i] == NULL) {
2005             BREAK_TO_DEBUGGER();
2006             dm_error(
2007                 "DC:failed to create hw i2c!!\n");
2008             goto create_fail;
2009         }
2010         pool->base.sw_i2cs[i] = NULL;
2011     }
2012 
2013     /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2014     if (!resource_construct(num_virtual_links, dc, &pool->base,
2015             (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2016             &res_create_funcs : &res_create_maximus_funcs)))
2017             goto create_fail;
2018 
2019     /* HW Sequencer and Plane caps */
2020     dcn31_hw_sequencer_construct(dc);
2021 
2022     dc->caps.max_planes =  pool->base.pipe_count;
2023 
2024     for (i = 0; i < dc->caps.max_planes; ++i)
2025         dc->caps.planes[i] = plane_cap;
2026 
2027     dc->cap_funcs = cap_funcs;
2028 
2029     dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp;
2030 
2031     return true;
2032 
2033 create_fail:
2034 
2035     dcn315_resource_destruct(pool);
2036 
2037     return false;
2038 }
2039 
2040 struct resource_pool *dcn315_create_resource_pool(
2041         const struct dc_init_data *init_data,
2042         struct dc *dc)
2043 {
2044     struct dcn315_resource_pool *pool =
2045         kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL);
2046 
2047     if (!pool)
2048         return NULL;
2049 
2050     if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool))
2051         return &pool->base;
2052 
2053     BREAK_TO_DEBUGGER();
2054     kfree(pool);
2055     return NULL;
2056 }
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