dc/dcn314/dcn314_optc.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright 2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: AMD
0024  *
0025  */
0026
0027 #ifndef __DC_OPTC_DCN314_H__
0028 #define __DC_OPTC_DCN314_H__
0029
0030 #include "dcn10/dcn10_optc.h"
0031
0032 #define OPTC_COMMON_REG_LIST_DCN3_14(inst) \
0033     SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
0034     SRI(OTG_VUPDATE_PARAM, OTG, inst),\
0035     SRI(OTG_VREADY_PARAM, OTG, inst),\
0036     SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
0037     SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
0038     SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
0039     SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
0040     SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
0041     SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
0042     SRI(OTG_H_TOTAL, OTG, inst),\
0043     SRI(OTG_H_BLANK_START_END, OTG, inst),\
0044     SRI(OTG_H_SYNC_A, OTG, inst),\
0045     SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
0046     SRI(OTG_H_TIMING_CNTL, OTG, inst),\
0047     SRI(OTG_V_TOTAL, OTG, inst),\
0048     SRI(OTG_V_BLANK_START_END, OTG, inst),\
0049     SRI(OTG_V_SYNC_A, OTG, inst),\
0050     SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
0051     SRI(OTG_CONTROL, OTG, inst),\
0052     SRI(OTG_STEREO_CONTROL, OTG, inst),\
0053     SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
0054     SRI(OTG_STEREO_STATUS, OTG, inst),\
0055     SRI(OTG_V_TOTAL_MAX, OTG, inst),\
0056     SRI(OTG_V_TOTAL_MIN, OTG, inst),\
0057     SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
0058     SRI(OTG_TRIGA_CNTL, OTG, inst),\
0059     SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
0060     SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
0061     SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
0062     SRI(OTG_STATUS, OTG, inst),\
0063     SRI(OTG_STATUS_POSITION, OTG, inst),\
0064     SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
0065     SRI(OTG_M_CONST_DTO0, OTG, inst),\
0066     SRI(OTG_M_CONST_DTO1, OTG, inst),\
0067     SRI(OTG_CLOCK_CONTROL, OTG, inst),\
0068     SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
0069     SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
0070     SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
0071     SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
0072     SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
0073     SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
0074     SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
0075     SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
0076     SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
0077     SRI(CONTROL, VTG, inst),\
0078     SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
0079     SRI(OTG_GSL_CONTROL, OTG, inst),\
0080     SRI(OTG_CRC_CNTL, OTG, inst),\
0081     SRI(OTG_CRC0_DATA_RG, OTG, inst),\
0082     SRI(OTG_CRC0_DATA_B, OTG, inst),\
0083     SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
0084     SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
0085     SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
0086     SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
0087     SR(GSL_SOURCE_SELECT),\
0088     SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
0089     SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
0090     SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
0091     SRI(OTG_GSL_WINDOW_X, OTG, inst),\
0092     SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
0093     SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
0094     SRI(OTG_DSC_START_POSITION, OTG, inst),\
0095     SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
0096     SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
0097     SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
0098     SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
0099     SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
0100     SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
0101     SRI(OTG_DRR_CONTROL, OTG, inst)
0102
0103 #define OPTC_COMMON_MASK_SH_LIST_DCN3_14(mask_sh)\
0104     SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
0105     SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
0106     SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
0107     SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
0108     SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
0109     SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
0110     SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
0111     SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
0112     SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
0113     SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
0114     SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
0115     SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
0116     SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
0117     SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
0118     SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
0119     SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
0120     SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
0121     SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
0122     SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
0123     SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
0124     SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
0125     SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
0126     SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
0127     SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
0128     SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
0129     SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
0130     SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
0131     SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
0132     SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
0133     SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
0134     SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
0135     SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
0136     SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
0137     SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
0138     SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
0139     SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
0140     SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
0141     SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
0142     SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
0143     SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
0144     SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
0145     SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
0146     SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
0147     SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
0148     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
0149     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
0150     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
0151     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
0152     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
0153     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
0154     SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
0155     SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
0156     SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
0157     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
0158     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
0159     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
0160     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
0161     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
0162     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
0163     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
0164     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
0165     SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
0166     SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
0167     SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
0168     SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
0169     SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
0170     SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
0171     SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
0172     SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
0173     SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
0174     SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
0175     SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
0176     SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
0177     SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
0178     SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
0179     SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
0180     SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
0181     SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
0182     SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
0183     SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
0184     SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
0185     SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
0186     SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
0187     SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
0188     SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
0189     SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
0190     SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
0191     SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
0192     SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
0193     SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
0194     SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
0195     SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
0196     SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
0197     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
0198     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
0199     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
0200     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
0201     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
0202     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
0203     SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
0204     SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
0205     SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
0206     SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
0207     SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
0208     SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
0209     SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
0210     SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
0211     SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
0212     SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
0213     SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
0214     SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
0215     SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
0216     SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
0217     SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
0218     SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
0219     SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
0220     SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
0221     SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
0222     SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
0223     SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
0224     SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
0225     SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
0226     SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
0227     SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
0228     SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
0229     SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
0230     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
0231     SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
0232     SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
0233     SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
0234     SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
0235     SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
0236     SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
0237     SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
0238     SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
0239     SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
0240     SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
0241     SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
0242     SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
0243     SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
0244     SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
0245     SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
0246     SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
0247     SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
0248     SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
0249     SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\
0250     SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
0251     SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
0252
0253 void dcn314_timing_generator_init(struct optc *optc1);
0254
0255 #endif /* __DC_OPTC_DCN314_H__ */