dc/dcn314/dcn314_optc.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright 2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: AMD
0024  *
0025  */
0026
0027 #include "dcn314_optc.h"
0028
0029 #include "dcn30/dcn30_optc.h"
0030 #include "dcn31/dcn31_optc.h"
0031 #include "reg_helper.h"
0032 #include "dc.h"
0033 #include "dcn_calc_math.h"
0034
0035 #define REG(reg)\
0036     optc1->tg_regs->reg
0037
0038 #define CTX \
0039     optc1->base.ctx
0040
0041 #undef FN
0042 #define FN(reg_name, field_name) \
0043     optc1->tg_shift->field_name, optc1->tg_mask->field_name
0044
0045 /*
0046  * Enable CRTC
0047  * Enable CRTC - call ASIC Control Object to enable Timing generator.
0048  */
0049
0050 static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
0051         struct dc_crtc_timing *timing)
0052 {
0053     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0054     uint32_t memory_mask = 0;
0055     int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
0056     int mpcc_hactive = h_active / opp_cnt;
0057     /* Each memory instance is 2048x(314x2) bits to support half line of 4096 */
0058     int odm_mem_count = (h_active + 2047) / 2048;
0059
0060     /*
0061      * display <= 4k : 2 memories + 2 pipes
0062      * 4k < display <= 8k : 4 memories + 2 pipes
0063      * 8k < display <= 12k : 6 memories + 4 pipes
0064      */
0065     if (opp_cnt == 4) {
0066         if (odm_mem_count <= 2)
0067             memory_mask = 0x3;
0068         else if (odm_mem_count <= 4)
0069             memory_mask = 0xf;
0070         else
0071             memory_mask = 0x3f;
0072     } else {
0073         if (odm_mem_count <= 2)
0074             memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
0075         else if (odm_mem_count <= 4)
0076             memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
0077         else
0078             memory_mask = 0x77;
0079     }
0080
0081     REG_SET(OPTC_MEMORY_CONFIG, 0,
0082         OPTC_MEM_SEL, memory_mask);
0083
0084     if (opp_cnt == 2) {
0085         REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
0086                 OPTC_NUM_OF_INPUT_SEGMENT, 1,
0087                 OPTC_SEG0_SRC_SEL, opp_id[0],
0088                 OPTC_SEG1_SRC_SEL, opp_id[1]);
0089     } else if (opp_cnt == 4) {
0090         REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
0091                 OPTC_NUM_OF_INPUT_SEGMENT, 3,
0092                 OPTC_SEG0_SRC_SEL, opp_id[0],
0093                 OPTC_SEG1_SRC_SEL, opp_id[1],
0094                 OPTC_SEG2_SRC_SEL, opp_id[2],
0095                 OPTC_SEG3_SRC_SEL, opp_id[3]);
0096     }
0097
0098     REG_UPDATE(OPTC_WIDTH_CONTROL,
0099             OPTC_SEGMENT_WIDTH, mpcc_hactive);
0100
0101     REG_UPDATE(OTG_H_TIMING_CNTL,
0102             OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
0103     optc1->opp_count = opp_cnt;
0104 }
0105
0106 static bool optc314_enable_crtc(struct timing_generator *optc)
0107 {
0108     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0109
0110     /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
0111     REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
0112             OPTC_SEG0_SRC_SEL, optc->inst);
0113
0114     /* VTG enable first is for HW workaround */
0115     REG_UPDATE(CONTROL,
0116             VTG0_ENABLE, 1);
0117
0118     REG_SEQ_START();
0119
0120     /* Enable CRTC */
0121     REG_UPDATE_2(OTG_CONTROL,
0122             OTG_DISABLE_POINT_CNTL, 2,
0123             OTG_MASTER_EN, 1);
0124
0125     REG_SEQ_SUBMIT();
0126     REG_SEQ_WAIT_DONE();
0127
0128     return true;
0129 }
0130
0131 /* disable_crtc */
0132 static bool optc314_disable_crtc(struct timing_generator *optc)
0133 {
0134     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0135
0136     /* disable otg request until end of the first line
0137      * in the vertical blank region
0138      */
0139     REG_UPDATE(OTG_CONTROL,
0140             OTG_MASTER_EN, 0);
0141
0142     REG_UPDATE(CONTROL,
0143             VTG0_ENABLE, 0);
0144
0145     /* CRTC disabled, so disable  clock. */
0146     REG_WAIT(OTG_CLOCK_CONTROL,
0147             OTG_BUSY, 0,
0148             1, 100000);
0149
0150     return true;
0151 }
0152
0153 void optc314_phantom_crtc_post_enable(struct timing_generator *optc)
0154 {
0155     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0156
0157     /* Disable immediately. */
0158     REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
0159
0160     /* CRTC disabled, so disable  clock. */
0161     REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
0162 }
0163
0164 static void optc314_set_odm_bypass(struct timing_generator *optc,
0165         const struct dc_crtc_timing *dc_crtc_timing)
0166 {
0167     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0168     enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
0169
0170     REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
0171             OPTC_NUM_OF_INPUT_SEGMENT, 0,
0172             OPTC_SEG0_SRC_SEL, optc->inst,
0173             OPTC_SEG1_SRC_SEL, 0xf,
0174             OPTC_SEG2_SRC_SEL, 0xf,
0175             OPTC_SEG3_SRC_SEL, 0xf
0176             );
0177
0178     h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
0179     REG_UPDATE(OTG_H_TIMING_CNTL,
0180             OTG_H_TIMING_DIV_MODE, h_div);
0181
0182     REG_SET(OPTC_MEMORY_CONFIG, 0,
0183             OPTC_MEM_SEL, 0);
0184     optc1->opp_count = 1;
0185 }
0186
0187 static void optc314_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
0188 {
0189     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0190
0191     REG_UPDATE(OTG_H_TIMING_CNTL,
0192             OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
0193 }
0194
0195
0196 static struct timing_generator_funcs dcn314_tg_funcs = {
0197         .validate_timing = optc1_validate_timing,
0198         .program_timing = optc1_program_timing,
0199         .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
0200         .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
0201         .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
0202         .program_global_sync = optc1_program_global_sync,
0203         .enable_crtc = optc314_enable_crtc,
0204         .disable_crtc = optc314_disable_crtc,
0205         .immediate_disable_crtc = optc31_immediate_disable_crtc,
0206         .phantom_crtc_post_enable = optc314_phantom_crtc_post_enable,
0207         /* used by enable_timing_synchronization. Not need for FPGA */
0208         .is_counter_moving = optc1_is_counter_moving,
0209         .get_position = optc1_get_position,
0210         .get_frame_count = optc1_get_vblank_counter,
0211         .get_scanoutpos = optc1_get_crtc_scanoutpos,
0212         .get_otg_active_size = optc1_get_otg_active_size,
0213         .set_early_control = optc1_set_early_control,
0214         /* used by enable_timing_synchronization. Not need for FPGA */
0215         .wait_for_state = optc1_wait_for_state,
0216         .set_blank_color = optc3_program_blank_color,
0217         .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
0218         .triplebuffer_lock = optc3_triplebuffer_lock,
0219         .triplebuffer_unlock = optc2_triplebuffer_unlock,
0220         .enable_reset_trigger = optc1_enable_reset_trigger,
0221         .enable_crtc_reset = optc1_enable_crtc_reset,
0222         .disable_reset_trigger = optc1_disable_reset_trigger,
0223         .lock = optc3_lock,
0224         .unlock = optc1_unlock,
0225         .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
0226         .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
0227         .enable_optc_clock = optc1_enable_optc_clock,
0228         .set_drr = optc31_set_drr,
0229         .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
0230         .set_vtotal_min_max = optc1_set_vtotal_min_max,
0231         .set_static_screen_control = optc1_set_static_screen_control,
0232         .program_stereo = optc1_program_stereo,
0233         .is_stereo_left_eye = optc1_is_stereo_left_eye,
0234         .tg_init = optc3_tg_init,
0235         .is_tg_enabled = optc1_is_tg_enabled,
0236         .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
0237         .clear_optc_underflow = optc1_clear_optc_underflow,
0238         .setup_global_swap_lock = NULL,
0239         .get_crc = optc1_get_crc,
0240         .configure_crc = optc2_configure_crc,
0241         .set_dsc_config = optc3_set_dsc_config,
0242         .get_dsc_status = optc2_get_dsc_status,
0243         .set_dwb_source = NULL,
0244         .set_odm_bypass = optc3_set_odm_bypass,
0245         .set_odm_combine = optc314_set_odm_combine,
0246         .get_optc_source = optc2_get_optc_source,
0247         .set_out_mux = optc3_set_out_mux,
0248         .set_drr_trigger_window = optc3_set_drr_trigger_window,
0249         .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
0250         .set_gsl = optc2_set_gsl,
0251         .set_gsl_source_select = optc2_set_gsl_source_select,
0252         .set_vtg_params = optc1_set_vtg_params,
0253         .program_manual_trigger = optc2_program_manual_trigger,
0254         .setup_manual_trigger = optc2_setup_manual_trigger,
0255         .get_hw_timing = optc1_get_hw_timing,
0256         .init_odm = optc3_init_odm,
0257         .set_odm_bypass = optc314_set_odm_bypass,
0258         .set_odm_combine = optc314_set_odm_combine,
0259         .set_h_timing_div_manual_mode = optc314_set_h_timing_div_manual_mode,
0260 };
0261
0262 void dcn314_timing_generator_init(struct optc *optc1)
0263 {
0264     optc1->base.funcs = &dcn314_tg_funcs;
0265
0266     optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
0267     optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
0268
0269     optc1->min_h_blank = 32;
0270     optc1->min_v_blank = 3;
0271     optc1->min_v_blank_interlace = 5;
0272     optc1->min_h_sync_width = 4;
0273     optc1->min_v_sync_width = 1;
0274 }
0275